Traceable Event Types

The table below lists the event types that can be traced. The performance counters for these traces can then be viewed with the PIAnalyzer Performance Counters view.

Table 1. Traceable event types
Value Trace name Description
0

(0x00)

Instruction cache miss to cachable location Instruction cache miss to a cachable location requires fetch from external memory.
1

(0x01)

Stall because instruction buffer cannot deliver Stall because the instruction buffer cannot deliver an instruction. This could indicate an Instruction Cache miss or an Instruction MicroTLB miss.

This event occurs in every cycle in which the condition is present.

2

(0x02)

Stall due to data dependency Stall because of a data dependency.

This event occurs in every cycle in which the condition is present.

3

(0x03)

Instruction MicroTLB miss Instruction MicroTLB miss.
4

(0x04)

Data MicroTLB miss Data MicroTLB miss.
5

(0x05)

Branch instruction executed Branch instruction executed, branch might or might not have changed program flow.
6

(0x06)

Branch mispredicted Branch mispredicted.
7

(0x07)

Instruction executed Instruction executed. If EVENTBUS bit [9] is HIGH, two instructions were executed in this clock cycle and the count is increments by two.

When performance counters for this trace are selected for the PIAnalyzer Performance Counters view, the MIPS graph can also be viewed.

9

(0x09)

Data cache access (cachable only) Data cache access, not including Cache operations.

This event occurs for each nonsequential access to a cache line, for cachable locations.

A

(0x0A)

Data cache access Data cache access, not including Cache Operations.

This event occurs for each nonsequential access to a cache line, regardless of whether or not the location is cachable.

B

(0x0B)

Data cache miss Data cache miss, not including Cache Operations.
C

(0x0C)

Data cache write-back Data cache write-back.

This event occurs once for each half line of four words that are written back from the cache.

D

(0x0D)

Software changed the PC

Software changed the PC.

This event occurs any time the PC is changed by software and there is not a mode change. For example, a MOV instruction with PC as the destination triggers this event.

Executing a SWI from User mode does not trigger this event, because it incurs a mode change. If EVENTBUS bit [15] is HIGH, two software PC changes occurred in this clock cycle and the count is increments by two.

F

(0x0F)

Main TLB miss Main TLB miss.
10

(0x10)

External memory request

Explicit external data accesses (Data Cache linefills, Noncachable, Write-Through).
11

(0x11)

Stall due to Load store Unit queue being full Stall because the Load Store Unit request queue is full.

This event occurs in each clock cycle in which the condition is met.

A high incidence of this event often indicates that the BCU is waiting for transactions to complete on the external bus.

12

(0x12)

Forced write buffer drain The number of times the Write Buffer was drained because of a Data Synchronization Barrier command or Strongly Ordered operation.
20

(0x20)

ETMEXTOUT[0] asserted ETMEXTOUT[0] signal was asserted for a cycle.
21

(0x21)

ETMEXTOUT[1] asserted ETMEXTOUT[1] signal was asserted for a cycle.
22

(0x22)

ETMEXTOUT asserted If both ETMEXTOUT[0] and ETMEXTOUT[1] signals are asserted then the count is incremented by two.
23

(0x23)

Procedure call instruction executed Procedure call instruction executed. The procedure return address was pushed on to the return stack.
24

(0x24)

Procedure return instruction executed Procedure return instruction executed. The procedure return address was popped off the return stack.
25

(0x25)

Procedure return instruction executed and return address predicted Procedure return instruction executed and return address predicted. The procedure return address was popped off the return stack and the core branched to this address.
26

(0x26)

Procedure return instruction executed and return address predicted incorrectly Procedure return instruction executed and return address predicted incorrectly. The procedure return address was restored to the return stack following the prediction being identified as incorrect.
FF

(0xFF)

Cycles An increment each cycle.
Related references