In ARM architecture, the saved program status register (SPSR) is a banked register in all of the exception modes (thus not in user mode or system mode). When switching the processor mode from any other mode to any of the exception modes, the value within the CPSR is stored to the SPSR so that it can be recovered after the exception (such as an interrupt) has been processed. When having performance measurement instrumentation within an interrupt, it can be useful to investigate the value within the SPSR in order to find out the mode of the processor before the interrupt.