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9 |
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10 <h2>Registers</h2> |
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11 <p>When a crash occurs, the processor state is captured and stored to a crash file. For more information on Symbian OS and ARM registers, see the reference links (ARM Architecture Manuals and Symbian OS Internals) in the end of this topic.</p> |
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12 <p>In Crash Analyser, the register values at the time of the crash are partitioned into discrete processor modes that closely mirror the ARM architecture.</p><p>The following ARM processor modes are supported:</p> |
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13 <table width="667" border="1" cellspacing="1" cellpadding="2"> |
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14 <colgroup> |
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15 <col width="50*"> |
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16 <col width="141*"></colgroup> |
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17 <thead> |
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18 <tr> |
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19 <td><b>Name</b></td> |
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20 <td><b>Description</b></td> |
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21 </tr> |
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22 </thead> |
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23 <tbody> |
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24 <tr> |
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25 <td>User</td> |
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26 <td> Contains registers associated with the processor whilst it was executing in USER mode. This is the normal execution mode for ARM processors.</td> |
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27 </tr> |
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28 <tr> |
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29 <td>Fast Interrupt (FIQ)</td> |
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30 <td>Registers that are associated with ARM FIQ mode, a privileged mode in which is used for high speed low latency interrupt handling.</td> |
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31 </tr> |
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32 <tr> |
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33 <td>Interrupt (IRQ)</td> |
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34 <td>General purpose ARM interrupt handling mode.</td> |
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35 </tr> |
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36 <tr> |
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37 <td>Supervisor </td> |
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38 <td>Registers that are associated with code executing within the context of the Symbian OS kernel. </td> |
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39 </tr> |
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40 <tr> |
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41 <td>Abort</td> |
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42 <td>Typically used when the processor was unable to access a memory area.</td> |
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43 </tr> |
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44 <tr> |
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45 <td>Undefined</td> |
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46 <td>Indicates that the processor could not interpret an instruction.</td> |
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47 </tr> |
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48 <tr> |
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49 <td>System</td> |
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50 <td>Not used in Symbian OS.</td> |
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51 </tr> |
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52 </tbody> |
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53 </table> |
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54 |
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55 <p>Additionally the ARM banks are supplemented by:</p> |
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56 <table width="667" border="1" cellspacing="1" cellpadding="2"> |
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57 <colgroup> |
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58 <col width="50*"> |
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59 <col width="141*"></colgroup> |
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60 <thead> |
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61 <tr> |
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62 <td><b>Name</b></td> |
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63 <td><b>Description</b></td> |
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64 </tr> |
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65 <tr> |
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66 <td>Exception</td> |
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67 <td>Contains exception-specific registers, such as the exception code relevant to the exception that occurred.</td> |
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68 </tr> |
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69 <tr> |
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70 <td>Co-processor</td> |
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71 <td>Contains co-processor registers, such as the fault status register.</td> |
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72 </tr> |
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73 </thead> |
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74 <tbody> |
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75 <tr> |
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76 <td></td> |
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77 <td></td> |
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78 </tr> |
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79 </tbody> |
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80 </table> |
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81 |
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82 <p>The ARM register modes typically support a register range of R00 to R15. R13, R14 and R15 have special meaning:</p> |
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83 <table width="667" border="1" cellspacing="1" cellpadding="2"> |
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84 <colgroup> |
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85 <col width="50*"> |
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86 <col width="141*"></colgroup> |
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87 <thead> |
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88 <tr> |
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89 <td><b>Name</b></td> |
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90 <td><b>Description</b></td> |
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91 </tr> |
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92 <tr> |
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93 <td>R13</td> |
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94 <td>Current stack pointer. Adjusted as data is pushed and popped from the stack. </td> |
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95 </tr> |
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96 </thead> |
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97 <tbody> |
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98 <tr> |
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99 <td>R14</td> |
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100 <td>Otherwise known as the link register (LR). Contains the address of the instruction to branch to after returning from a subroutine. Can also contain the address to return to after the processor enters an exception mode (for example Abort, Supervisor, FIQ, IRQ etc).</td> |
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101 </tr> |
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102 <tr> |
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103 <td>R15</td> |
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104 <td>Register 15 is the Program Counter (PC). It can be used in most instructions as a pointer to the instruction which is two instructions after the instruction being executed.</td> |
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105 </tr> |
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106 </tbody> |
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107 </table> |
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108 |
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109 <p>Additionally, some register values are preserved when the processor transitions from one execution mode to another (for example, when the process transitions from User to Supervisor mode in order to fulfill a privileged operation). Full details about this preservation or “banking” are described in ARM Architecture Manuals. See the link below.</p> |
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110 <p>Finally, the CPSR, or Current Program Status Register is also noteworthy. It is one of several Status Registers that is used to hold details about the current state of the processor at the time of a crash. For example, it can indicate if the processor was executing an ARM or THUMB instruction, or whether interrupts were disabled. Most critically, it describes the execution mode of the processor at the time of the panic/exception – for example, did the exception occur whilst the processor was executing kernel code (Supervisor Mode) or user code (User Mode)?</p> |
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111 <p>Function call arguments are typically passed to the function within register values (were possible, depending on argument type and number of arguments). If a function signature contains too many arguments then the registers may be supplemented by the stack (arguments are pushed on the stack by the function caller and popped of the stack by the function itself). Typically R00 to R03 are used for function passing.</p> |
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112 <p> Additionally, R00 is often utilized as the “this” pointer when performing method dispatch on an object. A common related problem can be de-referencing a null this pointer or then de-referencing a deleted object in order to invoke a method. Both issues can often be identified based upon the value of the program counter (R15) and the value of R00 (for example is it 0x00000000).</p> |
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113 <p>For reference information, see the following references:</p> |
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114 <ul> |
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115 <li>ARM EABI: <a href="http://www.arm.com/products/DevTools/ABI.html"> http://www.arm.com/products/DevTools/ABI.html</a></li> |
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116 <li>ARM Architecture Manuals: <a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0100i/ http://www.arm.com/pdfs/ARMv6_Architecture.pdf">http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0100i/ http://www.arm.com/pdfs/ARMv6_Architecture.pdf</a></li> |
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117 <li>Symbian OS Internals: <a href="http://www.amazon.com/Symbian-OS-Internals-Real-time-Programming/dp/0470025247">http://www.amazon.com/Symbian-OS-Internals-Real-time-Programming/dp/0470025247</a></li> |
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118 </ul> |
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119 |
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