1 <h1>Exceptions</h1>

     2 <p>Exceptions are generated by internal and external sources to cause the processor to handle an event, such as

     3 an externally generated interrupt or an attempt to execute an Undefined instruction. The processor state just

     4 before handling the exception is normally preserved so that the original program can be resumed when the

     5 exception routine has completed. More than one exception can arise at the same time.</p>

     6 <p>The ARM architecture supports seven types of exception. When an exception occurs, execution is forced from a fixed

     7 memory address corresponding to the type of exception. These fixed addresses are called the exception

     8 vectors.</p>

     9 <code>Reset</code>

    10 <p>When the Reset input is asserted on the processor, the ARM processor immediately stops execution of the

    11 current instruction. When Reset is de-asserted, the following actions are performed:</p>

    12 <code>R14_svc = UNPREDICTABLE value<br>

    13 SPSR_svc = UNPREDICTABLE value<br>

    14 CPSR[4:0] = 0b10011 /* Enter Supervisor mode */<br>

    15 CPSR[5] = 0 /* Execute in ARM state */<br>

    16 CPSR[6] = 1 /* Disable fast interrupts */<br>

    17 CPSR[7] = 1 /* Disable normal interrupts */<br>

    18 CPSR[8] = 1 /* Disable Imprecise Aborts (v6 only) */<br>

    19 CPSR[9] = CP15_reg1_EEbit /* Endianness on exception entry */<br>

    20 if high vectors configured then<br>

    21 PC = 0xFFFF0000<br>

    22 else<br>

    23 PC = 0x00000000</code><br>

    24 <p>

    25 After Reset, the ARM processor begins execution at address 0x00000000 or 0xFFFF0000 in Supervisor mode

    26 with interrupts disabled.</p>

    27 <code>Undefined Instruction exception</code>

    28 <p>

    29 If the ARM processor executes a coprocessor instruction, it waits for any external coprocessor

    30 to acknowledge that it can execute the instruction. If no coprocessor responds, an Undefined Instruction

    31 exception occurs.</p><p>

    32 If an attempt is made to execute an instruction that is UNDEFINED, an Undefined Instruction exception occurs.</p><p>

    33 The Undefined Instruction exception can be used for software emulation of a coprocessor in a system that

    34 does not have the physical coprocessor (hardware), or for general-purpose instruction set extension by

    35 software emulation.</p><p>

    36 When an Undefined Instruction exception occurs, the following actions are performed:

    37 </p><code>

    38 R14_und = address of next instruction after the Undefined instruction<br>

    39 SPSR_und = CPSR<br>

    40 CPSR[4:0] = 0b11011 /* Enter Undefined Instruction mode */<br>

    41 CPSR[5] = 0 /* Execute in ARM state */<br>

    42 /* CPSR[6] is unchanged */<br>

    43 CPSR[7] = 1 /* Disable normal interrupts */<br>

    44 /* CPSR[8] is unchanged */<br>

    45 CPSR[9] = CP15_reg1_EEbit /* Endianness on exception entry */<br>

    46 if high vectors configured then<br>

    47 PC = 0xFFFF0004<br>

    48 else<br>

    49 PC = 0x00000004</code>

    50 <p>To return after emulating the Undefined instruction use:</p>

    51 <code>

    52 MOVS PC,R14

    53 </code>

    54 <p>

    55 This restores the PC (from R14_und) and CPSR (from SPSR_und) and returns to the instruction following

    56 the Undefined instruction.</p><p>

    57 In some coprocessor designs, an internal exceptional condition caused by one coprocessor instruction is

    58 signaled imprecisely by refusing to respond to a later coprocessor instruction. In these circumstances, the

    59 Undefined Instruction handler takes whatever action is necessary to clear the exceptional condition, then

    60 returns to the second coprocessor instruction. To do this use:

    61 </p><code>

    62 SUBS PC,R14,#4

    63 </code>

    64 <code>Software Interrupt exception</code>

    65 <p>

    66 The Software Interrupt instruction (SWI) enters Supervisor mode to request a particular supervisor (operating

    67 system) function. When a SWI is executed, the following actions are performed:

    68 </p><code>

    69 R14_svc = address of next instruction after the SWI instruction<br>

    70 SPSR_svc = CPSR<br>

    71 CPSR[4:0] = 0b10011 /* Enter Supervisor mode */<br>

    72 CPSR[5] = 0 /* Execute in ARM state */<br>

    73 /* CPSR[6] is unchanged */<br>

    74 CPSR[7] = 1 /* Disable normal interrupts */<br>

    75 /* CPSR[8] is unchanged */<br>

    76 CPSR[9] = CP15_reg1_EEbit /* Endianness on exception entry */<br>

    77 if high vectors configured then<br>

    78 PC = 0xFFFF0008<br>

    79 else<br>

    80 PC = 0x00000008</code>

    81 <p>

    82 To return after performing the SWI operation, use the following instruction to restore the PC

    83 (from R14_svc) and CPSR (from SPSR_svc) and return to the instruction following the SWI:

    84 </p><code>

    85 MOVS PC,R14

    86 </code>

    87 <code>Prefetch Abort</code>

    88 <p>

    89 A memory abort is signaled by the memory system. Activating an abort in response to an instruction fetch

    90 marks the fetched instruction as invalid. A Prefetch Abort exception is generated if the processor tries to

    91 execute the invalid instruction. If the instruction is not executed (for example, as a result of a branch being

    92 taken while it is in the pipeline), no Prefetch Abort occurs.</p><p>

    93 In ARMv5 and above, a Prefetch Abort exception can also be generated as the result of executing a BKPT

    94 instruction.</p><p>

    95 When an attempt is made to execute an aborted instruction, the following actions are performed:

    96 </p><code>

    97 R14_abt = address of the aborted instruction + 4<br>

    98 SPSR_abt = CPSR<br>

    99 CPSR[4:0] = 0b10111 /* Enter Abort mode */<br>

   100 CPSR[5] = 0 /* Execute in ARM state */<br>

   101 /* CPSR[6] is unchanged */<br>

   102 CPSR[7] = 1 /* Disable normal interrupts */<br>

   103 CPSR[8] = 1 /* Disable Imprecise Data Aborts (v6 only) */<br>

   104 CPSR[9] = CP15_reg1_EEbit /* Endianness on exception entry */<br>

   105 if high vectors configured then<br>

   106 PC = 0xFFFF000C<br>

   107 else<br>

   108 PC = 0x0000000C</code>

   109 <p>

   110 To return after fixing the reason for the abort, use:

   111 </p><code>

   112 SUBS PC,R14,#4

   113 </code><p>

   114 This restores both the PC (from R14_abt) and CPSR (from SPSR_abt), and returns to the aborted

   115 instruction.

   116 </p>

   117 <code>Data Abort</code>

   118 <p>

   119 A memory abort is signaled by the memory system. Activating an abort in response to a data access (load

   120 or store) marks the data as invalid. A Data Abort exception occurs before any following instructions or

   121 exceptions have altered the state of the CPU. The following actions are performed:

   122 </p><code>

   123 R14_abt = address of the aborted instruction + 8<br>

   124 SPSR_abt = CPSR<br>

   125 CPSR[4:0] = 0b10111 /* Enter Abort mode */<br>

   126 CPSR[5] = 0 /* Execute in ARM state */<br>

   127 /* CPSR[6] is unchanged */<br>

   128 CPSR[7] = 1 /* Disable normal interrupts */<br>

   129 CPSR[8] = 1 /* Disable Imprecise Data Aborts (v6 only) */<br>

   130 CPSR[9] = CP15_reg1_EEbit /* Endianness on exception entry */<br>

   131 if high vectors configured then<br>

   132 PC = 0xFFFF0010<br>

   133 else<br>

   134 PC = 0x00000010

   135 </code><p>

   136 To return after fixing the reason for the abort use:

   137 </p><code>

   138 SUBS PC,R14,#8

   139 </code><p>

   140 This restores both the PC (from R14_abt) and CPSR (from SPSR_abt), and returns to re-execute the aborted

   141 instruction.</p><p>

   142 If the aborted instruction does not need to be re-executed use:

   143 </p><code>

   144 SUBS PC,R14,#4

   145 </code>

   146 <code>IRQ</code>

   147 <p>

   148 The IRQ exception is generated externally by asserting the IRQ input on the processor. It has a lower priority

   149 than FIQ, and is masked out when an FIQ sequence is entered.</p><p>

   150 Interrupts are disabled when the I bit in the CPSR is set. If the I bit is clear, ARM checks for an IRQ at

   151 instruction boundaries.</p><p>

   152 When an IRQ is detected, the following actions are performed:

   153 </p><code>

   154 R14_irq = address of next instruction to be executed + 4<br>

   155 SPSR_irq = CPSR<br>

   156 CPSR[4:0] = 0b10010 /* Enter IRQ mode */<br>

   157 CPSR[5] = 0 /* Execute in ARM state */<br>

   158 /* CPSR[6] is unchanged */<br>

   159 CPSR[7] = 1 /* Disable normal interrupts */<br>

   160 CPSR[8] = 1 /* Disable Imprecise Data Aborts (v6 only) */<br>

   161 CPSR[9] = CP15_reg1_EEbit /* Endianness on exception entry */<br>

   162 if VE==0 then<br>

   163 if high vectors configured then<br>

   164 PC = 0xFFFF0018<br>

   165 else<br>

   166 PC = 0x00000018<br>

   167 else<br>

   168 PC = IMPLEMENTATION DEFINED

   169 </code><p>To return after servicing the interrupt, use:</p><code>

   170 SUBS PC,R14,#4

   171 </code><p>This restores both the PC (from R14_irq) and CPSR (from SPSR_irq), and resumes execution of the

   172 interrupted code.</p>

   173 <code>FIQ</code>

   174 <p>

   175 The FIQ exception is generated externally by asserting the FIQ input on the processor. FIQ is designed to

   176 support a data transfer or channel process, and has sufficient private registers to remove the need for register

   177 saving in such applications, therefore minimizing the overhead of context switching.</p><p>

   178 Fast interrupts are disabled when the F bit in the CPSR is set. If the F bit is clear, ARM checks for an FIQ

   179 at instruction boundaries.</p><p>

   180 When an FIQ is detected, the following actions are performed:

   181 </p><code>

   182 R14_fiq = address of next instruction to be executed + 4<br>

   183 SPSR_fiq = CPSR<br>

   184 CPSR[4:0] = 0b10001 /* Enter FIQ mode */<br>

   185 CPSR[5] = 0 /* Execute in ARM state */<br>

   186 CPSR[6] = 1 /* Disable fast interrupts */<br>

   187 CPSR[7] = 1 /* Disable normal interrupts */<br>

   188 CPSR[8] = 1 /* Disable Imprecise Data Aborts (v6 only) */<br>

   189 CPSR[9] = CP15_reg1_EEbit /* Endianness on exception entry */<br>

   190 if VE==0 then<br>

   191 if high vectors configured then<br>

   192 PC = 0xFFFF001C<br>

   193 else<br>

   194 PC = 0x0000001C<br>

   195 else<br>

   196 PC = IMPLEMENTATION DEFINED

   197 </code><p>To return after servicing the interrupt, use:</p><code>

   198 SUBS PC, R14,#4

   199 </code><p>

   200 This restores both the PC (from R14_fiq) and CPSR (from SPSR_fiq), and resumes execution of the

   201 interrupted code.</p><p>

   202 The FIQ vector is deliberately the last vector to allow the FIQ exception-handler software to be placed

   203 directly at address 0x0000001C or 0xFFFF001C, without requiring a branch instruction from the vector.

   204 </p>