|
1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" |
|
2 "http://www.w3.org/TR/html4/loose.dtd"> |
|
3 <html> |
|
4 <head> |
|
5 <meta http-equiv="content-type" content="text/html; charset=UTF-8"> |
|
6 <title>Traceable Event Types</title> |
|
7 <link href="../../../book.css" rel="stylesheet" type="text/css"> |
|
8 <style type="text/css"> |
|
9 <!-- |
|
10 .style1 { |
|
11 font-family: Georgia, "Times New Roman", Times, serif; |
|
12 font-weight: bold; |
|
13 } |
|
14 --> |
|
15 |
|
16 </style> |
|
17 </head> |
|
18 |
|
19 <body> |
|
20 <h2>Traceable Event Types </h2> |
|
21 |
|
22 <p>The table below lists the event types that can be traced. The performance |
|
23 counters for these traces can then be viewed with the PIAnalyzer Performance |
|
24 Counters view.</p> |
|
25 |
|
26 <h5>Table 1. Traceable event types</h5> |
|
27 |
|
28 <table width="80%" border="0" cellpadding="2" cellspacing="0"> |
|
29 <tbody> |
|
30 <tr> |
|
31 <th width="10%" scope="col">Value</th> |
|
32 <th width="25%" scope="col">Trace name</th> |
|
33 <th width="65%" scope="col">Description</th> |
|
34 </tr> |
|
35 <tr> |
|
36 <td>0 |
|
37 |
|
38 <p>(0x00)</p> |
|
39 </td> |
|
40 <td>Instruction cache miss to cachable location</td> |
|
41 <td>Instruction cache miss to a cachable location requires fetch from |
|
42 external memory.</td> |
|
43 </tr> |
|
44 <tr> |
|
45 <td>1 |
|
46 |
|
47 <p>(0x01) </p> |
|
48 </td> |
|
49 <td>Stall because instruction buffer cannot deliver</td> |
|
50 <td>Stall because the instruction buffer cannot deliver an instruction. |
|
51 This could indicate an Instruction Cache miss or an Instruction |
|
52 MicroTLB miss. |
|
53 |
|
54 <p>This event occurs in every cycle in which the condition is |
|
55 present.</p> |
|
56 </td> |
|
57 </tr> |
|
58 <tr> |
|
59 <td>2 |
|
60 |
|
61 <p>(0x02) </p> |
|
62 </td> |
|
63 <td>Stall due to data dependency</td> |
|
64 <td>Stall because of a data dependency. |
|
65 |
|
66 <p>This event occurs in every cycle in which the condition is |
|
67 present.</p> |
|
68 </td> |
|
69 </tr> |
|
70 <tr> |
|
71 <td>3 |
|
72 |
|
73 <p>(0x03) </p> |
|
74 </td> |
|
75 <td>Instruction MicroTLB miss</td> |
|
76 <td>Instruction MicroTLB miss.</td> |
|
77 </tr> |
|
78 <tr> |
|
79 <td>4 |
|
80 |
|
81 <p>(0x04) </p> |
|
82 </td> |
|
83 <td>Data MicroTLB miss</td> |
|
84 <td>Data MicroTLB miss.</td> |
|
85 </tr> |
|
86 <tr> |
|
87 <td>5 |
|
88 |
|
89 <p>(0x05)</p> |
|
90 </td> |
|
91 <td>Branch instruction executed</td> |
|
92 <td>Branch instruction executed, branch might or might not have changed |
|
93 program flow.</td> |
|
94 </tr> |
|
95 <tr> |
|
96 <td>6 |
|
97 |
|
98 <p>(0x06) </p> |
|
99 </td> |
|
100 <td>Branch mispredicted</td> |
|
101 <td>Branch mispredicted.</td> |
|
102 </tr> |
|
103 <tr> |
|
104 <td>7 |
|
105 |
|
106 <p>(0x07) </p> |
|
107 </td> |
|
108 <td>Instruction executed</td> |
|
109 <td>Instruction executed. If EVENTBUS bit [9] is HIGH, two instructions |
|
110 were executed in this clock cycle and the count is increments by two. |
|
111 |
|
112 <p>When performance counters for this trace are selected for the |
|
113 PIAnalyzer Performance Counters view, the MIPS graph can also be |
|
114 viewed.</p> |
|
115 </td> |
|
116 </tr> |
|
117 <tr> |
|
118 <td>9 |
|
119 |
|
120 <p>(0x09) </p> |
|
121 </td> |
|
122 <td>Data cache access (cachable only)</td> |
|
123 <td>Data cache access, not including Cache operations. |
|
124 |
|
125 <p>This event occurs for each nonsequential access to a cache line, for |
|
126 cachable locations.</p> |
|
127 </td> |
|
128 </tr> |
|
129 <tr> |
|
130 <td>A |
|
131 |
|
132 <p>(0x0A) </p> |
|
133 </td> |
|
134 <td>Data cache access</td> |
|
135 <td>Data cache access, not including Cache Operations. |
|
136 |
|
137 <p>This event occurs for each nonsequential access to a cache line, |
|
138 regardless of whether or not the location is cachable.</p> |
|
139 </td> |
|
140 </tr> |
|
141 <tr> |
|
142 <td>B |
|
143 |
|
144 <p>(0x0B) </p> |
|
145 </td> |
|
146 <td>Data cache miss</td> |
|
147 <td>Data cache miss, not including Cache Operations.</td> |
|
148 </tr> |
|
149 <tr> |
|
150 <td>C |
|
151 |
|
152 <p>(0x0C) </p> |
|
153 </td> |
|
154 <td>Data cache write-back</td> |
|
155 <td>Data cache write-back. |
|
156 |
|
157 <p>This event occurs once for each half line of four words that are |
|
158 written back from the cache.</p> |
|
159 </td> |
|
160 </tr> |
|
161 <tr> |
|
162 <td>D |
|
163 |
|
164 <p>(0x0D) </p> |
|
165 </td> |
|
166 <td><p>Software changed the PC</p> |
|
167 </td> |
|
168 <td>Software changed the PC. |
|
169 |
|
170 <p>This event occurs any time the PC is changed by software and there |
|
171 is not a mode change. For example, a MOV instruction with PC as the |
|
172 destination triggers this event.</p> |
|
173 |
|
174 <p>Executing a SWI from User mode does not trigger this event, because |
|
175 it incurs a mode change. If EVENTBUS bit [15] is HIGH, two software PC |
|
176 changes occurred in this clock cycle and the count is increments by |
|
177 two.</p> |
|
178 </td> |
|
179 </tr> |
|
180 <tr> |
|
181 <td>F |
|
182 |
|
183 <p>(0x0F) </p> |
|
184 </td> |
|
185 <td>Main TLB miss</td> |
|
186 <td>Main TLB miss.</td> |
|
187 </tr> |
|
188 <tr> |
|
189 <td>10 |
|
190 |
|
191 <p>(0x10) </p> |
|
192 </td> |
|
193 <td><p>External memory request</p> |
|
194 </td> |
|
195 <td>Explicit external data accesses (Data Cache linefills, Noncachable, |
|
196 Write-Through).</td> |
|
197 </tr> |
|
198 <tr> |
|
199 <td>11 |
|
200 |
|
201 <p>(0x11) </p> |
|
202 </td> |
|
203 <td>Stall due to Load store Unit queue being full</td> |
|
204 <td>Stall because the Load Store Unit request queue is full. |
|
205 |
|
206 <p>This event occurs in each clock cycle in which the condition is |
|
207 met.</p> |
|
208 |
|
209 <p>A high incidence of this event often indicates that the BCU is |
|
210 waiting for transactions to complete on the external bus.</p> |
|
211 </td> |
|
212 </tr> |
|
213 <tr> |
|
214 <td>12 |
|
215 |
|
216 <p>(0x12) </p> |
|
217 </td> |
|
218 <td>Forced write buffer drain</td> |
|
219 <td>The number of times the Write Buffer was drained because of a Data |
|
220 Synchronization Barrier command or Strongly Ordered operation.</td> |
|
221 </tr> |
|
222 <tr> |
|
223 <td>20 |
|
224 |
|
225 <p>(0x20) </p> |
|
226 </td> |
|
227 <td>ETMEXTOUT[0] asserted</td> |
|
228 <td>ETMEXTOUT[0] signal was asserted for a cycle.</td> |
|
229 </tr> |
|
230 <tr> |
|
231 <td>21 |
|
232 |
|
233 <p>(0x21)</p> |
|
234 </td> |
|
235 <td>ETMEXTOUT[1] asserted</td> |
|
236 <td>ETMEXTOUT[1] signal was asserted for a cycle.</td> |
|
237 </tr> |
|
238 <tr> |
|
239 <td>22 |
|
240 |
|
241 <p>(0x22)</p> |
|
242 </td> |
|
243 <td>ETMEXTOUT asserted</td> |
|
244 <td>If both ETMEXTOUT[0] and ETMEXTOUT[1] signals are asserted then the |
|
245 count is incremented by two.</td> |
|
246 </tr> |
|
247 <tr> |
|
248 <td>23 |
|
249 |
|
250 <p>(0x23)</p> |
|
251 </td> |
|
252 <td>Procedure call instruction executed</td> |
|
253 <td>Procedure call instruction executed. The procedure return address was |
|
254 pushed on to the return stack.</td> |
|
255 </tr> |
|
256 <tr> |
|
257 <td>24 |
|
258 |
|
259 <p>(0x24)</p> |
|
260 </td> |
|
261 <td>Procedure return instruction executed</td> |
|
262 <td>Procedure return instruction executed. The procedure return address |
|
263 was popped off the return stack.</td> |
|
264 </tr> |
|
265 <tr> |
|
266 <td>25 |
|
267 |
|
268 <p>(0x25)</p> |
|
269 </td> |
|
270 <td>Procedure return instruction executed and return address |
|
271 predicted</td> |
|
272 <td>Procedure return instruction executed and return address predicted. |
|
273 The procedure return address was popped off the return stack and the |
|
274 core branched to this address.</td> |
|
275 </tr> |
|
276 <tr> |
|
277 <td>26 |
|
278 |
|
279 <p>(0x26)</p> |
|
280 </td> |
|
281 <td>Procedure return instruction executed and return address predicted |
|
282 incorrectly</td> |
|
283 <td>Procedure return instruction executed and return address predicted |
|
284 incorrectly. The procedure return address was restored to the return |
|
285 stack following the prediction being identified as incorrect.</td> |
|
286 </tr> |
|
287 <tr> |
|
288 <td>FF |
|
289 |
|
290 <p>(0xFF) </p> |
|
291 </td> |
|
292 <td>Cycles</td> |
|
293 <td>An increment each cycle.</td> |
|
294 </tr> |
|
295 </tbody> |
|
296 </table> |
|
297 |
|
298 <h5>Related references</h5> |
|
299 <ul> |
|
300 <li><a |
|
301 href="../../reference/analyzer/view_performance_counters.htm">Performance |
|
302 Counters View</a></li> |
|
303 <li><a href="../../reference/profiler/Prof_counter_settings.htm">PIProfiler |
|
304 Performance Counter Settings</a></li> |
|
305 </ul> |
|
306 |
|
307 <div id="footer"> |
|
308 Copyright © 2010 Nokia Corporation and/or its subsidiary(-ies). All rights |
|
309 reserved. <br> |
|
310 License: <a |
|
311 href="http://www.eclipse.org/legal/epl-v10.html">http://www.eclipse.org/legal/epl-v10.html</a></div> |
|
312 </body> |
|
313 </html> |