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1 /* |
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2 * Copyright (c) 2009 Nokia Corporation and/or its subsidiary(-ies). |
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3 * All rights reserved. |
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4 * This component and the accompanying materials are made available |
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5 * under the terms of "Eclipse Public License v1.0" |
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6 * which accompanies this distribution, and is available |
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7 * at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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8 * |
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9 * Initial Contributors: |
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10 * Nokia Corporation - initial contribution. |
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11 * |
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12 * Contributors: |
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13 * |
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14 * Description: |
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15 * |
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16 */ |
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17 using System; |
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18 using System.Text; |
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19 using System.Collections.Generic; |
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20 using CrashItemLib.Crash; |
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21 using CrashItemLib.Crash.Base; |
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22 using CrashItemLib.Crash.Messages; |
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23 using CrashItemLib.Crash.Container; |
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24 using CrashItemLib.Crash.Threads; |
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25 using SymbianUtils.Range; |
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26 using SymbianStructuresLib.Arm.Registers; |
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27 using CrashItemLib.Crash.Registers.Visualization; |
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28 using CrashItemLib.Crash.Registers.Visualization.Bits; |
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29 using CrashItemLib.Crash.Registers.Visualization.Utilities; |
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30 |
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31 namespace CrashItemLib.Crash.Registers.Special |
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32 { |
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33 public class CIRegisterCPSR : CIRegister, ICIRegisterVisualizerVisitor |
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34 { |
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35 #region Constructors |
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36 public CIRegisterCPSR( CIRegisterList aCollection, uint aValue ) |
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37 : base( aCollection, TArmRegisterType.EArmReg_CPSR, aValue ) |
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38 { |
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39 PrepareMessage(); |
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40 // |
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41 CIRegisterVisualization modeARMv5 = new CIRegisterVisualization( this, this, KVisMode_ARMv5 ); |
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42 this.AddChild( modeARMv5 ); |
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43 modeARMv5.Refresh(); |
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44 // |
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45 CIRegisterVisualization modeARMv6 = new CIRegisterVisualization( this, this, KVisMode_ARMv6 ); |
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46 this.AddChild( modeARMv6 ); |
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47 modeARMv6.Refresh(); |
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48 } |
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49 #endregion |
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50 |
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51 #region API |
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52 #endregion |
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53 |
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54 #region Properties |
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55 public TArmRegisterBank ProcessorMode |
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56 { |
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57 get |
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58 { |
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59 TArmRegisterBank bank = ArmRegisterBankUtils.ExtractBank( this.Value ); |
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60 return bank; |
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61 } |
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62 } |
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63 #endregion |
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64 |
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65 #region Internal constants |
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66 private const string KVisMode_ARMv5 = "CPSR (ARMv5)"; |
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67 private const string KVisMode_ARMv6 = "CPSR (ARMv6)"; |
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68 #endregion |
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69 |
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70 #region ICIRegisterVisualizerVisitor Members |
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71 void ICIRegisterVisualizerVisitor.Build( CIRegisterVisualization aVisualization ) |
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72 { |
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73 aVisualization.Clear(); |
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74 // |
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75 switch ( aVisualization.Description ) |
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76 { |
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77 default: |
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78 case KVisMode_ARMv5: |
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79 PrepareVisARMv5( aVisualization ); |
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80 break; |
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81 case KVisMode_ARMv6: |
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82 PrepareVisARMv6( aVisualization ); |
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83 break; |
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84 } |
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85 } |
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86 #endregion |
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87 |
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88 #region Internal constants |
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89 private const string KReserved = "Reserved"; |
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90 #endregion |
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91 |
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92 #region Internal methods |
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93 private void PrepareMessage() |
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94 { |
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95 CIMessage message = CIMessage.NewMessage( Container ); |
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96 message.Title = "Processor Mode"; |
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97 message.Description = string.Format( "CPSR (Current Processor Status Register) indicates that the processor was in [{0}] mode.", |
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98 ArmRegisterBankUtils.BankAsStringLong( ProcessorMode ) ); |
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99 base.AddChild( message ); |
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100 } |
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101 |
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102 private void PrepareVisARMv5( CIRegisterVisualization aVisualization ) |
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103 { |
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104 AddBits0To8( aVisualization, true ); |
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105 AddEndianness( aVisualization, true ); |
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106 |
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107 // These bits are always reserved - "########", "########", "111111##", "########" |
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108 AddReserved( aVisualization, 10, 15 ); |
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109 |
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110 // GE[3:0] bits - reserved in ARMv5 - "########", "####1111", "########", "########" |
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111 AddReserved( aVisualization, 16, 19 ); |
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112 |
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113 // These bits are always reserved - "########", "1111####", "########", "########" |
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114 AddReserved( aVisualization, 20, 23 ); |
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115 |
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116 // Jazelle bit |
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117 AddJazelle( aVisualization, true ); |
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118 |
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119 // These bits are always reserved - "#####11#", "########", "########", "########" |
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120 AddReserved( aVisualization, 25, 26 ); |
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121 |
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122 // Reserved bit - Q flag, ARMv5E only. Indicates "overflow and/or saturation has occurred..." |
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123 AddQFlag( aVisualization, true ); |
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124 |
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125 // Condition code flags |
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126 AddConditionCodeFlags( aVisualization ); |
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127 } |
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128 |
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129 private void PrepareVisARMv6( CIRegisterVisualization aVisualization ) |
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130 { |
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131 AddBits0To8( aVisualization, false ); |
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132 AddEndianness( aVisualization, false ); |
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133 |
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134 // These bits are always reserved - "########", "########", "111111##", "########" |
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135 AddReserved( aVisualization, 10, 15 ); |
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136 |
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137 // GE[3:0] bits - reserved in ARMv5 - "########", "####1111", "########", "########" |
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138 AddBitRange( aVisualization, 16, 19, "Greater than or Equal (SIMD)" ); |
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139 |
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140 // These bits are always reserved - "########", "1111####", "########", "########" |
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141 AddReserved( aVisualization, 20, 23 ); |
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142 |
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143 // Jazelle bit |
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144 AddJazelle( aVisualization, false ); |
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145 |
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146 // These bits are always reserved - "#####11#", "########", "########", "########" |
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147 AddReserved( aVisualization, 25, 26 ); |
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148 |
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149 // Reserved bit - Q flag, ARMv5E only. Indicates "overflow and/or saturation has occurred..." |
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150 AddQFlag( aVisualization, false ); |
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151 |
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152 // Condition code flags |
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153 AddConditionCodeFlags( aVisualization ); |
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154 } |
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155 |
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156 private void AddBits0To8( CIRegisterVisualization aVisualization, bool aIsIABitReserved ) |
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157 { |
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158 uint value = aVisualization.Register.Value; |
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159 |
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160 // Processor mode |
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161 CIRegisterVisBitRange rangeProcMode = new CIRegisterVisBitRange( Container, 0, 4, "Processor Mode" ); |
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162 rangeProcMode.Interpretation = ArmRegisterBankUtils.BankAsStringLong( ProcessorMode ); |
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163 rangeProcMode.ExtractBits( value, "########", "########", "########", "###11111" ); |
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164 aVisualization.AddChild( rangeProcMode ); |
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165 |
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166 // Thumb bit |
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167 CIRegisterVisBit thumbBit = CreateYesNoBit( aVisualization, 5, "########", "########", "########", "##1#####", false, "Thumb Mode", "T" ); |
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168 aVisualization.AddChild( thumbBit ); |
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169 |
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170 // FIQ, IRQ bits |
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171 CIRegisterVisBitGroup gpIRQs = new CIRegisterVisBitGroup( Container, "Interrupt Disabled Bits" ); |
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172 CIRegisterVisBit fiqBit = CreateYesNoBit( aVisualization, 6, "########", "########", "########", "#1######", false, "FIQ Disabled", "F" ); |
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173 gpIRQs.Add( fiqBit ); |
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174 CIRegisterVisBit irqBit = CreateYesNoBit( aVisualization, 7, "########", "########", "########", "1#######", false, "IRQ Disabled", "I" ); |
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175 gpIRQs.Add( irqBit ); |
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176 |
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177 // Imprecise Abort bit - reserved in non-ARMv5 |
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178 CIRegisterVisBit iaBit = CreateYesNoBit( aVisualization, 8, "########", "########", "#######1", "########", aIsIABitReserved, "Imprecise Aborts", "A" ); |
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179 gpIRQs.Add( iaBit ); |
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180 |
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181 aVisualization.AddChild( gpIRQs ); |
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182 } |
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183 |
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184 private void AddEndianness( CIRegisterVisualization aVisualization, bool aIsReserved ) |
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185 { |
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186 uint value = aVisualization.Register.Value; |
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187 |
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188 CIRegisterVisBit eBit = CreateBitValue( aVisualization, 9, "###1####", "########", "######1#", "########", aIsReserved, "Endianness", "Big", "Little", "B", "L" ); |
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189 aVisualization.AddChild( eBit ); |
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190 } |
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191 |
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192 private void AddJazelle( CIRegisterVisualization aVisualization, bool aIsReserved ) |
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193 { |
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194 CIRegisterVisBit bit = CreateYesNoBit( aVisualization, 24, "#######1", "########", "########", "########", aIsReserved, "Jazelle", "J" ); |
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195 aVisualization.AddChild( bit ); |
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196 } |
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197 |
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198 private void AddQFlag( CIRegisterVisualization aVisualization, bool aIsReserved ) |
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199 { |
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200 CIRegisterVisBit bit = CreateYesNoBit( aVisualization, 27, "####1###", "########", "########", "########", aIsReserved, "Q-Flag (DSP Saturation/Overflow)", "Q" ); |
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201 aVisualization.AddChild( bit ); |
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202 } |
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203 |
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204 private void AddConditionCodeFlags( CIRegisterVisualization aVisualization ) |
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205 { |
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206 uint value = aVisualization.Register.Value; |
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207 |
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208 CIRegisterVisBitGroup group = new CIRegisterVisBitGroup( Container ); |
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209 |
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210 CIRegisterVisBit oBit = CreateYesNoBit( aVisualization, 28, "###1####", "########", "########", "########", false, "Overflow (Condition Code)", "O" ); |
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211 group.Add( oBit ); |
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212 CIRegisterVisBit cBit = CreateYesNoBit( aVisualization, 29, "##1#####", "########", "########", "########", false, "Carry (Condition Code)", "C" ); |
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213 group.Add( cBit ); |
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214 CIRegisterVisBit zBit = CreateYesNoBit( aVisualization, 30, "#1######", "########", "########", "########", false, "Zero (Condition Code)", "Z" ); |
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215 group.Add( zBit ); |
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216 CIRegisterVisBit nBit = CreateYesNoBit( aVisualization, 31, "1#######", "########", "########", "########", false, "Negative (Condition Code)", "N" ); |
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217 group.Add( nBit ); |
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218 |
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219 aVisualization.AddChild( group ); |
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220 } |
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221 |
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222 private CIRegisterVisBitRange AddBitRange( CIRegisterVisualization aVisualization, uint aStart, uint aEnd, string aCategory ) |
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223 { |
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224 // Make the mask |
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225 AddressRange range = new AddressRange( aStart, aEnd ); |
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226 StringBuilder mask = new StringBuilder(); |
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227 mask.Append( string.Empty.PadLeft( 32, '#' ) ); |
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228 for ( int i=31; i>=0; i-- ) |
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229 { |
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230 if ( range.Contains( i ) ) |
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231 { |
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232 int index = 31 - i; |
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233 mask[ index ] = '1'; |
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234 } |
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235 } |
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236 |
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237 // Reserved |
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238 uint value = aVisualization.Register.Value; |
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239 |
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240 CIRegisterVisBitRange bitRange = new CIRegisterVisBitRange( Container, aStart, aEnd, aCategory ); |
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241 bitRange.ExtractBits( value, mask.ToString() ); |
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242 aVisualization.AddChild( bitRange ); |
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243 |
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244 return bitRange; |
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245 } |
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246 |
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247 private void AddReserved( CIRegisterVisualization aVisualization, uint aStart, uint aEnd ) |
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248 { |
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249 CIRegisterVisBitRange range = AddBitRange( aVisualization, aStart, aEnd, KReserved ); |
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250 range.IsReserved = true; |
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251 } |
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252 |
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253 private CIRegisterVisBit CreateBitValue( CIRegisterVisualization aVisualization, int aIndex, |
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254 string aMaskByte3, string aMaskByte2, string aMaskByte1, string aMaskByte0, |
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255 bool aReserved, string aCategory, string aInterpretationSet, string aInterpretationClear, string aBitSetCharacter ) |
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256 { |
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257 CIRegisterVisBit bit = CreateBitValue( aVisualization, aIndex, aMaskByte3, aMaskByte2, aMaskByte1, aMaskByte0, aReserved, aCategory,aInterpretationSet, aInterpretationClear, aBitSetCharacter, string.Empty ); |
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258 return bit; |
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259 } |
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260 |
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261 private CIRegisterVisBit CreateBitValue( CIRegisterVisualization aVisualization, int aIndex, |
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262 string aMaskByte3, string aMaskByte2, string aMaskByte1, string aMaskByte0, |
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263 bool aReserved, string aCategory, string aInterpretationSet, string aInterpretationClear, string aBitSetCharacter, string aBitClearCharacter ) |
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264 { |
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265 uint value = aVisualization.Register.Value; |
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266 // |
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267 CIRegisterVisBit bit = new CIRegisterVisBit( Container, aIndex, VisUtilities.ExtractBit( value, aMaskByte3, aMaskByte2, aMaskByte1, aMaskByte0 ), aCategory, string.Empty ); |
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268 bit.IsReserved = aReserved; |
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269 bit[ TBit.EBitClear ] = aBitClearCharacter; |
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270 bit[ TBit.EBitSet ] = aBitSetCharacter; |
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271 // |
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272 switch ( bit.Value ) |
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273 { |
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274 case TBit.EBitSet: |
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275 bit.Interpretation = aInterpretationSet; |
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276 break; |
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277 default: |
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278 case TBit.EBitClear: |
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279 bit.Interpretation = aInterpretationClear; |
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280 break; |
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281 } |
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282 // |
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283 return bit; |
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284 } |
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285 |
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286 private CIRegisterVisBit CreateYesNoBit( CIRegisterVisualization aVisualization, int aIndex, string aMaskByte3, string aMaskByte2, string aMaskByte1, string aMaskByte0, bool aReserved, string aCategory, string aBitSetCharacter ) |
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287 { |
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288 CIRegisterVisBit bit = CreateBitValue( aVisualization, aIndex, aMaskByte3, aMaskByte2, aMaskByte1, aMaskByte0, aReserved, aCategory, "Yes", "No", aBitSetCharacter ); |
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289 return bit; |
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290 } |
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291 #endregion |
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292 |
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293 #region Data members |
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294 #endregion |
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295 } |
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296 } |