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<concept id="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C" xml:lang="en"><title>Bootstrap Source Macros</title><shortdesc>Describes the macros used in source files.</shortdesc><prolog><metadata><keywords/></metadata></prolog><conbody>

<p>This set of macros is available for use in source files, but not in platform

specific configuration header files. Their definitions are obtained by including <filepath>os/kernelhwsrv/kernel/eka/include/kernel/arm/bootcpu.inc</filepath>. </p>

<section id="GUID-B4783B78-8320-5315-B88D-40BCC8FDF64B"><title>General macros</title> <p><b>GETCPSR</b> </p><codeblock id="GUID-DE99B191-1C2F-5843-B6FC-776996CDB238" xml:space="preserve">GETCPSR    reg</codeblock><p>Reads

the CPSR into the specified ARM general register <codeph>reg</codeph>. </p><p>This

macro should be used in preference to MRS instructions to avoid problems related

to syntax incompatibility between different assembler versions. </p> <p><b>CGETCPSR</b> </p><codeblock id="GUID-7F37007A-9407-5BBA-B42A-DB447B32F4A6" xml:space="preserve">CGETCPSR reg, cc</codeblock><p>Reads

the CPSR into the specified ARM general register <codeph>reg</codeph>. This

is conditionally executed using <codeph>cc</codeph> as the execution condition. </p><p>This

macro should be used in preference to MRS instructions to avoid problems related

to syntax incompatibility between different assembler versions. </p> <p><b>GETSPSR</b> </p><codeblock id="GUID-8636F4DC-EE5F-5121-A397-4AD5B66EB4A4" xml:space="preserve">GETSPSR    reg</codeblock><p>Reads

the SPSR into the specified ARM general register <codeph>reg</codeph>. </p><p>This

macro should be used in preference to MRS instructions to avoid problems related

to syntax incompatibility between different assembler versions. </p> <p><b>CGETSPSR</b> </p><codeblock id="GUID-EA9861EC-AA09-5E52-9A84-D35DA301EE1E" xml:space="preserve">CGETSPSR reg, cc</codeblock><p>Reads

the SPSR into the specified ARM general register <codeph>reg</codeph>. This

is conditionally executed using <codeph>cc</codeph> as the execution condition. </p><p>This

macro should be used in preference to MRS instructions to avoid problems related

to syntax incompatibility between different assembler versions. </p> <p><b>SETCPSR</b> </p> <codeblock id="GUID-5AC38C91-DF6D-5842-B669-7D54D9E1C580" xml:space="preserve">SETCPSR    reg</codeblock> <p>Writes

the entire (all 32 bits) CPSR from the specified ARM general register <codeph>reg</codeph>.</p><p>This

macro should be used in preference to MRS instructions to avoid problems related

to syntax incompatibility between different assembler versions. </p> <p><b>CSETCPSR</b> </p><codeblock id="GUID-B2ED96F7-0985-5673-8D22-5E036F73B308" xml:space="preserve">CSETCPSR reg, cc</codeblock><p>Writes

the entire (all 32 bits) CPSR from the specified ARM general register <codeph>reg</codeph>.

This is conditionally executed using <codeph>cc</codeph> as the execution

condition. </p><p>This macro should be used in preference to MRS instructions

to avoid problems related to syntax incompatibility between different assembler

versions. </p> <p><b>SETSPSR</b> </p><codeblock id="GUID-A5DA9C4A-1D08-5CCE-B507-25E778B80A2D" xml:space="preserve">SETSPSR    reg</codeblock><p>Writes

the entire (all 32 bits) SPSR from the specified ARM general register <codeph>reg</codeph>. </p><p>This

macro should be used in preference to MRS instructions to avoid problems related

to syntax incompatibility between different assembler versions. </p> <p><b>CSETSPSR</b> </p><codeblock id="GUID-94F1C1A0-92E1-5F7D-B49A-A283303D10BC" xml:space="preserve">CSETSPSR reg, cc</codeblock><p>Writes

the entire (all 32 bits) SPSR from the specified ARM general register <codeph>reg</codeph>.

This is conditionally executed using <codeph>cc</codeph> as the execution

condition. </p><p>This macro should be used in preference to MRS instructions

to avoid problems related to syntax incompatibility between different assembler

versions. </p> <p><b>BOOTCALL</b> </p><codeblock id="GUID-EDAA1A5D-8067-5754-8FED-2B0C5E68F687" xml:space="preserve">BOOTCALL call_numbe</codeblock><p>Calls

the specified function via the boot table. <codeph>call_number</codeph> should

be one of the <codeph>BTF_*</codeph> values in the <codeph>TBootTableEntry</codeph> enumeration,

defined in <filepath>os/kernelhwsrv/kernel/eka/include/kernel/arm/bootdefs.h</filepath>. </p><p>The

macro is transparent; the function is entered with all registers and flags

having the same values as immediately before the macro. </p> <p><b>GETPARAM</b> </p><codeblock id="GUID-3A25AFEF-8195-555B-B328-4BA1A8988D1F" xml:space="preserve">GETPARAM pnum, default</codeblock><p>Retrieves

the parameter with number <codeph>pnum</codeph> from the boot parameter table,

and returns its value in <codeph>R0</codeph>. If the parameter is not present

in the table, then <codeph>R0</codeph> is loaded with value <codeph>default</codeph>. </p><p>See

the description of <xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita#GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE/GUID-4DEA1D4C-EC7B-5F9A-A293-A7F80899044B">BTF_Params</xref> for

more information on the boot parameter table. </p> <p><b>GETMPARAM</b> </p><codeblock id="GUID-5DA2A8EA-6D2E-5ECD-80B9-FDD1CDEE1797" xml:space="preserve">GETMPARAM pnum</codeblock><p>Retrieves

the parameter with number <codeph>pnum</codeph> from the boot parameter table,

and returns its value in <codeph>R0</codeph>. If the parameter is not present

in the table, then the macro faults the system. </p><p>See the description

of <xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita#GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE/GUID-4DEA1D4C-EC7B-5F9A-A293-A7F80899044B">BTF_Params</xref> for

more information on the boot parameter table. </p> <p><b>FAULT</b> </p><codeblock id="GUID-8C551296-DAF8-57D3-9048-3B06387820AB" xml:space="preserve">FAULT cc</codeblock><p>Faults

the system if condition <codeph>cc</codeph> is true. The condition is a standard

ARM condition code. </p> <p id="GUID-B5EC22B5-B995-5D54-8F33-1B6FCE11BB3F"><b>BTP_ENTRY</b></p> <p>Declares

MMU permissions and cache attributes. The macro takes a variable number of

arguments depending on the processor in use. </p><p>For ARM architecture 6

CPUs: </p><codeblock id="GUID-7CD2FE06-23C4-569A-AFBB-D62BE8CE2CC9" xml:space="preserve">BTP_ENTRY $domain, $perm, $cache, $execute, $global, $P, $S</codeblock> <p>For

XScale CPUs: </p><codeblock id="GUID-1E6704C5-AABA-51E3-8C6B-233E6A188829" xml:space="preserve">BTP_ENTRY $domain, $perm, $cache, $P</codeblock> <p>For

other CPUs: </p><codeblock id="GUID-1D95F820-E5FC-5A95-B4D7-051F9A5DD70C" xml:space="preserve">BTP_ENTRY $domain, $perm, $cache</codeblock> <table id="GUID-99F49C22-9194-565E-8C8A-F4D864311A8B">

<tgroup cols="2"><colspec colname="col0"/><colspec colname="col1"/>

<tbody>

<row>

<entry><p>$domain </p> </entry>

<entry><p>ARM domain number 0-15. In general only one memory-model-dependent

value is used here and the symbol <codeph>CLIENT_DOMAIN</codeph> specifies

this. </p></entry>

</row>

<row>

<entry><p>$perm </p> </entry>

<entry><p>Permissions for mapping. </p><p>For architecture 6 CPUs, use one

of <codeph>PERM_NONO</codeph>, <codeph>PERM_RWNO</codeph>, <codeph>PERM_RWRO</codeph>, <codeph>PERM_RWRW</codeph>, <codeph>PERM_RONO</codeph>, <codeph>PERM_RORO</codeph>. </p><p>For other CPUs, use one of <codeph>PERM_RORO</codeph>, <codeph>PERM_RWNO</codeph>, <codeph>PERM_RWRO</codeph>, <codeph>PERM_RWRW</codeph>. </p><p>In each of these names the first pair of letters

refers to supervisor, and the second pair to user access, so <codeph>PERM_RWNO</codeph> means

supervisor read/write, user no access. </p></entry>

</row>

<row>

<entry><p>$cache </p> </entry>

<entry><p>Cache attributes for mapping. These are processor dependent - see

the <codeph>CACHE_*</codeph> macros in <filepath>os/kernelhwsrv/kernel/eka/include/kernel/arm/bootcpu.inc</filepath>. </p></entry>

</row>

<row>

<entry><p>$execute </p> </entry>

<entry><p>ARM architecture 6 only. Determines whether code can be executed

from the mapped region; either <codeph>BTPERM_EXECUTE</codeph> or <codeph>BTPERM_NO_EXECUTE</codeph>. </p> </entry>

</row>

<row>

<entry><p>$global </p> </entry>

<entry><p>ARM architecture 6 only. Determines whether the mapped region is

ASID specific (local) or non-ASID specific (global); either <codeph>BTPERM_LOCAL</codeph> or <codeph>BTPERM_GLOBAL</codeph>. </p> </entry>

</row>

<row>

<entry><p>$P </p> </entry>

<entry><p>ARM architecture 6 and XScale only. Determines whether or not ECC

should be used on the mapped region (assuming hardware supports ECC); either <codeph>BTPERM_ECC</codeph> or <codeph>BTPERM_NON_ECC</codeph>. </p> </entry>

</row>

<row>

<entry><p>$S </p> </entry>

<entry><p>ARM architecture 6 only. Determines whether the mapped region is

shared between multiple CPUs or not; either <codeph>BTPERM_SHARED</codeph> or <codeph>BTPERM_NON_SHARED</codeph>. </p> </entry>

</row>

</tbody>

</tgroup>

</table> <p id="GUID-7361BC74-7164-52EE-9A5B-D254560D1939"><b>ROM_BANK</b> </p><codeblock id="GUID-7685BA97-8DC4-537C-AEBC-110AB0981DD0" xml:space="preserve">ROM_BANK PHYS, SIZE, LIN, WIDTH, TYPE, RAND, SEQ</codeblock><p>Declares

an XIP ROM bank entry. </p> <table id="GUID-F701B695-A499-57E0-97B6-7C5701E09F77">

<tgroup cols="2"><colspec colname="col0"/><colspec colname="col1"/>

<tbody>

<row>

<entry><p>PHYS </p> </entry>

<entry><p>The physical base address of the ROM bank. </p> </entry>

</row>

<row>

<entry><p>SIZE </p> </entry>

<entry><p>The size of the ROM bank. </p> </entry>

</row>

<row>

<entry><p>LIN </p> </entry>

<entry><p>Linear address override (usually 0). </p> </entry>

</row>

<row>

<entry><p>WIDTH </p> </entry>

<entry><p>Bus width. One of: <codeph>ROM_WIDTH_8</codeph>, <codeph>ROM_WIDTH_16</codeph> or <codeph>ROM_WIDTH_32</codeph>  </p> </entry>

</row>

<row>

<entry><p>TYPE </p> </entry>

<entry><p>The ROM type; see the <xref href="GUID-C1232A34-6E4C-3AAF-8E97-8BA2303B9508.dita"><apiname>TRomType</apiname></xref> enumeration. </p> </entry>

</row>

<row>

<entry><p>RAND </p> </entry>

<entry><p>Random access speed. </p> </entry>

</row>

<row>

<entry><p>SEQ </p> </entry>

<entry><p>Sequential access speed. </p> </entry>

</row>

</tbody>

</tgroup>

</table> <p>See also <xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita#GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE/GUID-52792290-48DA-5F1A-A7AD-0105A8AA37CF">BTF_RomBanks</xref> in <xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita">Boot Table Functions</xref>. </p> </section>

<section id="GUID-7728C7F2-BB04-518B-8B0A-752CB799A561"><title>Macros for

declaring I/O mappings</title> <p id="GUID-13254CB0-3659-5338-A3C2-1277F6869CA7"><b>HW_MAPPING</b> </p><codeblock id="GUID-5A4745F8-8B21-593B-85AF-4C56D7DA7075" xml:space="preserve">HW_MAPPING PHYS,SIZE,MULT</codeblock><p>Defines

an I/O mapping using the standard permissions and cache attributes for I/O

mappings, i.e. those defined for the <codeph>BTP_Hw</codeph> boot table entry.

See <xref href="GUID-C92CC81A-35A1-5860-AA08-C8C08B39804C.dita">Boot Table MMU

Permission and Cache Attribute Definitions</xref>. </p> <table id="GUID-9B975DEB-0D16-5DEE-8E11-7109E052D409">

<tgroup cols="2"><colspec colname="col0"/><colspec colname="col1"/>

<tbody>

<row>

<entry><p>PHYS </p> </entry>

<entry><p>Physical base address. </p> </entry>

</row>

<row>

<entry><p>SIZE </p> </entry>

<entry><p>Size of the mapping. </p> </entry>

</row>

<row>

<entry><p>MULT </p> </entry>

<entry><p> <xref href="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C.dita#GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C/GUID-B13C34B2-69E5-51A2-8807-5576FD091C34">Granularity

of the I/O mapping</xref> (below). </p> </entry>

</row>

</tbody>

</tgroup>

</table> <p>See also: </p><ul>

<li id="GUID-75387946-50A1-5D24-A5C4-4AED7954ACAF"><p><xref href="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C.dita#GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C/GUID-20A2344A-1BE2-5AFD-BC37-997F08E2A28C">Determining the linear address</xref> (below). </p> </li>

<li id="GUID-2DD01E2F-841B-5242-9757-A48F6036AE6A"><p><xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita#GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE/GUID-62CD8D6F-6E12-5DFC-85BC-EA24000BA588">BTF_HwBanks</xref> in <xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita">Boot

Table Functions</xref>. </p></li>

</ul> <p id="GUID-EF703014-E498-5623-ACC6-8E3E9882C681"><b>HW_MAPPING_EXT</b> </p><codeblock id="GUID-EEAFCF55-9C2F-5EE6-9A37-287772F4BCF4" xml:space="preserve">HW_MAPPING_EXT    PHYS,SIZE,MULT</codeblock><p>Defines

an I/O mapping using the permissions and cache attributes defined by a <codeph>BTP_ENTRY</codeph> macro

that immediately follows this macro. See <xref href="GUID-C92CC81A-35A1-5860-AA08-C8C08B39804C.dita">Boot

Table MMU Permission and Cache Attribute Definitions</xref>. </p><table id="GUID-8186D7BA-30AC-5A3A-BF25-6AB6984B0A45">

<tgroup cols="2"><colspec colname="col0"/><colspec colname="col1"/>

<tbody>

<row>

<entry><p>PHYS </p> </entry>

<entry><p>Physical base address. </p> </entry>

</row>

<row>

<entry><p>SIZE </p> </entry>

<entry><p>Size of the mapping. </p> </entry>

</row>

<row>

<entry><p>MULT </p> </entry>

<entry><p> <xref href="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C.dita#GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C/GUID-B13C34B2-69E5-51A2-8807-5576FD091C34">Granularity

of the I/O mapping</xref> (below). </p> </entry>

</row>

</tbody>

</tgroup>

</table> <p>See also: </p> <ul>

<li id="GUID-460D2F0F-F42B-58CD-910B-5DEEE210F061"><p> <xref href="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C.dita#GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C/GUID-20A2344A-1BE2-5AFD-BC37-997F08E2A28C">Determining the linear address</xref> (below). </p> </li>

<li id="GUID-D13EB05F-E447-51EA-BF15-0AA3870BE101"><p><xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita#GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE/GUID-62CD8D6F-6E12-5DFC-85BC-EA24000BA588">BTF_HwBanks</xref> in <xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita">Boot

Table Functions</xref>. </p> </li>

</ul> <p id="GUID-7402DE22-6CB9-5236-BA3B-99D6CE40A381"><b>HW_MAPPING_EXT2</b> </p><codeblock id="GUID-6F0B0F0D-CBE6-5320-9F51-39388B4181E6" xml:space="preserve">HW_MAPPING_EXT2    PHYS,SIZE,MULT,LIN</codeblock><p>Defines

an I/O mapping using the standard permissions and cache attributes for I/O

mappings, i.e. those defined for the <codeph>BTP_Hw</codeph> boot table entry.

See <xref href="GUID-C92CC81A-35A1-5860-AA08-C8C08B39804C.dita">Boot Table MMU

Permission and Cache Attribute Definitions</xref>. </p> <table id="GUID-55243AD3-DF9F-5D9D-9549-35F577C20E83">

<tgroup cols="2"><colspec colname="col0"/><colspec colname="col1"/>

<tbody>

<row>

<entry><p>PHYS </p> </entry>

<entry><p>Physical base address. </p> </entry>

</row>

<row>

<entry><p>SIZE </p> </entry>

<entry><p>Size of the mapping. </p> </entry>

</row>

<row>

<entry><p>MULT </p> </entry>

<entry><p> <xref href="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C.dita#GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C/GUID-B13C34B2-69E5-51A2-8807-5576FD091C34">Granularity

of the I/O mapping</xref> (below). </p> </entry>

</row>

<row>

<entry><p>LIN </p> </entry>

<entry><p>Linear address. </p> </entry>

</row>

</tbody>

</tgroup>

</table> <p>See also <xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita#GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE/GUID-62CD8D6F-6E12-5DFC-85BC-EA24000BA588">BTF_HwBanks</xref> in <xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita">Boot Table Functions</xref>. </p> <p id="GUID-9F79FF06-C8E8-599A-875A-D772FB6E8862"><b>HW_MAPPING_EXT3</b> </p><codeblock id="GUID-C1948F05-F4C7-5DCC-A266-0489F5A0BC00" xml:space="preserve">HW_MAPPING_EXT3 PHYS,SIZE,MULT,LIN</codeblock><p>Defines

an I/O mapping using the permissions and cache attributes defined by a <codeph>BTP_ENTRY</codeph> macro

that immediately follows this macro. See <xref href="GUID-C92CC81A-35A1-5860-AA08-C8C08B39804C.dita">Boot

Table MMU Permission and Cache Attribute Definitions</xref>. </p> <table id="GUID-D7252A3A-F7ED-5A78-94B2-B736AC61046E">

<tgroup cols="2"><colspec colname="col0"/><colspec colname="col1"/>

<tbody>

<row>

<entry><p>PHYS </p> </entry>

<entry><p>Physical base address. </p> </entry>

</row>

<row>

<entry><p>SIZE </p> </entry>

<entry><p>Size of the mapping. </p> </entry>

</row>

<row>

<entry><p>MULT </p> </entry>

<entry><p> <xref href="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C.dita#GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C/GUID-B13C34B2-69E5-51A2-8807-5576FD091C34">Granularity

of the I/O mapping</xref> (below). </p> </entry>

</row>

<row>

<entry><p>LIN </p> </entry>

<entry><p>Linear address. </p> </entry>

</row>

</tbody>

</tgroup>

</table> <p>See also <xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita#GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE/GUID-62CD8D6F-6E12-5DFC-85BC-EA24000BA588">BTF_HwBanks</xref> in <xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita">Boot Table Functions</xref>.. </p> <p id="GUID-B13C34B2-69E5-51A2-8807-5576FD091C34"><b>Granularity of the I/O mapping</b> </p> <p>The

granularity of the I/O mapping is defined by the <codeph>MULT</codeph> parameter

of the I/O mapping macros: <xref href="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C.dita#GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C/GUID-13254CB0-3659-5338-A3C2-1277F6869CA7">HW_MAPPING</xref>, <xref href="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C.dita#GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C/GUID-EF703014-E498-5623-ACC6-8E3E9882C681">HW_MAPPING_EXT</xref>, <xref href="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C.dita#GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C/GUID-7402DE22-6CB9-5236-BA3B-99D6CE40A381">HW_MAPPING_EXT2</xref> and <xref href="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C.dita#GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C/GUID-9F79FF06-C8E8-599A-875A-D772FB6E8862">HW_MAPPING_EXT3</xref>. </p> <p>The <codeph>MULT</codeph> parameter specifies the granularity of the mapping. It takes one of the

following values: </p> <ul>

<li id="GUID-AA1B0CD5-6336-5C02-AF02-562AB4A44FA3"><p> <codeph>HW_MULT_4K</codeph> use

4K pages. The <codeph>PHYS</codeph> and <codeph>LIN</codeph> parameters must

be multiples of 4K. </p> </li>

<li id="GUID-15DC0CE0-B90C-500C-90FD-F750F61F509B"><p> <codeph>HW_MULT_64K</codeph> use

64K pages. The <codeph>PHYS</codeph> and <codeph>LIN</codeph> parameters must

be multiples of 64K. </p> </li>

<li id="GUID-DE644971-8E56-5921-85BD-BC79AAD66C49"><p> <codeph>HW_MULT_1M</codeph> use

1M sections. The <codeph>PHYS</codeph> and <codeph>LIN</codeph> parameters

must be multiples of 1M. </p> </li>

</ul> <p>In each case the unit in which the <codeph>SIZE</codeph> parameter

is specified is <codeph>MULT</codeph>, that is to say the actual mapping size

in bytes is <codeph>SIZE*MULT</codeph>. For example: </p><codeblock id="GUID-5B389113-F6DB-5011-8B59-93F599519E94" xml:space="preserve">HW_MAPPING    0x80000000, 1, HW_MULT_4K

HW_MAPPING    0x80010000, 3, HW_MULT_64K</codeblock><p>declares a mapping

of size 4K starting at physical address <codeph>0x80000000</codeph> followed

by a mapping of 192K in 64K pages starting at physical address <codeph>0x80010000</codeph>. </p> <p id="GUID-20A2344A-1BE2-5AFD-BC37-997F08E2A28C"><b>Determining the linear address</b> </p> <p>For

those macros that don't specify a linear address: <xref href="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C.dita#GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C/GUID-13254CB0-3659-5338-A3C2-1277F6869CA7">HW_MAPPING</xref> and <xref href="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C.dita#GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C/GUID-EF703014-E498-5623-ACC6-8E3E9882C681">HW_MAPPING_EXT</xref>,

it is determined as follows: </p> <ul>

<li id="GUID-37DB1D7B-0D4B-5E3C-9E7F-F195D7A1B95C"><p>On the direct memory

model, it is equal to the physical address. </p> </li>

<li id="GUID-77168F6C-3B11-5B32-AEF1-B77046A0EC78"><p>On the moving memory

model and the multiple memory model, the first such mapping is placed at <codeph>KPrimaryIOBase</codeph> (<codeph>0x63000000</codeph> on

the moving model, <codeph>0xC3000000</codeph> on the multiple model). Each

mapping first rounds the linear address counter up to the next multiple of <codeph>MULT</codeph> before

making the mapping, then increments it by <codeph>SIZE*MULT</codeph> after

making it. </p> </li>

</ul> <p>For example, on the moving memory model, the following mappings would

have linear addresses <codeph>0x63000000</codeph>, <codeph>0x63002000</codeph>, <codeph>0x63010000</codeph>, <codeph>0x63020000</codeph> and <codeph>0x63100000</codeph> respectively: </p><codeblock id="GUID-529F87FB-7DD6-521F-8397-667C710843E2" xml:space="preserve">HW_MAPPING    0x80000000, 2, HW_MULT_4K

HW_MAPPING    0x80010000, 1, HW_MULT_4K

HW_MAPPING    0x80100000, 1, HW_MULT_64K

HW_MAPPING    0x80200000, 1, HW_MULT_4K

HW_MAPPING    0x90000000, 1, HW_MULT_1M</codeblock> <p>For the direct memory

model, all I/O mappings required by the system must be listed here since it

is not possible to make further mappings once the kernel is running. </p> </section>

</conbody></concept>