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Symbian3/PDK/Source/GUID-96F07979-3863-5198-AF8B-4ACC1193CF3E.dita
author Graeme Price <GRAEME.PRICE@NOKIA.COM>
Fri, 15 Oct 2010 14:32:18 +0100
changeset 15 307f4279f433
parent 14 578be2adaf3e
permissions -rw-r--r--
Initial contribution of the Adaptation Documentation.
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<?xml version="1.0" encoding="utf-8"?>
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<!-- Copyright (c) 2007-2010 Nokia Corporation and/or its subsidiary(-ies) All rights reserved. -->
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<!-- This component and the accompanying materials are made available under the terms of the License
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"Eclipse Public License v1.0" which accompanies this distribution,
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and is available at the URL "http://www.eclipse.org/legal/epl-v10.html". -->
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<!-- Initial Contributors:
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    Nokia Corporation - initial contribution.
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Contributors:
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-->
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<!DOCTYPE concept
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  PUBLIC "-//OASIS//DTD DITA Concept//EN" "concept.dtd">
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<concept id="GUID-96F07979-3863-5198-AF8B-4ACC1193CF3E" xml:lang="en"><title>Level
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2 Cache Tutorial</title><shortdesc>This topic describes how to configure the base port to use the
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ARM L210 cache or L220 cache controllers in ARM processors. </shortdesc><prolog><metadata><keywords/></metadata></prolog><conbody>
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<p>Cache is a fast buffer that keeps copies of recently accessed memory. </p>
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<section id="GUID-6ECBAFBD-87A5-4CB2-8A83-24F5208A58DA"><title>L210 Cache</title> <p>In
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the <filepath>variant.mmh</filepath> file, set the macro: </p> <codeblock id="GUID-FB4E4E84-828F-5FD6-A296-F55FA8F7C25D" xml:space="preserve">__ARM_L210_CACHE__</codeblock> <p>You
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must also set a L210 Cache macro and initialise Level 2 cache in the Bootstrap.
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See <xref href="GUID-4A910E9F-E881-51D7-A84A-CBC6AC343FD1.dita">Level 2 Cache Macros</xref> and <xref href="GUID-F67FA7B5-F6D1-5C5C-8E10-A8E317A778E4.dita#GUID-F67FA7B5-F6D1-5C5C-8E10-A8E317A778E4/GUID-C111DA06-F7EE-5E70-8D86-26BA2213B506">HardwareInitialise()</xref>. </p> <p>The
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L210 cache is switched on by generic Symbian platform code before jumping
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into the kernel code. The cache is switched on after the MMU and L1 cache
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are enabled. </p> </section>
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<section id="GUID-D713DF71-C896-45EA-86D6-55E5FF9CFABC"><title>L220 Cache</title> <p>In
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the <filepath>variant.mmh</filepath> file, set the macro: </p> <codeblock id="GUID-8DCEE6B7-E852-5B3D-AFE7-E512DCAA73C0" xml:space="preserve">__ARM_L220_CACHE__</codeblock> <p>You
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parents: 5
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must also set a L220 Cache macro and initialise Level 2 cache in the Bootstrap.
578be2adaf3e Week 32 contribution of PDK documentation content. See release notes for details. Fixes bug Bug 3582
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See <xref href="GUID-4A910E9F-E881-51D7-A84A-CBC6AC343FD1.dita">Level 2 Cache Macros</xref> and <xref href="GUID-F67FA7B5-F6D1-5C5C-8E10-A8E317A778E4.dita#GUID-F67FA7B5-F6D1-5C5C-8E10-A8E317A778E4/GUID-C111DA06-F7EE-5E70-8D86-26BA2213B506">HardwareInitialise()</xref>. </p> <p>Code
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to switch on the L220 cache on must be provided by the base port. You can
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do this in the <xref href="GUID-F67FA7B5-F6D1-5C5C-8E10-A8E317A778E4.dita#GUID-F67FA7B5-F6D1-5C5C-8E10-A8E317A778E4/GUID-C111DA06-F7EE-5E70-8D86-26BA2213B506">HardwareInitialise()</xref> function
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or the <xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita#GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE/GUID-EEF889E7-915F-57E9-8E2D-DC17B24C7728">BTF_Final()</xref> function
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in the Bootstrap. </p> </section>
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25a17d01db0c Addition of the PDK content and example code for Documentation_content according to Feature bug 1607 and bug 1608
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</conbody></concept>
FCL/sftools/depl/docscontent