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1 <?xml version="1.0" encoding="utf-8"?> |
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2 <!-- Copyright (c) 2007-2010 Nokia Corporation and/or its subsidiary(-ies) All rights reserved. --> |
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3 <!-- This component and the accompanying materials are made available under the terms of the License |
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4 "Eclipse Public License v1.0" which accompanies this distribution, |
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5 and is available at the URL "http://www.eclipse.org/legal/epl-v10.html". --> |
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6 <!-- Initial Contributors: |
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7 Nokia Corporation - initial contribution. |
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8 Contributors: |
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9 --> |
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10 <!DOCTYPE concept |
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11 PUBLIC "-//OASIS//DTD DITA Concept//EN" "concept.dtd"> |
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12 <concept id="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C" xml:lang="en"><title>Bootstrap Source Macros</title><shortdesc>Describes the macros used in source files.</shortdesc><prolog><metadata><keywords/></metadata></prolog><conbody> |
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13 <p>This set of macros is available for use in source files, but not in platform |
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14 specific configuration header files. Their definitions are obtained by including <filepath>os/kernelhwsrv/kernel/eka/include/kernel/arm/bootcpu.inc</filepath>. </p> |
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15 <section id="GUID-B4783B78-8320-5315-B88D-40BCC8FDF64B"><title>General macros</title> <p><b>GETCPSR</b> </p><codeblock id="GUID-DE99B191-1C2F-5843-B6FC-776996CDB238" xml:space="preserve">GETCPSR reg</codeblock><p>Reads |
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16 the CPSR into the specified ARM general register <codeph>reg</codeph>. </p><p>This |
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17 macro should be used in preference to MRS instructions to avoid problems related |
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18 to syntax incompatibility between different assembler versions. </p> <p><b>CGETCPSR</b> </p><codeblock id="GUID-7F37007A-9407-5BBA-B42A-DB447B32F4A6" xml:space="preserve">CGETCPSR reg, cc</codeblock><p>Reads |
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19 the CPSR into the specified ARM general register <codeph>reg</codeph>. This |
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20 is conditionally executed using <codeph>cc</codeph> as the execution condition. </p><p>This |
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21 macro should be used in preference to MRS instructions to avoid problems related |
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22 to syntax incompatibility between different assembler versions. </p> <p><b>GETSPSR</b> </p><codeblock id="GUID-8636F4DC-EE5F-5121-A397-4AD5B66EB4A4" xml:space="preserve">GETSPSR reg</codeblock><p>Reads |
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23 the SPSR into the specified ARM general register <codeph>reg</codeph>. </p><p>This |
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24 macro should be used in preference to MRS instructions to avoid problems related |
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25 to syntax incompatibility between different assembler versions. </p> <p><b>CGETSPSR</b> </p><codeblock id="GUID-EA9861EC-AA09-5E52-9A84-D35DA301EE1E" xml:space="preserve">CGETSPSR reg, cc</codeblock><p>Reads |
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26 the SPSR into the specified ARM general register <codeph>reg</codeph>. This |
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27 is conditionally executed using <codeph>cc</codeph> as the execution condition. </p><p>This |
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28 macro should be used in preference to MRS instructions to avoid problems related |
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29 to syntax incompatibility between different assembler versions. </p> <p><b>SETCPSR</b> </p> <codeblock id="GUID-5AC38C91-DF6D-5842-B669-7D54D9E1C580" xml:space="preserve">SETCPSR reg</codeblock> <p>Writes |
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30 the entire (all 32 bits) CPSR from the specified ARM general register <codeph>reg</codeph>.</p><p>This |
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31 macro should be used in preference to MRS instructions to avoid problems related |
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32 to syntax incompatibility between different assembler versions. </p> <p><b>CSETCPSR</b> </p><codeblock id="GUID-B2ED96F7-0985-5673-8D22-5E036F73B308" xml:space="preserve">CSETCPSR reg, cc</codeblock><p>Writes |
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33 the entire (all 32 bits) CPSR from the specified ARM general register <codeph>reg</codeph>. |
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34 This is conditionally executed using <codeph>cc</codeph> as the execution |
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35 condition. </p><p>This macro should be used in preference to MRS instructions |
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36 to avoid problems related to syntax incompatibility between different assembler |
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37 versions. </p> <p><b>SETSPSR</b> </p><codeblock id="GUID-A5DA9C4A-1D08-5CCE-B507-25E778B80A2D" xml:space="preserve">SETSPSR reg</codeblock><p>Writes |
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38 the entire (all 32 bits) SPSR from the specified ARM general register <codeph>reg</codeph>. </p><p>This |
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39 macro should be used in preference to MRS instructions to avoid problems related |
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40 to syntax incompatibility between different assembler versions. </p> <p><b>CSETSPSR</b> </p><codeblock id="GUID-94F1C1A0-92E1-5F7D-B49A-A283303D10BC" xml:space="preserve">CSETSPSR reg, cc</codeblock><p>Writes |
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41 the entire (all 32 bits) SPSR from the specified ARM general register <codeph>reg</codeph>. |
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42 This is conditionally executed using <codeph>cc</codeph> as the execution |
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43 condition. </p><p>This macro should be used in preference to MRS instructions |
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44 to avoid problems related to syntax incompatibility between different assembler |
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45 versions. </p> <p><b>BOOTCALL</b> </p><codeblock id="GUID-EDAA1A5D-8067-5754-8FED-2B0C5E68F687" xml:space="preserve">BOOTCALL call_numbe</codeblock><p>Calls |
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46 the specified function via the boot table. <codeph>call_number</codeph> should |
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47 be one of the <codeph>BTF_*</codeph> values in the <codeph>TBootTableEntry</codeph> enumeration, |
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48 defined in <filepath>os/kernelhwsrv/kernel/eka/include/kernel/arm/bootdefs.h</filepath>. </p><p>The |
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49 macro is transparent; the function is entered with all registers and flags |
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50 having the same values as immediately before the macro. </p> <p><b>GETPARAM</b> </p><codeblock id="GUID-3A25AFEF-8195-555B-B328-4BA1A8988D1F" xml:space="preserve">GETPARAM pnum, default</codeblock><p>Retrieves |
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51 the parameter with number <codeph>pnum</codeph> from the boot parameter table, |
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52 and returns its value in <codeph>R0</codeph>. If the parameter is not present |
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53 in the table, then <codeph>R0</codeph> is loaded with value <codeph>default</codeph>. </p><p>See |
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54 the description of <xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita#GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE/GUID-4DEA1D4C-EC7B-5F9A-A293-A7F80899044B">BTF_Params</xref> for |
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55 more information on the boot parameter table. </p> <p><b>GETMPARAM</b> </p><codeblock id="GUID-5DA2A8EA-6D2E-5ECD-80B9-FDD1CDEE1797" xml:space="preserve">GETMPARAM pnum</codeblock><p>Retrieves |
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56 the parameter with number <codeph>pnum</codeph> from the boot parameter table, |
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57 and returns its value in <codeph>R0</codeph>. If the parameter is not present |
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58 in the table, then the macro faults the system. </p><p>See the description |
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59 of <xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita#GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE/GUID-4DEA1D4C-EC7B-5F9A-A293-A7F80899044B">BTF_Params</xref> for |
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60 more information on the boot parameter table. </p> <p><b>FAULT</b> </p><codeblock id="GUID-8C551296-DAF8-57D3-9048-3B06387820AB" xml:space="preserve">FAULT cc</codeblock><p>Faults |
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61 the system if condition <codeph>cc</codeph> is true. The condition is a standard |
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62 ARM condition code. </p> <p id="GUID-B5EC22B5-B995-5D54-8F33-1B6FCE11BB3F"><b>BTP_ENTRY</b></p> <p>Declares |
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63 MMU permissions and cache attributes. The macro takes a variable number of |
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64 arguments depending on the processor in use. </p><p>For ARM architecture 6 |
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65 CPUs: </p><codeblock id="GUID-7CD2FE06-23C4-569A-AFBB-D62BE8CE2CC9" xml:space="preserve">BTP_ENTRY $domain, $perm, $cache, $execute, $global, $P, $S</codeblock> <p>For |
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66 XScale CPUs: </p><codeblock id="GUID-1E6704C5-AABA-51E3-8C6B-233E6A188829" xml:space="preserve">BTP_ENTRY $domain, $perm, $cache, $P</codeblock> <p>For |
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67 other CPUs: </p><codeblock id="GUID-1D95F820-E5FC-5A95-B4D7-051F9A5DD70C" xml:space="preserve">BTP_ENTRY $domain, $perm, $cache</codeblock> <table id="GUID-99F49C22-9194-565E-8C8A-F4D864311A8B"> |
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68 <tgroup cols="2"><colspec colname="col0"/><colspec colname="col1"/> |
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69 <tbody> |
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70 <row> |
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71 <entry><p>$domain </p> </entry> |
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72 <entry><p>ARM domain number 0-15. In general only one memory-model-dependent |
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73 value is used here and the symbol <codeph>CLIENT_DOMAIN</codeph> specifies |
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74 this. </p></entry> |
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75 </row> |
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76 <row> |
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77 <entry><p>$perm </p> </entry> |
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78 <entry><p>Permissions for mapping. </p><p>For architecture 6 CPUs, use one |
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79 of <codeph>PERM_NONO</codeph>, <codeph>PERM_RWNO</codeph>, <codeph>PERM_RWRO</codeph>, <codeph>PERM_RWRW</codeph>, <codeph>PERM_RONO</codeph>, <codeph>PERM_RORO</codeph>. </p><p>For other CPUs, use one of <codeph>PERM_RORO</codeph>, <codeph>PERM_RWNO</codeph>, <codeph>PERM_RWRO</codeph>, <codeph>PERM_RWRW</codeph>. </p><p>In each of these names the first pair of letters |
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80 refers to supervisor, and the second pair to user access, so <codeph>PERM_RWNO</codeph> means |
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81 supervisor read/write, user no access. </p></entry> |
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82 </row> |
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83 <row> |
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84 <entry><p>$cache </p> </entry> |
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85 <entry><p>Cache attributes for mapping. These are processor dependent - see |
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86 the <codeph>CACHE_*</codeph> macros in <filepath>os/kernelhwsrv/kernel/eka/include/kernel/arm/bootcpu.inc</filepath>. </p></entry> |
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87 </row> |
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88 <row> |
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89 <entry><p>$execute </p> </entry> |
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90 <entry><p>ARM architecture 6 only. Determines whether code can be executed |
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91 from the mapped region; either <codeph>BTPERM_EXECUTE</codeph> or <codeph>BTPERM_NO_EXECUTE</codeph>. </p> </entry> |
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92 </row> |
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93 <row> |
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94 <entry><p>$global </p> </entry> |
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95 <entry><p>ARM architecture 6 only. Determines whether the mapped region is |
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96 ASID specific (local) or non-ASID specific (global); either <codeph>BTPERM_LOCAL</codeph> or <codeph>BTPERM_GLOBAL</codeph>. </p> </entry> |
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97 </row> |
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98 <row> |
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99 <entry><p>$P </p> </entry> |
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100 <entry><p>ARM architecture 6 and XScale only. Determines whether or not ECC |
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101 should be used on the mapped region (assuming hardware supports ECC); either <codeph>BTPERM_ECC</codeph> or <codeph>BTPERM_NON_ECC</codeph>. </p> </entry> |
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102 </row> |
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103 <row> |
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104 <entry><p>$S </p> </entry> |
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105 <entry><p>ARM architecture 6 only. Determines whether the mapped region is |
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106 shared between multiple CPUs or not; either <codeph>BTPERM_SHARED</codeph> or <codeph>BTPERM_NON_SHARED</codeph>. </p> </entry> |
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107 </row> |
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108 </tbody> |
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109 </tgroup> |
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110 </table> <p id="GUID-7361BC74-7164-52EE-9A5B-D254560D1939"><b>ROM_BANK</b> </p><codeblock id="GUID-7685BA97-8DC4-537C-AEBC-110AB0981DD0" xml:space="preserve">ROM_BANK PHYS, SIZE, LIN, WIDTH, TYPE, RAND, SEQ</codeblock><p>Declares |
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111 an XIP ROM bank entry. </p> <table id="GUID-F701B695-A499-57E0-97B6-7C5701E09F77"> |
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112 <tgroup cols="2"><colspec colname="col0"/><colspec colname="col1"/> |
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113 <tbody> |
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114 <row> |
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115 <entry><p>PHYS </p> </entry> |
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116 <entry><p>The physical base address of the ROM bank. </p> </entry> |
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117 </row> |
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118 <row> |
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119 <entry><p>SIZE </p> </entry> |
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120 <entry><p>The size of the ROM bank. </p> </entry> |
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121 </row> |
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122 <row> |
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123 <entry><p>LIN </p> </entry> |
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124 <entry><p>Linear address override (usually 0). </p> </entry> |
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125 </row> |
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126 <row> |
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127 <entry><p>WIDTH </p> </entry> |
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128 <entry><p>Bus width. One of: <codeph>ROM_WIDTH_8</codeph>, <codeph>ROM_WIDTH_16</codeph> or <codeph>ROM_WIDTH_32</codeph> </p> </entry> |
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129 </row> |
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130 <row> |
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131 <entry><p>TYPE </p> </entry> |
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132 <entry><p>The ROM type; see the <xref href="GUID-C1232A34-6E4C-3AAF-8E97-8BA2303B9508.dita"><apiname>TRomType</apiname></xref> enumeration. </p> </entry> |
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133 </row> |
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134 <row> |
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135 <entry><p>RAND </p> </entry> |
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136 <entry><p>Random access speed. </p> </entry> |
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137 </row> |
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138 <row> |
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139 <entry><p>SEQ </p> </entry> |
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140 <entry><p>Sequential access speed. </p> </entry> |
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141 </row> |
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142 </tbody> |
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143 </tgroup> |
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144 </table> <p>See also <xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita#GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE/GUID-52792290-48DA-5F1A-A7AD-0105A8AA37CF">BTF_RomBanks</xref> in <xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita">Boot Table Functions</xref>. </p> </section> |
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145 <section id="GUID-7728C7F2-BB04-518B-8B0A-752CB799A561"><title>Macros for |
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146 declaring I/O mappings</title> <p id="GUID-13254CB0-3659-5338-A3C2-1277F6869CA7"><b>HW_MAPPING</b> </p><codeblock id="GUID-5A4745F8-8B21-593B-85AF-4C56D7DA7075" xml:space="preserve">HW_MAPPING PHYS,SIZE,MULT</codeblock><p>Defines |
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147 an I/O mapping using the standard permissions and cache attributes for I/O |
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148 mappings, i.e. those defined for the <codeph>BTP_Hw</codeph> boot table entry. |
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149 See <xref href="GUID-C92CC81A-35A1-5860-AA08-C8C08B39804C.dita">Boot Table MMU |
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150 Permission and Cache Attribute Definitions</xref>. </p> <table id="GUID-9B975DEB-0D16-5DEE-8E11-7109E052D409"> |
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151 <tgroup cols="2"><colspec colname="col0"/><colspec colname="col1"/> |
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152 <tbody> |
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153 <row> |
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154 <entry><p>PHYS </p> </entry> |
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155 <entry><p>Physical base address. </p> </entry> |
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156 </row> |
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157 <row> |
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158 <entry><p>SIZE </p> </entry> |
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159 <entry><p>Size of the mapping. </p> </entry> |
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160 </row> |
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161 <row> |
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162 <entry><p>MULT </p> </entry> |
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163 <entry><p> <xref href="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C.dita#GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C/GUID-B13C34B2-69E5-51A2-8807-5576FD091C34">Granularity |
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164 of the I/O mapping</xref> (below). </p> </entry> |
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165 </row> |
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166 </tbody> |
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167 </tgroup> |
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168 </table> <p>See also: </p><ul> |
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169 <li id="GUID-75387946-50A1-5D24-A5C4-4AED7954ACAF"><p><xref href="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C.dita#GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C/GUID-20A2344A-1BE2-5AFD-BC37-997F08E2A28C">Determining the linear address</xref> (below). </p> </li> |
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170 <li id="GUID-2DD01E2F-841B-5242-9757-A48F6036AE6A"><p><xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita#GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE/GUID-62CD8D6F-6E12-5DFC-85BC-EA24000BA588">BTF_HwBanks</xref> in <xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita">Boot |
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171 Table Functions</xref>. </p></li> |
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172 </ul> <p id="GUID-EF703014-E498-5623-ACC6-8E3E9882C681"><b>HW_MAPPING_EXT</b> </p><codeblock id="GUID-EEAFCF55-9C2F-5EE6-9A37-287772F4BCF4" xml:space="preserve">HW_MAPPING_EXT PHYS,SIZE,MULT</codeblock><p>Defines |
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173 an I/O mapping using the permissions and cache attributes defined by a <codeph>BTP_ENTRY</codeph> macro |
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174 that immediately follows this macro. See <xref href="GUID-C92CC81A-35A1-5860-AA08-C8C08B39804C.dita">Boot |
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175 Table MMU Permission and Cache Attribute Definitions</xref>. </p><table id="GUID-8186D7BA-30AC-5A3A-BF25-6AB6984B0A45"> |
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176 <tgroup cols="2"><colspec colname="col0"/><colspec colname="col1"/> |
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177 <tbody> |
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178 <row> |
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179 <entry><p>PHYS </p> </entry> |
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180 <entry><p>Physical base address. </p> </entry> |
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181 </row> |
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182 <row> |
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183 <entry><p>SIZE </p> </entry> |
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184 <entry><p>Size of the mapping. </p> </entry> |
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185 </row> |
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186 <row> |
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187 <entry><p>MULT </p> </entry> |
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188 <entry><p> <xref href="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C.dita#GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C/GUID-B13C34B2-69E5-51A2-8807-5576FD091C34">Granularity |
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189 of the I/O mapping</xref> (below). </p> </entry> |
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190 </row> |
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191 </tbody> |
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192 </tgroup> |
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193 </table> <p>See also: </p> <ul> |
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194 <li id="GUID-460D2F0F-F42B-58CD-910B-5DEEE210F061"><p> <xref href="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C.dita#GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C/GUID-20A2344A-1BE2-5AFD-BC37-997F08E2A28C">Determining the linear address</xref> (below). </p> </li> |
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195 <li id="GUID-D13EB05F-E447-51EA-BF15-0AA3870BE101"><p><xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita#GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE/GUID-62CD8D6F-6E12-5DFC-85BC-EA24000BA588">BTF_HwBanks</xref> in <xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita">Boot |
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196 Table Functions</xref>. </p> </li> |
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197 </ul> <p id="GUID-7402DE22-6CB9-5236-BA3B-99D6CE40A381"><b>HW_MAPPING_EXT2</b> </p><codeblock id="GUID-6F0B0F0D-CBE6-5320-9F51-39388B4181E6" xml:space="preserve">HW_MAPPING_EXT2 PHYS,SIZE,MULT,LIN</codeblock><p>Defines |
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198 an I/O mapping using the standard permissions and cache attributes for I/O |
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199 mappings, i.e. those defined for the <codeph>BTP_Hw</codeph> boot table entry. |
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200 See <xref href="GUID-C92CC81A-35A1-5860-AA08-C8C08B39804C.dita">Boot Table MMU |
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201 Permission and Cache Attribute Definitions</xref>. </p> <table id="GUID-55243AD3-DF9F-5D9D-9549-35F577C20E83"> |
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202 <tgroup cols="2"><colspec colname="col0"/><colspec colname="col1"/> |
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203 <tbody> |
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204 <row> |
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205 <entry><p>PHYS </p> </entry> |
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206 <entry><p>Physical base address. </p> </entry> |
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207 </row> |
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208 <row> |
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209 <entry><p>SIZE </p> </entry> |
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210 <entry><p>Size of the mapping. </p> </entry> |
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211 </row> |
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212 <row> |
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213 <entry><p>MULT </p> </entry> |
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214 <entry><p> <xref href="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C.dita#GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C/GUID-B13C34B2-69E5-51A2-8807-5576FD091C34">Granularity |
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215 of the I/O mapping</xref> (below). </p> </entry> |
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216 </row> |
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217 <row> |
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218 <entry><p>LIN </p> </entry> |
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219 <entry><p>Linear address. </p> </entry> |
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220 </row> |
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221 </tbody> |
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222 </tgroup> |
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223 </table> <p>See also <xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita#GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE/GUID-62CD8D6F-6E12-5DFC-85BC-EA24000BA588">BTF_HwBanks</xref> in <xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita">Boot Table Functions</xref>. </p> <p id="GUID-9F79FF06-C8E8-599A-875A-D772FB6E8862"><b>HW_MAPPING_EXT3</b> </p><codeblock id="GUID-C1948F05-F4C7-5DCC-A266-0489F5A0BC00" xml:space="preserve">HW_MAPPING_EXT3 PHYS,SIZE,MULT,LIN</codeblock><p>Defines |
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224 an I/O mapping using the permissions and cache attributes defined by a <codeph>BTP_ENTRY</codeph> macro |
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225 that immediately follows this macro. See <xref href="GUID-C92CC81A-35A1-5860-AA08-C8C08B39804C.dita">Boot |
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226 Table MMU Permission and Cache Attribute Definitions</xref>. </p> <table id="GUID-D7252A3A-F7ED-5A78-94B2-B736AC61046E"> |
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227 <tgroup cols="2"><colspec colname="col0"/><colspec colname="col1"/> |
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228 <tbody> |
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229 <row> |
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230 <entry><p>PHYS </p> </entry> |
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231 <entry><p>Physical base address. </p> </entry> |
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232 </row> |
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233 <row> |
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234 <entry><p>SIZE </p> </entry> |
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235 <entry><p>Size of the mapping. </p> </entry> |
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236 </row> |
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237 <row> |
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238 <entry><p>MULT </p> </entry> |
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239 <entry><p> <xref href="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C.dita#GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C/GUID-B13C34B2-69E5-51A2-8807-5576FD091C34">Granularity |
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240 of the I/O mapping</xref> (below). </p> </entry> |
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241 </row> |
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242 <row> |
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243 <entry><p>LIN </p> </entry> |
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244 <entry><p>Linear address. </p> </entry> |
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245 </row> |
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246 </tbody> |
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247 </tgroup> |
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248 </table> <p>See also <xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita#GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE/GUID-62CD8D6F-6E12-5DFC-85BC-EA24000BA588">BTF_HwBanks</xref> in <xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita">Boot Table Functions</xref>.. </p> <p id="GUID-B13C34B2-69E5-51A2-8807-5576FD091C34"><b>Granularity of the I/O mapping</b> </p> <p>The |
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249 granularity of the I/O mapping is defined by the <codeph>MULT</codeph> parameter |
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250 of the I/O mapping macros: <xref href="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C.dita#GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C/GUID-13254CB0-3659-5338-A3C2-1277F6869CA7">HW_MAPPING</xref>, <xref href="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C.dita#GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C/GUID-EF703014-E498-5623-ACC6-8E3E9882C681">HW_MAPPING_EXT</xref>, <xref href="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C.dita#GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C/GUID-7402DE22-6CB9-5236-BA3B-99D6CE40A381">HW_MAPPING_EXT2</xref> and <xref href="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C.dita#GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C/GUID-9F79FF06-C8E8-599A-875A-D772FB6E8862">HW_MAPPING_EXT3</xref>. </p> <p>The <codeph>MULT</codeph> parameter specifies the granularity of the mapping. It takes one of the |
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251 following values: </p> <ul> |
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252 <li id="GUID-AA1B0CD5-6336-5C02-AF02-562AB4A44FA3"><p> <codeph>HW_MULT_4K</codeph> use |
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253 4K pages. The <codeph>PHYS</codeph> and <codeph>LIN</codeph> parameters must |
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254 be multiples of 4K. </p> </li> |
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255 <li id="GUID-15DC0CE0-B90C-500C-90FD-F750F61F509B"><p> <codeph>HW_MULT_64K</codeph> use |
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256 64K pages. The <codeph>PHYS</codeph> and <codeph>LIN</codeph> parameters must |
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257 be multiples of 64K. </p> </li> |
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258 <li id="GUID-DE644971-8E56-5921-85BD-BC79AAD66C49"><p> <codeph>HW_MULT_1M</codeph> use |
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259 1M sections. The <codeph>PHYS</codeph> and <codeph>LIN</codeph> parameters |
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260 must be multiples of 1M. </p> </li> |
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261 </ul> <p>In each case the unit in which the <codeph>SIZE</codeph> parameter |
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262 is specified is <codeph>MULT</codeph>, that is to say the actual mapping size |
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263 in bytes is <codeph>SIZE*MULT</codeph>. For example: </p><codeblock id="GUID-5B389113-F6DB-5011-8B59-93F599519E94" xml:space="preserve">HW_MAPPING 0x80000000, 1, HW_MULT_4K |
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264 HW_MAPPING 0x80010000, 3, HW_MULT_64K</codeblock><p>declares a mapping |
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265 of size 4K starting at physical address <codeph>0x80000000</codeph> followed |
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266 by a mapping of 192K in 64K pages starting at physical address <codeph>0x80010000</codeph>. </p> <p id="GUID-20A2344A-1BE2-5AFD-BC37-997F08E2A28C"><b>Determining the linear address</b> </p> <p>For |
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267 those macros that don't specify a linear address: <xref href="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C.dita#GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C/GUID-13254CB0-3659-5338-A3C2-1277F6869CA7">HW_MAPPING</xref> and <xref href="GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C.dita#GUID-25941CD2-D124-55DD-8716-ACC93E3F1D6C/GUID-EF703014-E498-5623-ACC6-8E3E9882C681">HW_MAPPING_EXT</xref>, |
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268 it is determined as follows: </p> <ul> |
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269 <li id="GUID-37DB1D7B-0D4B-5E3C-9E7F-F195D7A1B95C"><p>On the direct memory |
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270 model, it is equal to the physical address. </p> </li> |
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271 <li id="GUID-77168F6C-3B11-5B32-AEF1-B77046A0EC78"><p>On the moving memory |
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272 model and the multiple memory model, the first such mapping is placed at <codeph>KPrimaryIOBase</codeph> (<codeph>0x63000000</codeph> on |
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273 the moving model, <codeph>0xC3000000</codeph> on the multiple model). Each |
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274 mapping first rounds the linear address counter up to the next multiple of <codeph>MULT</codeph> before |
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275 making the mapping, then increments it by <codeph>SIZE*MULT</codeph> after |
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276 making it. </p> </li> |
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277 </ul> <p>For example, on the moving memory model, the following mappings would |
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278 have linear addresses <codeph>0x63000000</codeph>, <codeph>0x63002000</codeph>, <codeph>0x63010000</codeph>, <codeph>0x63020000</codeph> and <codeph>0x63100000</codeph> respectively: </p><codeblock id="GUID-529F87FB-7DD6-521F-8397-667C710843E2" xml:space="preserve">HW_MAPPING 0x80000000, 2, HW_MULT_4K |
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279 HW_MAPPING 0x80010000, 1, HW_MULT_4K |
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280 HW_MAPPING 0x80100000, 1, HW_MULT_64K |
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281 HW_MAPPING 0x80200000, 1, HW_MULT_4K |
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282 HW_MAPPING 0x90000000, 1, HW_MULT_1M</codeblock> <p>For the direct memory |
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283 model, all I/O mappings required by the system must be listed here since it |
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284 is not possible to make further mappings once the kernel is running. </p> </section> |
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285 </conbody></concept> |