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1 <?xml version="1.0" encoding="utf-8"?> |
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2 <!-- Copyright (c) 2007-2010 Nokia Corporation and/or its subsidiary(-ies) All rights reserved. --> |
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3 <!-- This component and the accompanying materials are made available under the terms of the License |
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4 "Eclipse Public License v1.0" which accompanies this distribution, |
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5 and is available at the URL "http://www.eclipse.org/legal/epl-v10.html". --> |
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6 <!-- Initial Contributors: |
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7 Nokia Corporation - initial contribution. |
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8 Contributors: |
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9 --> |
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10 <!DOCTYPE concept |
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11 PUBLIC "-//OASIS//DTD DITA Concept//EN" "concept.dtd"> |
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12 <concept id="GUID-7ECDCF7B-3B2A-561F-9136-04BC4DAE46E4" xml:lang="en"><title>ARM |
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13 Exception Types, Fault Status Register Values, and Processor Mode Values</title><shortdesc>Reference for users of the debug monitor tool to ARM exception |
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14 types, fault status register values, and processor mode values. </shortdesc><prolog><metadata><keywords/></metadata></prolog><conbody> |
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15 <section id="GUID-567330BE-A308-50CD-9EB8-891E45FA8294"><title>ARM exception |
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16 types</title> <p>The numeric value in the left hand column is the value of |
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17 the <codeph>ExcId</codeph> field displayed as a result of entering an <xref href="GUID-08E14B34-5144-5AA8-AA55-7AF03671676C.dita#GUID-08E14B34-5144-5AA8-AA55-7AF03671676C/GUID-D5F2E0AF-EF03-5150-813B-DF989F12C47B">f</xref> command |
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18 in the debug monitor. </p> <table id="GUID-D87BD88D-734C-571F-A02F-039AB98B3906"> |
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19 <tgroup cols="2"><colspec colname="col0"/><colspec colname="col1"/> |
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20 <tbody> |
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21 <row> |
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22 <entry><p> <codeph>00000000</codeph> </p> </entry> |
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23 <entry><p>Prefetch abort </p> </entry> |
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24 </row> |
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25 <row> |
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26 <entry><p> <codeph>00000001</codeph> </p> </entry> |
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27 <entry><p>Data abort </p> </entry> |
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28 </row> |
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29 <row> |
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30 <entry><p> <codeph>00000002</codeph> </p> </entry> |
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31 <entry><p>Undefined instruction </p> </entry> |
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32 </row> |
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33 </tbody> |
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34 </tgroup> |
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35 </table> </section> |
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36 <section id="GUID-E55E7DA9-61DC-57D9-9678-05D490FEE604"><title>Fault status |
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37 register values (FSR register)</title> <p>The lowest 4-bits of the FSR register |
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38 indicates the fault generated by the MMU. The FSR register value is displayed |
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39 as a result of entering an <xref href="GUID-08E14B34-5144-5AA8-AA55-7AF03671676C.dita#GUID-08E14B34-5144-5AA8-AA55-7AF03671676C/GUID-D5F2E0AF-EF03-5150-813B-DF989F12C47B">f</xref> command |
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40 in the debug monitor. </p> <table id="GUID-502176DF-8084-5D06-8443-29D64B2BDC33"> |
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41 <tgroup cols="2"><colspec colname="col0"/><colspec colname="col1"/> |
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42 <tbody> |
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43 <row> |
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44 <entry><p> <codeph>0</codeph> </p> </entry> |
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45 <entry><p>Vector exception </p> </entry> |
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46 </row> |
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47 <row> |
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48 <entry><p> <codeph>1</codeph> </p> </entry> |
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49 <entry><p>Alignment fault </p> </entry> |
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50 </row> |
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51 <row> |
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52 <entry><p> <codeph>2</codeph> </p> </entry> |
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53 <entry><p>Terminal exception </p> </entry> |
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54 </row> |
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55 <row> |
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56 <entry><p> <codeph>3</codeph> </p> </entry> |
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57 <entry><p>Alignment fault </p> </entry> |
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58 </row> |
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59 <row> |
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60 <entry><p> <codeph>4</codeph> </p> </entry> |
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61 <entry><p>External abort on linefetch for section translation </p> </entry> |
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62 </row> |
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63 <row> |
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64 <entry><p> <codeph>5</codeph> </p> </entry> |
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65 <entry><p>Section translation fault (unmapped virtual address) </p> </entry> |
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66 </row> |
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67 <row> |
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68 <entry><p> <codeph>6</codeph> </p> </entry> |
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69 <entry><p>External abort on linefetch for page translation </p> </entry> |
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70 </row> |
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71 <row> |
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72 <entry><p> <codeph>7</codeph> </p> </entry> |
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73 <entry><p>Page translation fault (unmapped virtual address) </p> </entry> |
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74 </row> |
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75 <row> |
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76 <entry><p> <codeph>8</codeph> </p> </entry> |
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77 <entry><p>External abort on non-linefetch for section translation </p> </entry> |
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78 </row> |
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79 <row> |
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80 <entry><p> <codeph>9</codeph> </p> </entry> |
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81 <entry><p>Domain fault on section translation (i.e. accessing invalid domain) </p> </entry> |
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82 </row> |
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83 <row> |
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84 <entry><p> <codeph>A</codeph> </p> </entry> |
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85 <entry><p>External abort on non-linefetch for page translation </p> </entry> |
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86 </row> |
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87 <row> |
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88 <entry><p> <codeph>B</codeph> </p> </entry> |
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89 <entry><p>Domain fault on page translation (i.e. accessing invalid domain) </p> </entry> |
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90 </row> |
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91 <row> |
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92 <entry><p> <codeph>C</codeph> </p> </entry> |
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93 <entry><p>External abort on first level translation </p> </entry> |
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94 </row> |
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95 <row> |
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96 <entry><p> <codeph>D</codeph> </p> </entry> |
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97 <entry><p>Permission fault on section (i.e. no permission to access virtual |
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98 address) </p> </entry> |
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99 </row> |
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100 <row> |
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101 <entry><p> <codeph>E</codeph> </p> </entry> |
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102 <entry><p>External abort on second level translation </p> </entry> |
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103 </row> |
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104 <row> |
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105 <entry><p> <codeph>F</codeph> </p> </entry> |
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106 <entry><p>Permission fault on page (i.e. no permission to access virtual address) </p> </entry> |
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107 </row> |
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108 </tbody> |
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109 </tgroup> |
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110 </table> </section> |
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111 <section id="GUID-BFA2235C-1598-59E6-9F1F-A8281F13A957"><title>ARM processor |
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112 modes (CPSR register)</title> <p>The 5 least-significant bits of the CPSR |
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113 register indicate the ARM processor mode. The CPSR register value is displayed |
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114 as a result of entering an <xref href="GUID-08E14B34-5144-5AA8-AA55-7AF03671676C.dita#GUID-08E14B34-5144-5AA8-AA55-7AF03671676C/GUID-D5F2E0AF-EF03-5150-813B-DF989F12C47B">f</xref> command |
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115 in the debug monitor. </p> <table id="GUID-6B7CF34F-384D-52BF-9C72-C4D8E8B42633"> |
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116 <tgroup cols="3"><colspec colname="col0"/><colspec colname="col1"/><colspec colname="col2"/> |
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117 <tbody> |
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118 <row> |
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119 <entry><p> <b>CPSR[4:0]</b> </p> </entry> |
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120 <entry><p> <b>Mode</b> </p> </entry> |
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121 <entry><p> <b>Register set</b> </p> </entry> |
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122 </row> |
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123 <row> |
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124 <entry><p>10000 </p> </entry> |
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125 <entry><p>User </p> </entry> |
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126 <entry><p>PC, R14..R0, CPSR </p> </entry> |
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127 </row> |
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128 <row> |
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129 <entry><p>10001 </p> </entry> |
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130 <entry><p>FIQ </p> </entry> |
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131 <entry><p>PC, R14_fiq..R8_fiq, R7-R0, CPSR, SPSR_fiq </p> </entry> |
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132 </row> |
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133 <row> |
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134 <entry><p>10010 </p> </entry> |
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135 <entry><p>IRQ </p> </entry> |
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136 <entry><p>PC, R14_irq, R13_irq, R12-R0, CPSR, SPSR_irq </p> </entry> |
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137 </row> |
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138 <row> |
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139 <entry><p>10011 </p> </entry> |
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140 <entry><p>SVC </p> </entry> |
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141 <entry><p>PC, R14_svc, R13_svc, R12-R0, CPSR, SPSR_sv </p> </entry> |
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142 </row> |
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143 <row> |
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144 <entry><p>10111 </p> </entry> |
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145 <entry><p>Abort </p> </entry> |
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146 <entry><p>PC, R14_abt, R13_abt, R12-R0, CPSR, SPSR_abt </p> </entry> |
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147 </row> |
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148 <row> |
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149 <entry><p>11011 </p> </entry> |
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150 <entry><p>Undef </p> </entry> |
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151 <entry><p>PC, R14_und, R13_und, R12-R0, CPSR, SPSR_und </p> </entry> |
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152 </row> |
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153 <row> |
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154 <entry><p>11111 </p> </entry> |
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155 <entry><p>System </p> </entry> |
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156 <entry><p>PC, R14..R0, CPSR </p> </entry> |
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157 </row> |
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158 </tbody> |
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159 </tgroup> |
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160 </table> </section> |
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161 </conbody></concept> |