64 <section id="GUID-9026A4AC-57AF-545D-887C-AF43E0B37EDC"><title>Chained interrupts</title> <p>A |
64 <section id="GUID-9026A4AC-57AF-545D-887C-AF43E0B37EDC"><title>Chained interrupts</title> <p>A |
65 system may have multiple interrupt controllers to handle a large number of |
65 system may have multiple interrupt controllers to handle a large number of |
66 interrupt sources. These are usually prioritised by connecting the interrupt |
66 interrupt sources. These are usually prioritised by connecting the interrupt |
67 output of a lower-priority controller to an interrupt input of a higher-priority |
67 output of a lower-priority controller to an interrupt input of a higher-priority |
68 controller. This is called chaining. </p> <fig id="GUID-49264B94-DF6D-5F11-8815-D42CDBF94E39"> |
68 controller. This is called chaining. </p> <fig id="GUID-49264B94-DF6D-5F11-8815-D42CDBF94E39"> |
69 <image href="GUID-0DB79535-E4E6-50BD-852D-B2F177202C9C_d0e375610_href.png" placement="inline"/> |
69 <image href="GUID-0DB79535-E4E6-50BD-852D-B2F177202C9C_d0e381454_href.png" placement="inline"/> |
70 </fig> <p>An interrupt from a lower priority controller will appear as an |
70 </fig> <p>An interrupt from a lower priority controller will appear as an |
71 interrupt on the highest-priority controller. </p> <p>When the interrupt dispatcher |
71 interrupt on the highest-priority controller. </p> <p>When the interrupt dispatcher |
72 of the higher-priority controller detects that it is the chained interrupt |
72 of the higher-priority controller detects that it is the chained interrupt |
73 that is pending, the usual way of dealing with this is to run a secondary |
73 that is pending, the usual way of dealing with this is to run a secondary |
74 dispatcher to determine which interrupt on the chained controller is pending. </p> <p>There |
74 dispatcher to determine which interrupt on the chained controller is pending. </p> <p>There |
75 may be further levels of chaining before the true source of the interrupt |
75 may be further levels of chaining before the true source of the interrupt |
76 has been identified. </p> </section> |
76 has been identified. </p> </section> |
77 <section id="GUID-ED6F2F47-7A16-5AE6-8E5B-B2475F6EDEAA"><title>Multiple interrupt |
77 <section id="GUID-ED6F2F47-7A16-5AE6-8E5B-B2475F6EDEAA"><title>Multiple interrupt |
78 sources and pseudo interrupt sources</title> <p>It is possible that a single |
78 sources and pseudo interrupt sources</title> <p>It is possible that a single |
79 input to an interrupt controller is shared by several interrupt sources. </p> <fig id="GUID-DC96E3A8-9820-5CD4-8020-3B55398388D9"> |
79 input to an interrupt controller is shared by several interrupt sources. </p> <fig id="GUID-DC96E3A8-9820-5CD4-8020-3B55398388D9"> |
80 <image href="GUID-DCBBDFA7-1E6C-5B00-A13E-A25794668E12_d0e375632_href.png" placement="inline"/> |
80 <image href="GUID-DCBBDFA7-1E6C-5B00-A13E-A25794668E12_d0e381476_href.png" placement="inline"/> |
81 </fig> <p>It appears necessary to bind multiple ISRs to the same interrupt. |
81 </fig> <p>It appears necessary to bind multiple ISRs to the same interrupt. |
82 However, this is not possible. There are two ways of dealing with this: </p> <ul> |
82 However, this is not possible. There are two ways of dealing with this: </p> <ul> |
83 <li id="GUID-0D954444-C2C3-51CC-8E1D-7EB063CDACAA"><p>Maintain a list of all |
83 <li id="GUID-0D954444-C2C3-51CC-8E1D-7EB063CDACAA"><p>Maintain a list of all |
84 ISRs that are bound to this single interrupt source, and call all the ISRs |
84 ISRs that are bound to this single interrupt source, and call all the ISRs |
85 in the list when the interrupt is dispatched. This is most conveniently implemented |
85 in the list when the interrupt is dispatched. This is most conveniently implemented |
120 an example, the core layer for the template reference board defines a class <codeph>TemplateAssp</codeph> that |
120 an example, the core layer for the template reference board defines a class <codeph>TemplateAssp</codeph> that |
121 is derived from <xref href="GUID-A83A7C3C-7DC0-3B9C-842F-70FCC751365D.dita"><apiname>Asic</apiname></xref>. <codeph>TemplateAssp</codeph> defines |
121 is derived from <xref href="GUID-A83A7C3C-7DC0-3B9C-842F-70FCC751365D.dita"><apiname>Asic</apiname></xref>. <codeph>TemplateAssp</codeph> defines |
122 the pure virtual functions: <codeph>InterruptBind()</codeph>, <codeph>InterruptUnbind()</codeph>, <codeph>InterruptEnable()</codeph> etc, |
122 the pure virtual functions: <codeph>InterruptBind()</codeph>, <codeph>InterruptUnbind()</codeph>, <codeph>InterruptEnable()</codeph> etc, |
123 all with signatures that are the same for the comparable functions defined |
123 all with signatures that are the same for the comparable functions defined |
124 by <xref href="GUID-E7A7083C-97B9-39B9-A147-4A6E314EE3A3.dita"><apiname>Interrupt</apiname></xref>, and which are implemented by the <codeph>Template</codeph> class. </p> <fig id="GUID-458C7825-5B35-583C-BDF6-7DCD21DAE670"> |
124 by <xref href="GUID-E7A7083C-97B9-39B9-A147-4A6E314EE3A3.dita"><apiname>Interrupt</apiname></xref>, and which are implemented by the <codeph>Template</codeph> class. </p> <fig id="GUID-458C7825-5B35-583C-BDF6-7DCD21DAE670"> |
125 <image href="GUID-B7E7E6D6-7824-505C-BA0B-B7861897E78F_d0e375726_href.png" placement="inline"/> |
125 <image href="GUID-B7E7E6D6-7824-505C-BA0B-B7861897E78F_d0e381570_href.png" placement="inline"/> |
126 </fig> </section> |
126 </fig> </section> |
127 <section id="GUID-9D98586F-AD1D-5C50-9AD8-F81D72135382"><title>Spurious interrupts</title> <p>In |
127 <section id="GUID-9D98586F-AD1D-5C50-9AD8-F81D72135382"><title>Spurious interrupts</title> <p>In |
128 the Kernel Architecture 2, it is a convention that unbound interrupts should |
128 the Kernel Architecture 2, it is a convention that unbound interrupts should |
129 be bound to a "spurious" interrupt handler, i.e. an interrupt handler that |
129 be bound to a "spurious" interrupt handler, i.e. an interrupt handler that |
130 faults the system indicating the number of the interrupt. This aids debugging |
130 faults the system indicating the number of the interrupt. This aids debugging |
175 group IRQs at the start of the table, and FIQs at the end of the table. If |
175 group IRQs at the start of the table, and FIQs at the end of the table. If |
176 the hardware has separate interrupt controller hardware for IRQs and FIQs |
176 the hardware has separate interrupt controller hardware for IRQs and FIQs |
177 (or at least, different registers) then you will need to arrange the table |
177 (or at least, different registers) then you will need to arrange the table |
178 so that you can determine from the <xref href="GUID-76A30EC4-4B99-5471-9E80-F853C91485BC.dita#GUID-76A30EC4-4B99-5471-9E80-F853C91485BC/GUID-8E58F4C9-0290-55E0-A4FD-B6C2361BE205">interrupt |
178 so that you can determine from the <xref href="GUID-76A30EC4-4B99-5471-9E80-F853C91485BC.dita#GUID-76A30EC4-4B99-5471-9E80-F853C91485BC/GUID-8E58F4C9-0290-55E0-A4FD-B6C2361BE205">interrupt |
179 ID</xref> whether the interrupt is an IRQ or FIQ. </p> <p>For example: </p> <fig id="GUID-9DD2CC92-A5DB-5C78-A9A6-64402FF04FE2"> |
179 ID</xref> whether the interrupt is an IRQ or FIQ. </p> <p>For example: </p> <fig id="GUID-9DD2CC92-A5DB-5C78-A9A6-64402FF04FE2"> |
180 <image href="GUID-60949ACD-AAA9-540E-85AE-BB173382D548_d0e375842_href.png" placement="inline"/> |
180 <image href="GUID-60949ACD-AAA9-540E-85AE-BB173382D548_d0e381686_href.png" placement="inline"/> |
181 </fig> </section> |
181 </fig> </section> |
182 <section id="GUID-EACCBDFD-46CD-4D67-B60C-D705867C9116"><title>Location of |
182 <section id="GUID-EACCBDFD-46CD-4D67-B60C-D705867C9116"><title>Location of |
183 interrupt handling code</title> <p>Most of the interrupt dispatching code |
183 interrupt handling code</title> <p>Most of the interrupt dispatching code |
184 is implemented in the ASSP layer. This includes a list of ISRs, code for adding |
184 is implemented in the ASSP layer. This includes a list of ISRs, code for adding |
185 and removing ISRs, enabling and disabling interrupt sources, and dispatching |
185 and removing ISRs, enabling and disabling interrupt sources, and dispatching |