Symbian3/PDK/Source/GUID-8A00E047-3DCE-5D02-9ECE-1396DC99DA4B.dita
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    23 objects for such things as threads, processes, chunks, and inter-process communication. </p> </li>
    23 objects for such things as threads, processes, chunks, and inter-process communication. </p> </li>
    24 <li id="GUID-290A7566-8CC8-538F-930D-62B85FF73E75"><p> <i>Memory model</i>:
    24 <li id="GUID-290A7566-8CC8-538F-930D-62B85FF73E75"><p> <i>Memory model</i>:
    25 this provides per-process address spaces and inter-process data transfer,
    25 this provides per-process address spaces and inter-process data transfer,
    26 and governs how memory is allocated and mapped. It encapsulates access to
    26 and governs how memory is allocated and mapped. It encapsulates access to
    27 the hardware Memory Management Unit (MMU), allowing the nanokernel and the
    27 the hardware Memory Management Unit (MMU), allowing the nanokernel and the
    28 Symbian OS kernel to be MMU-independent. </p> </li>
    28 Symbian platform kernel to be MMU-independent. </p> </li>
    29 <li id="GUID-5324322B-BC5E-5D08-BD9A-DA22EC41CFF4"><p> <i>Variant DLL</i>:
    29 <li id="GUID-5324322B-BC5E-5D08-BD9A-DA22EC41CFF4"><p> <i>Variant DLL</i>:
    30 this provides hardware dependent services required by the kernel, for example
    30 this provides hardware dependent services required by the kernel, for example
    31 timer tick interrupts and Real Time Clock access. Systems based on an ASSP
    31 timer tick interrupts and Real Time Clock access. Systems based on an ASSP
    32 also have an ASSP DLL, which shares some of the variant DLLs responsibilities.
    32 also have an ASSP DLL, which shares some of the variant DLLs responsibilities.
    33 Board Support Packages provides variant libraries for reference hardware. </p> </li>
    33 Board Support Packages provides variant libraries for reference hardware. </p> </li>
    37 </ul>
    37 </ul>
    38 <p>The following diagram shows how the place of the kernel between the low-level
    38 <p>The following diagram shows how the place of the kernel between the low-level
    39 user side code, such as the user library, and the device hardware: </p>
    39 user side code, such as the user library, and the device hardware: </p>
    40 <fig id="GUID-9B3AF7EC-8339-5F92-B4BC-20DD3331F103">
    40 <fig id="GUID-9B3AF7EC-8339-5F92-B4BC-20DD3331F103">
    41 <title>           Kernel architectural relationships          </title>
    41 <title>           Kernel architectural relationships          </title>
    42 <image href="GUID-C842C016-0D1B-5462-8B04-49CFE941A964_d0e365435_href.jpg" placement="inline"/>
    42 <image href="GUID-C842C016-0D1B-5462-8B04-49CFE941A964_d0e386668_href.jpg" placement="inline"/>
    43 </fig>
    43 </fig>
    44 <p>The implementation of these parts is split into code that is hardware independent,
    44 <p>The implementation of these parts is split into code that is hardware independent,
    45 and code that is dependent on the hardware platform. Hardware dependent code
    45 and code that is dependent on the hardware platform. Hardware dependent code
    46 is divided into a number of layers to aid its portability to new hardware.
    46 is divided into a number of layers to aid its portability to new hardware.
    47 The diagram below shows how the kernel source is split into four kernel layers: </p>
    47 The diagram below shows how the kernel source is split into four kernel layers: </p>
    53 <li id="GUID-7AB71CB5-5BF6-5F75-9C17-7EB2A9F9E40D"><p>and two peripheral layers:
    53 <li id="GUID-7AB71CB5-5BF6-5F75-9C17-7EB2A9F9E40D"><p>and two peripheral layers:
    54 ASSP and Variant. </p> </li>
    54 ASSP and Variant. </p> </li>
    55 </ul>
    55 </ul>
    56 <fig id="GUID-EBB913A8-1694-5C98-B38B-1387F850CDB4">
    56 <fig id="GUID-EBB913A8-1694-5C98-B38B-1387F850CDB4">
    57 <title>           Kernel source layers          </title>
    57 <title>           Kernel source layers          </title>
    58 <image href="GUID-A480F734-9EDF-5E29-AC96-039B71B22AC3_d0e365474_href.png" placement="inline"/>
    58 <image href="GUID-A480F734-9EDF-5E29-AC96-039B71B22AC3_d0e386707_href.png" placement="inline"/>
    59 </fig>
    59 </fig>
    60 <p>The following is a brief description of each layer and its purpose. </p>
    60 <p>The following is a brief description of each layer and its purpose. </p>
    61 <section id="GUID-5317DC8F-56A2-4AF1-889D-D8E6F4925A0B"><title>Layer 1: Independent </title><p>This layer is about 60% of
    61 <section id="GUID-5317DC8F-56A2-4AF1-889D-D8E6F4925A0B"><title>Layer 1: Independent </title><p>This
    62 the total source code. It provides all the basic building blocks of both the
    62 layer is about 60% of the total source code. It provides all the basic building
    63 nanokernel and the Symbian platform kernel. </p></section>
    63 blocks of both the nanokernel and the Symbian platform kernel. </p></section>
    64 <section id="GUID-4ABDF396-D282-4DDE-975F-7AEBBBE4C0E0"><title>Layer 2: Platform </title><p>This layer is concerned with
    64 <section id="GUID-4ABDF396-D282-4DDE-975F-7AEBBBE4C0E0"><title>Layer 2: Platform </title><p>This
    65 executable images, whether on the emulator or real hardware. Only the memory
    65 layer is concerned with executable images, whether on the emulator or real
    66 model has code in this layer. It defines two platforms: the windows emulator
    66 hardware. Only the memory model has code in this layer. It defines two platforms:
    67 and the real Symbian OS hardware. The windows emulator provides a single-process
    67 the windows emulator and the real Symbian platform hardware. The windows emulator
    68 emulation of Symbian OS using the PC’s Win32 API, for software development:
    68 provides a single-process emulation of Symbian platform using the PC’s Win32
    69 the Symbian OS hardware starts as a program running Win32 DLLs and threads,
    69 API, for software development: the Symbian platform hardware starts as a program
    70 and interfaces with Win32 services rather than hardware and devices. </p><p>Key
    70 running Win32 DLLs and threads, and interfaces with Win32 services rather
    71 differences between the hardware and the emulator are: </p><ul>
    71 than hardware and devices. </p><p>Key differences between the hardware and
       
    72 the emulator are: </p><ul>
    72 <li id="GUID-109C7BE4-93C2-5848-8A4F-61474E240BAC"><p>The emulator runs in
    73 <li id="GUID-109C7BE4-93C2-5848-8A4F-61474E240BAC"><p>The emulator runs in
    73 a single process, and Symbian OS processes are emulated within this. This
    74 a single process, and Symbian platform processes are emulated within this.
    74 means there is no memory protection between emulated Symbian OS processes. </p> </li>
    75 This means there is no memory protection between emulated Symbian platform
       
    76 processes. </p> </li>
    75 <li id="GUID-40B1A70F-1813-50ED-9EA0-9DE4C4067FFB"><p>The emulator file system
    77 <li id="GUID-40B1A70F-1813-50ED-9EA0-9DE4C4067FFB"><p>The emulator file system
    76 maps Z: and C: to subdirectories on the user’s PC, so that programs running
    78 maps Z: and C: to subdirectories on the user’s PC, so that programs running
    77 under the emulator do not interfere with the majority of the PC’s file system. </p> </li>
    79 under the emulator do not interfere with the majority of the PC’s file system. </p> </li>
    78 <li id="GUID-6E52C610-8600-520F-9958-185C3BC97294"><p>Delayed function calls
    80 <li id="GUID-6E52C610-8600-520F-9958-185C3BC97294"><p>Delayed function calls
    79 (DFCs) always run immediately on the emulator. </p> </li>
    81 (DFCs) always run immediately on the emulator. </p> </li>
    80 </ul></section>
    82 </ul></section>
    81 <section id="GUID-AA29E2F8-D6B2-4C14-B983-3CF340BA17BA"><title>Layer 3: Model </title><p>This layer provides supports for
    83 <section id="GUID-AA29E2F8-D6B2-4C14-B983-3CF340BA17BA"><title>Layer 3: Model </title><p>This
    82 the organisation of per process memory. Only the memory model has code at
    84 layer provides supports for the organisation of per process memory. Only the
    83 this level. There are three types of memory model supported: </p><ul>
    85 memory model has code at this level. There are three types of memory model
       
    86 supported: </p><ul>
    84 <li id="GUID-38ACBEB0-C5E9-5F6A-BA8F-F6E0BD4EBA90"><p> <i>Moving</i>: a single
    87 <li id="GUID-38ACBEB0-C5E9-5F6A-BA8F-F6E0BD4EBA90"><p> <i>Moving</i>: a single
    85 page directory is used and page directory entries are moved between the home
    88 page directory is used and page directory entries are moved between the home
    86 and run sections at address space switch time. This is intended for ARMv4
    89 and run sections at address space switch time. This is intended for ARMv4
    87 and ARMv5 CPUs. </p> </li>
    90 and ARMv5 CPUs. </p> </li>
    88 <li id="GUID-18792718-FE86-566F-A82D-7B090AC48007"><p> <i>Multiple</i>: one
    91 <li id="GUID-18792718-FE86-566F-A82D-7B090AC48007"><p> <i>Multiple</i>: one
    89 page directory per process. This is intended for ARMv6 CPUs. </p> </li>
    92 page directory per process. This is intended for ARMv6 CPUs. </p> </li>
    90 <li id="GUID-41AB60A6-4A73-5807-9A1E-A48FAC8EB157"><p> <i>Single</i>: a single
    93 <li id="GUID-41AB60A6-4A73-5807-9A1E-A48FAC8EB157"><p> <i>Single</i>: a single
    91 address space for the whole system. This can be used either for MMU-less CPUs
    94 address space for the whole system. This can be used either for MMU-less CPUs
    92 or to allow incremental porting to a new MMU-aware CPU. </p> </li>
    95 or to allow incremental porting to a new MMU-aware CPU. </p> </li>
    93 </ul></section>
    96 </ul></section>
    94 <section id="GUID-AD70D1A5-E777-4FF3-B247-4F2E94C1D3C7"> <title>Layer 4: CPU</title><p>This layer provides code which differs
    97 <section id="GUID-AD70D1A5-E777-4FF3-B247-4F2E94C1D3C7"> <title>Layer 4: CPU</title><p>This
    95 according to the processor the OS is running on. The nanokernel, memory model
    98 layer provides code which differs according to the processor the OS is running
    96 and Symbian platform kernel all have code in this layer. This is the layer
    99 on. The nanokernel, memory model and Symbian platform kernel all have code
    97 where assembly code belongs. Current possibilities for the CPU layer are X86
   100 in this layer. This is the layer where assembly code belongs. Current possibilities
    98 (real X86 port to PC hardware), ARM (devices) and Win32 (for the emulator). </p><p>The
   101 for the CPU layer are X86 (real X86 port to PC hardware), ARM (devices) and
    99 nanokernel in this layer contains most of the realisation of the core CPU
   102 Win32 (for the emulator). </p><p>The nanokernel in this layer contains most
   100 architecture, such as the exception/interrupt handling, context-switching
   103 of the realisation of the core CPU architecture, such as the exception/interrupt
   101 mechanism, etc. It also contains some functionality which is conceptually
   104 handling, context-switching mechanism, etc. It also contains some functionality
   102 part of the independent layer, but has been assembler coded for improved performance,
   105 which is conceptually part of the independent layer, but has been assembler
   103 for instance, DFC handling and timer handling on ARM-based hardware. </p><p>The
   106 coded for improved performance, for instance, DFC handling and timer handling
   104 bottom layer of the memory model is both CPU-specific as well as specific
   107 on ARM-based hardware. </p><p>The bottom layer of the memory model is both
   105 to the type of memory model. It presents interfaces used by the lower layers
   108 CPU-specific as well as specific to the type of memory model. It presents
   106 (ASSP and variant), and by the memory model and independent layer. </p></section>
   109 interfaces used by the lower layers (ASSP and variant), and by the memory
   107 <section id="GUID-7BA28980-E4B2-4777-AB38-C25DD0B277A3"><title>Layers 5 and 6: ASSP/Variant </title><p>The variant provides
   110 model and independent layer. </p></section>
   108 the hardware specific implementation of the control functions expected by
   111 <section id="GUID-7BA28980-E4B2-4777-AB38-C25DD0B277A3"><title>Layers 5 and
   109 the nanokernel and Symbian platform kernel. </p><p>For some hardware, it may
   112 6: ASSP/Variant </title><p>The variant provides the hardware specific implementation
   110 be appropriate to separate support for a particular ASSP (Application Specific
   113 of the control functions expected by the nanokernel and Symbian platform kernel. </p><p>For
   111 Standard Product), an off-the-shelf integrated CPU part, so that multiple
   114 some hardware, it may be appropriate to separate support for a particular
   112 variants can be produced using the ASSP. </p></section>
   115 ASSP (Application Specific Standard Product), an off-the-shelf integrated
       
   116 CPU part, so that multiple variants can be produced using the ASSP. </p></section>
   113 </conbody></concept>
   117 </conbody></concept>