equal
deleted
inserted
replaced
1 /****************************************************************************** |
1 /****************************************************************************** |
2 * |
2 * |
3 * Copyright (C) 1997-2008 by Dimitri van Heesch. |
3 * Copyright (C) 1997-2010 by Dimitri van Heesch. |
4 * |
4 * |
5 * Permission to use, copy, modify, and distribute this software and its |
5 * Permission to use, copy, modify, and distribute this software and its |
6 * documentation under the terms of the GNU General Public License is hereby |
6 * documentation under the terms of the GNU General Public License is hereby |
7 * granted. No representations are made about the suitability of this software |
7 * granted. No representations are made about the suitability of this software |
8 * for any purpose. It is provided "as is" without express or implied warranty. |
8 * for any purpose. It is provided "as is" without express or implied warranty. |
873 } |
873 } |
874 |
874 |
875 current->name=QCString(qsl[0]); |
875 current->name=QCString(qsl[0]); |
876 if (lastCompound) |
876 if (lastCompound) |
877 { |
877 { |
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878 if (!VhdlDocGen::foundInsertedComponent(current->type,lastCompound)) |
|
879 { |
|
880 BaseInfo *bb=new BaseInfo(current->type,Public,Normal); |
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881 lastCompound->extends->append(bb); |
|
882 } |
878 lastCompound->addSubEntry(current); |
883 lastCompound->addSubEntry(current); |
879 current = new Entry; |
884 current = new Entry; |
880 initEntry(current); |
885 initEntry(current); |
881 } |
886 } |
882 else |
887 else |
966 else if (current->spec==VhdlDocGen::ARCHITECTURE) |
971 else if (current->spec==VhdlDocGen::ARCHITECTURE) |
967 { |
972 { |
968 //current->name+=qcs.lower(); |
973 //current->name+=qcs.lower(); |
969 current->name.prepend(qcs+"::"); |
974 current->name.prepend(qcs+"::"); |
970 |
975 |
971 if (lastEntity) |
976 //if (lastEntity) |
972 { |
977 //{ |
973 // inherit private inheritance relation between entity and architecture |
978 // inherit private inheritance relation between entity and architecture |
974 if (!VhdlDocGen::foundInsertedComponent(current->name,lastEntity)) |
979 //if (!VhdlDocGen::foundInsertedComponent(current->name,lastEntity)) |
975 { |
980 //{ |
976 BaseInfo *bb=new BaseInfo(current->name,Private,Normal); |
981 // BaseInfo *bb=new BaseInfo(current->name,Private,Normal); |
977 lastEntity->extends->append(bb); |
982 // lastEntity->extends->append(bb); |
978 } |
983 //} |
979 } |
984 //} |
980 |
985 |
981 } |
986 } |
982 else if (current->spec==VhdlDocGen::PACKAGE_BODY) |
987 else if (current->spec==VhdlDocGen::PACKAGE_BODY) |
983 { |
988 { |
984 current->name+=qcs; |
989 current->name+=qcs; |
2008 const char *exampleName, |
2013 const char *exampleName, |
2009 FileDef *fileDef, |
2014 FileDef *fileDef, |
2010 int startLine, |
2015 int startLine, |
2011 int endLine, |
2016 int endLine, |
2012 bool inlineFragment, |
2017 bool inlineFragment, |
2013 MemberDef *memberDef |
2018 MemberDef *memberDef, |
|
2019 bool showLineNumbers |
2014 ) |
2020 ) |
2015 { |
2021 { |
2016 ::parseVhdlCode(codeOutIntf,scopeName,input,isExampleBlock,exampleName,fileDef,startLine,endLine,inlineFragment,memberDef); |
2022 ::parseVhdlCode(codeOutIntf,scopeName,input,isExampleBlock,exampleName, |
2017 } |
2023 fileDef,startLine,endLine,inlineFragment,memberDef, |
2018 |
2024 showLineNumbers); |
|
2025 } |
|
2026 |