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   128 .\" ========================================================================

   129 .\"

   130 .IX Title "AS 1"

   131 .TH AS 1 "2008-01-09" "binutils-2.18.50" "GNU Development Tools"

   132 .SH "NAME"

   133 AS \- the portable GNU assembler.

   134 .SH "SYNOPSIS"

   135 .IX Header "SYNOPSIS"

   136 as [\fB\-a\fR[\fBcdhlns\fR][=\fIfile\fR]] [\fB\-\-alternate\fR] [\fB\-D\fR]

   137  [\fB\-\-debug\-prefix\-map\fR \fIold\fR=\fInew\fR]

   138  [\fB\-\-defsym\fR \fIsym\fR=\fIval\fR] [\fB\-f\fR] [\fB\-g\fR] [\fB\-\-gstabs\fR]

   139  [\fB\-\-gstabs+\fR] [\fB\-\-gdwarf\-2\fR] [\fB\-\-help\fR] [\fB\-I\fR \fIdir\fR] [\fB\-J\fR]

   140  [\fB\-K\fR] [\fB\-L\fR] [\fB\-\-listing\-lhs\-width\fR=\fI\s-1NUM\s0\fR]

   141  [\fB\-\-listing\-lhs\-width2\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-rhs\-width\fR=\fI\s-1NUM\s0\fR]

   142  [\fB\-\-listing\-cont\-lines\fR=\fI\s-1NUM\s0\fR] [\fB\-\-keep\-locals\fR] [\fB\-o\fR

   143  \fIobjfile\fR] [\fB\-R\fR] [\fB\-\-reduce\-memory\-overheads\fR] [\fB\-\-statistics\fR]

   144  [\fB\-v\fR] [\fB\-version\fR] [\fB\-\-version\fR] [\fB\-W\fR] [\fB\-\-warn\fR]

   145  [\fB\-\-fatal\-warnings\fR] [\fB\-w\fR] [\fB\-x\fR] [\fB\-Z\fR] [\fB@\fR\fI\s-1FILE\s0\fR]

   146  [\fB\-\-target\-help\fR] [\fItarget-options\fR]

   147  [\fB\-\-\fR|\fIfiles\fR ...]

   148 .PP

   149 \&\fITarget Alpha options:\fR

   150    [\fB\-m\fR\fIcpu\fR]

   151    [\fB\-mdebug\fR | \fB\-no\-mdebug\fR]

   152    [\fB\-relax\fR] [\fB\-g\fR] [\fB\-G\fR\fIsize\fR]

   153    [\fB\-F\fR] [\fB\-32addr\fR]

   154 .PP

   155 \&\fITarget \s-1ARC\s0 options:\fR

   156    [\fB\-marc[5|6|7|8]\fR]

   157    [\fB\-EB\fR|\fB\-EL\fR]

   158 .PP

   159 \&\fITarget \s-1ARM\s0 options:\fR

   160    [\fB\-mcpu\fR=\fIprocessor\fR[+\fIextension\fR...]]

   161    [\fB\-march\fR=\fIarchitecture\fR[+\fIextension\fR...]]

   162    [\fB\-mfpu\fR=\fIfloating-point-format\fR]

   163    [\fB\-mfloat\-abi\fR=\fIabi\fR]

   164    [\fB\-meabi\fR=\fIver\fR]

   165    [\fB\-mthumb\fR]

   166    [\fB\-EB\fR|\fB\-EL\fR]

   167    [\fB\-mapcs\-32\fR|\fB\-mapcs\-26\fR|\fB\-mapcs\-float\fR|

   168     \fB\-mapcs\-reentrant\fR]

   169    [\fB\-mthumb\-interwork\fR] [\fB\-k\fR]

   170 .PP

   171 \&\fITarget \s-1CRIS\s0 options:\fR

   172    [\fB\-\-underscore\fR | \fB\-\-no\-underscore\fR]

   173    [\fB\-\-pic\fR] [\fB\-N\fR]

   174    [\fB\-\-emulation=criself\fR | \fB\-\-emulation=crisaout\fR]

   175    [\fB\-\-march=v0_v10\fR | \fB\-\-march=v10\fR | \fB\-\-march=v32\fR | \fB\-\-march=common_v10_v32\fR]

   176 .PP

   177 \&\fITarget D10V options:\fR

   178    [\fB\-O\fR]

   179 .PP

   180 \&\fITarget D30V options:\fR

   181    [\fB\-O\fR|\fB\-n\fR|\fB\-N\fR]

   182 .PP

   183 \&\fITarget i386 options:\fR

   184    [\fB\-\-32\fR|\fB\-\-64\fR] [\fB\-n\fR]

   185    [\fB\-march\fR=\fI\s-1CPU\s0\fR] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR] 

   186 .PP

   187 \&\fITarget i960 options:\fR

   188    [\fB\-ACA\fR|\fB\-ACA_A\fR|\fB\-ACB\fR|\fB\-ACC\fR|\fB\-AKA\fR|\fB\-AKB\fR|

   189     \fB\-AKC\fR|\fB\-AMC\fR]

   190    [\fB\-b\fR] [\fB\-no\-relax\fR]

   191 .PP

   192 \&\fITarget \s-1IA\-64\s0 options:\fR

   193    [\fB\-mconstant\-gp\fR|\fB\-mauto\-pic\fR]

   194    [\fB\-milp32\fR|\fB\-milp64\fR|\fB\-mlp64\fR|\fB\-mp64\fR]

   195    [\fB\-mle\fR|\fBmbe\fR]

   196    [\fB\-mtune=itanium1\fR|\fB\-mtune=itanium2\fR]

   197    [\fB\-munwind\-check=warning\fR|\fB\-munwind\-check=error\fR]

   198    [\fB\-mhint.b=ok\fR|\fB\-mhint.b=warning\fR|\fB\-mhint.b=error\fR]

   199    [\fB\-x\fR|\fB\-xexplicit\fR] [\fB\-xauto\fR] [\fB\-xdebug\fR]

   200 .PP

   201 \&\fITarget \s-1IP2K\s0 options:\fR

   202    [\fB\-mip2022\fR|\fB\-mip2022ext\fR]

   203 .PP

   204 \&\fITarget M32C options:\fR

   205    [\fB\-m32c\fR|\fB\-m16c\fR]

   206 .PP

   207 \&\fITarget M32R options:\fR

   208    [\fB\-\-m32rx\fR|\fB\-\-[no\-]warn\-explicit\-parallel\-conflicts\fR|

   209    \fB\-\-W[n]p\fR]

   210 .PP

   211 \&\fITarget M680X0 options:\fR

   212    [\fB\-l\fR] [\fB\-m68000\fR|\fB\-m68010\fR|\fB\-m68020\fR|...]

   213 .PP

   214 \&\fITarget M68HC11 options:\fR

   215    [\fB\-m68hc11\fR|\fB\-m68hc12\fR|\fB\-m68hcs12\fR]

   216    [\fB\-mshort\fR|\fB\-mlong\fR]

   217    [\fB\-mshort\-double\fR|\fB\-mlong\-double\fR]

   218    [\fB\-\-force\-long\-branches\fR] [\fB\-\-short\-branches\fR]

   219    [\fB\-\-strict\-direct\-mode\fR] [\fB\-\-print\-insn\-syntax\fR]

   220    [\fB\-\-print\-opcodes\fR] [\fB\-\-generate\-example\fR]

   221 .PP

   222 \&\fITarget \s-1MCORE\s0 options:\fR

   223    [\fB\-jsri2bsr\fR] [\fB\-sifilter\fR] [\fB\-relax\fR]

   224    [\fB\-mcpu=[210|340]\fR]

   225 .PP

   226 \&\fITarget \s-1MIPS\s0 options:\fR

   227    [\fB\-nocpp\fR] [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-O\fR[\fIoptimization level\fR]]

   228    [\fB\-g\fR[\fIdebug level\fR]] [\fB\-G\fR \fInum\fR] [\fB\-KPIC\fR] [\fB\-call_shared\fR]

   229    [\fB\-non_shared\fR] [\fB\-xgot\fR [\fB\-mvxworks\-pic\fR]

   230    [\fB\-mabi\fR=\fI\s-1ABI\s0\fR] [\fB\-32\fR] [\fB\-n32\fR] [\fB\-64\fR] [\fB\-mfp32\fR] [\fB\-mgp32\fR]

   231    [\fB\-march\fR=\fI\s-1CPU\s0\fR] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR] [\fB\-mips1\fR] [\fB\-mips2\fR]

   232    [\fB\-mips3\fR] [\fB\-mips4\fR] [\fB\-mips5\fR] [\fB\-mips32\fR] [\fB\-mips32r2\fR]

   233    [\fB\-mips64\fR] [\fB\-mips64r2\fR]

   234    [\fB\-construct\-floats\fR] [\fB\-no\-construct\-floats\fR]

   235    [\fB\-trap\fR] [\fB\-no\-break\fR] [\fB\-break\fR] [\fB\-no\-trap\fR]

   236    [\fB\-mfix7000\fR] [\fB\-mno\-fix7000\fR]

   237    [\fB\-mips16\fR] [\fB\-no\-mips16\fR]

   238    [\fB\-msmartmips\fR] [\fB\-mno\-smartmips\fR]

   239    [\fB\-mips3d\fR] [\fB\-no\-mips3d\fR]

   240    [\fB\-mdmx\fR] [\fB\-no\-mdmx\fR]

   241    [\fB\-mdsp\fR] [\fB\-mno\-dsp\fR]

   242    [\fB\-mdspr2\fR] [\fB\-mno\-dspr2\fR]

   243    [\fB\-mmt\fR] [\fB\-mno\-mt\fR]

   244    [\fB\-mdebug\fR] [\fB\-no\-mdebug\fR]

   245    [\fB\-mpdr\fR] [\fB\-mno\-pdr\fR]

   246 .PP

   247 \&\fITarget \s-1MMIX\s0 options:\fR

   248    [\fB\-\-fixed\-special\-register\-names\fR] [\fB\-\-globalize\-symbols\fR]

   249    [\fB\-\-gnu\-syntax\fR] [\fB\-\-relax\fR] [\fB\-\-no\-predefined\-symbols\fR]

   250    [\fB\-\-no\-expand\fR] [\fB\-\-no\-merge\-gregs\fR] [\fB\-x\fR]

   251    [\fB\-\-linker\-allocated\-gregs\fR]

   252 .PP

   253 \&\fITarget \s-1PDP11\s0 options:\fR

   254    [\fB\-mpic\fR|\fB\-mno\-pic\fR] [\fB\-mall\fR] [\fB\-mno\-extensions\fR]

   255    [\fB\-m\fR\fIextension\fR|\fB\-mno\-\fR\fIextension\fR]

   256    [\fB\-m\fR\fIcpu\fR] [\fB\-m\fR\fImachine\fR]  

   257 .PP

   258 \&\fITarget picoJava options:\fR

   259    [\fB\-mb\fR|\fB\-me\fR]

   260 .PP

   261 \&\fITarget PowerPC options:\fR

   262    [\fB\-mpwrx\fR|\fB\-mpwr2\fR|\fB\-mpwr\fR|\fB\-m601\fR|\fB\-mppc\fR|\fB\-mppc32\fR|\fB\-m603\fR|\fB\-m604\fR|

   263     \fB\-m403\fR|\fB\-m405\fR|\fB\-mppc64\fR|\fB\-m620\fR|\fB\-mppc64bridge\fR|\fB\-mbooke\fR|

   264     \fB\-mbooke32\fR|\fB\-mbooke64\fR]

   265    [\fB\-mcom\fR|\fB\-many\fR|\fB\-maltivec\fR] [\fB\-memb\fR]

   266    [\fB\-mregnames\fR|\fB\-mno\-regnames\fR]

   267    [\fB\-mrelocatable\fR|\fB\-mrelocatable\-lib\fR]

   268    [\fB\-mlittle\fR|\fB\-mlittle\-endian\fR|\fB\-mbig\fR|\fB\-mbig\-endian\fR]

   269    [\fB\-msolaris\fR|\fB\-mno\-solaris\fR]

   270 .PP

   271 \&\fITarget \s-1SPARC\s0 options:\fR

   272    [\fB\-Av6\fR|\fB\-Av7\fR|\fB\-Av8\fR|\fB\-Asparclet\fR|\fB\-Asparclite\fR

   273     \fB\-Av8plus\fR|\fB\-Av8plusa\fR|\fB\-Av9\fR|\fB\-Av9a\fR]

   274    [\fB\-xarch=v8plus\fR|\fB\-xarch=v8plusa\fR] [\fB\-bump\fR]

   275    [\fB\-32\fR|\fB\-64\fR]

   276 .PP

   277 \&\fITarget \s-1TIC54X\s0 options:\fR

   278  [\fB\-mcpu=54[123589]\fR|\fB\-mcpu=54[56]lp\fR] [\fB\-mfar\-mode\fR|\fB\-mf\fR] 

   279  [\fB\-merrors\-to\-file\fR \fI<filename>\fR|\fB\-me\fR \fI<filename>\fR]

   280 .PP

   281 \&\fITarget Z80 options:\fR

   282   [\fB\-z80\fR] [\fB\-r800\fR]

   283   [ \fB\-ignore\-undocumented\-instructions\fR] [\fB\-Wnud\fR]

   284   [ \fB\-ignore\-unportable\-instructions\fR] [\fB\-Wnup\fR]

   285   [ \fB\-warn\-undocumented\-instructions\fR] [\fB\-Wud\fR]

   286   [ \fB\-warn\-unportable\-instructions\fR] [\fB\-Wup\fR]

   287   [ \fB\-forbid\-undocumented\-instructions\fR] [\fB\-Fud\fR]

   288   [ \fB\-forbid\-unportable\-instructions\fR] [\fB\-Fup\fR]

   289 .PP

   290 \&\fITarget Xtensa options:\fR

   291  [\fB\-\-[no\-]text\-section\-literals\fR] [\fB\-\-[no\-]absolute\-literals\fR]

   292  [\fB\-\-[no\-]target\-align\fR] [\fB\-\-[no\-]longcalls\fR]

   293  [\fB\-\-[no\-]transform\fR]

   294  [\fB\-\-rename\-section\fR \fIoldname\fR=\fInewname\fR]

   295 .SH "DESCRIPTION"

   296 .IX Header "DESCRIPTION"

   297 \&\s-1GNU\s0 \fBas\fR is really a family of assemblers.

   298 If you use (or have used) the \s-1GNU\s0 assembler on one architecture, you

   299 should find a fairly similar environment when you use it on another

   300 architecture.  Each version has much in common with the others,

   301 including object file formats, most assembler directives (often called

   302 \&\fIpseudo-ops\fR) and assembler syntax.

   303 .PP

   304 \&\fBas\fR is primarily intended to assemble the output of the

   305 \&\s-1GNU\s0 C compiler \f(CW\*(C`gcc\*(C'\fR for use by the linker

   306 \&\f(CW\*(C`ld\*(C'\fR.  Nevertheless, we've tried to make \fBas\fR

   307 assemble correctly everything that other assemblers for the same

   308 machine would assemble.

   309 Any exceptions are documented explicitly.

   310 This doesn't mean \fBas\fR always uses the same syntax as another

   311 assembler for the same architecture; for example, we know of several

   312 incompatible versions of 680x0 assembly language syntax.

   313 .PP

   314 Each time you run \fBas\fR it assembles exactly one source

   315 program.  The source program is made up of one or more files.

   316 (The standard input is also a file.)

   317 .PP

   318 You give \fBas\fR a command line that has zero or more input file

   319 names.  The input files are read (from left file name to right).  A

   320 command line argument (in any position) that has no special meaning

   321 is taken to be an input file name.

   322 .PP

   323 If you give \fBas\fR no file names it attempts to read one input file

   324 from the \fBas\fR standard input, which is normally your terminal.  You

   325 may have to type \fBctl-D\fR to tell \fBas\fR there is no more program

   326 to assemble.

   327 .PP

   328 Use \fB\-\-\fR if you need to explicitly name the standard input file

   329 in your command line.

   330 .PP

   331 If the source is empty, \fBas\fR produces a small, empty object

   332 file.

   333 .PP

   334 \&\fBas\fR may write warnings and error messages to the standard error

   335 file (usually your terminal).  This should not happen when  a compiler

   336 runs \fBas\fR automatically.  Warnings report an assumption made so

   337 that \fBas\fR could keep assembling a flawed program; errors report a

   338 grave problem that stops the assembly.

   339 .PP

   340 If you are invoking \fBas\fR via the \s-1GNU\s0 C compiler,

   341 you can use the \fB\-Wa\fR option to pass arguments through to the assembler.

   342 The assembler arguments must be separated from each other (and the \fB\-Wa\fR)

   343 by commas.  For example:

   344 .PP

   345 .Vb 1

   346 \&        gcc -c -g -O -Wa,-alh,-L file.c

   347 .Ve

   348 .PP

   349 This passes two options to the assembler: \fB\-alh\fR (emit a listing to

   350 standard output with high-level and assembly source) and \fB\-L\fR (retain

   351 local symbols in the symbol table).

   352 .PP

   353 Usually you do not need to use this \fB\-Wa\fR mechanism, since many compiler

   354 command-line options are automatically passed to the assembler by the compiler.

   355 (You can call the \s-1GNU\s0 compiler driver with the \fB\-v\fR option to see

   356 precisely what options it passes to each compilation pass, including the

   357 assembler.)

   358 .SH "OPTIONS"

   359 .IX Header "OPTIONS"

   360 .IP "\fB@\fR\fIfile\fR" 4

   361 .IX Item "@file"

   362 Read command-line options from \fIfile\fR.  The options read are

   363 inserted in place of the original @\fIfile\fR option.  If \fIfile\fR

   364 does not exist, or cannot be read, then the option will be treated

   365 literally, and not removed.  

   366 .Sp

   367 Options in \fIfile\fR are separated by whitespace.  A whitespace

   368 character may be included in an option by surrounding the entire

   369 option in either single or double quotes.  Any character (including a

   370 backslash) may be included by prefixing the character to be included

   371 with a backslash.  The \fIfile\fR may itself contain additional

   372 @\fIfile\fR options; any such options will be processed recursively.

   373 .IP "\fB\-a[cdhlmns]\fR" 4

   374 .IX Item "-a[cdhlmns]"

   375 Turn on listings, in any of a variety of ways:

   376 .RS 4

   377 .IP "\fB\-ac\fR" 4

   378 .IX Item "-ac"

   379 omit false conditionals

   380 .IP "\fB\-ad\fR" 4

   381 .IX Item "-ad"

   382 omit debugging directives

   383 .IP "\fB\-ah\fR" 4

   384 .IX Item "-ah"

   385 include high-level source

   386 .IP "\fB\-al\fR" 4

   387 .IX Item "-al"

   388 include assembly

   389 .IP "\fB\-am\fR" 4

   390 .IX Item "-am"

   391 include macro expansions

   392 .IP "\fB\-an\fR" 4

   393 .IX Item "-an"

   394 omit forms processing

   395 .IP "\fB\-as\fR" 4

   396 .IX Item "-as"

   397 include symbols

   398 .IP "\fB=file\fR" 4

   399 .IX Item "=file"

   400 set the name of the listing file

   401 .RE

   402 .RS 4

   403 .Sp

   404 You may combine these options; for example, use \fB\-aln\fR for assembly

   405 listing without forms processing.  The \fB=file\fR option, if used, must be

   406 the last one.  By itself, \fB\-a\fR defaults to \fB\-ahls\fR.

   407 .RE

   408 .IP "\fB\-\-alternate\fR" 4

   409 .IX Item "--alternate"

   410 Begin in alternate macro mode.

   411 .IP "\fB\-D\fR" 4

   412 .IX Item "-D"

   413 Ignored.  This option is accepted for script compatibility with calls to

   414 other assemblers.

   415 .IP "\fB\-\-debug\-prefix\-map\fR \fIold\fR\fB=\fR\fInew\fR" 4

   416 .IX Item "--debug-prefix-map old=new"

   417 When assembling files in directory \fI\fIold\fI\fR, record debugging

   418 information describing them as in \fI\fInew\fI\fR instead.

   419 .IP "\fB\-\-defsym\fR \fIsym\fR\fB=\fR\fIvalue\fR" 4

   420 .IX Item "--defsym sym=value"

   421 Define the symbol \fIsym\fR to be \fIvalue\fR before assembling the input file.

   422 \&\fIvalue\fR must be an integer constant.  As in C, a leading \fB0x\fR

   423 indicates a hexadecimal value, and a leading \fB0\fR indicates an octal

   424 value.  The value of the symbol can be overridden inside a source file via the

   425 use of a \f(CW\*(C`.set\*(C'\fR pseudo\-op.

   426 .IP "\fB\-f\fR" 4

   427 .IX Item "-f"

   428 \&\*(L"fast\*(R"\-\-\-skip whitespace and comment preprocessing (assume source is

   429 compiler output).

   430 .IP "\fB\-g\fR" 4

   431 .IX Item "-g"

   432 .PD 0

   433 .IP "\fB\-\-gen\-debug\fR" 4

   434 .IX Item "--gen-debug"

   435 .PD

   436 Generate debugging information for each assembler source line using whichever

   437 debug format is preferred by the target.  This currently means either \s-1STABS\s0,

   438 \&\s-1ECOFF\s0 or \s-1DWARF2\s0.

   439 .IP "\fB\-\-gstabs\fR" 4

   440 .IX Item "--gstabs"

   441 Generate stabs debugging information for each assembler line.  This

   442 may help debugging assembler code, if the debugger can handle it.

   443 .IP "\fB\-\-gstabs+\fR" 4

   444 .IX Item "--gstabs+"

   445 Generate stabs debugging information for each assembler line, with \s-1GNU\s0

   446 extensions that probably only gdb can handle, and that could make other

   447 debuggers crash or refuse to read your program.  This

   448 may help debugging assembler code.  Currently the only \s-1GNU\s0 extension is

   449 the location of the current working directory at assembling time.

   450 .IP "\fB\-\-gdwarf\-2\fR" 4

   451 .IX Item "--gdwarf-2"

   452 Generate \s-1DWARF2\s0 debugging information for each assembler line.  This

   453 may help debugging assembler code, if the debugger can handle it.  Note\-\-\-this

   454 option is only supported by some targets, not all of them.

   455 .IP "\fB\-\-help\fR" 4

   456 .IX Item "--help"

   457 Print a summary of the command line options and exit.

   458 .IP "\fB\-\-target\-help\fR" 4

   459 .IX Item "--target-help"

   460 Print a summary of all target specific options and exit.

   461 .IP "\fB\-I\fR \fIdir\fR" 4

   462 .IX Item "-I dir"

   463 Add directory \fIdir\fR to the search list for \f(CW\*(C`.include\*(C'\fR directives.

   464 .IP "\fB\-J\fR" 4

   465 .IX Item "-J"

   466 Don't warn about signed overflow.

   467 .IP "\fB\-K\fR" 4

   468 .IX Item "-K"

   469 Issue warnings when difference tables altered for long displacements.

   470 .IP "\fB\-L\fR" 4

   471 .IX Item "-L"

   472 .PD 0

   473 .IP "\fB\-\-keep\-locals\fR" 4

   474 .IX Item "--keep-locals"

   475 .PD

   476 Keep (in the symbol table) local symbols.  These symbols start with

   477 system-specific local label prefixes, typically \fB.L\fR for \s-1ELF\s0 systems

   478 or \fBL\fR for traditional a.out systems.

   479 .IP "\fB\-\-listing\-lhs\-width=\fR\fInumber\fR" 4

   480 .IX Item "--listing-lhs-width=number"

   481 Set the maximum width, in words, of the output data column for an assembler

   482 listing to \fInumber\fR.

   483 .IP "\fB\-\-listing\-lhs\-width2=\fR\fInumber\fR" 4

   484 .IX Item "--listing-lhs-width2=number"

   485 Set the maximum width, in words, of the output data column for continuation

   486 lines in an assembler listing to \fInumber\fR.

   487 .IP "\fB\-\-listing\-rhs\-width=\fR\fInumber\fR" 4

   488 .IX Item "--listing-rhs-width=number"

   489 Set the maximum width of an input source line, as displayed in a listing, to

   490 \&\fInumber\fR bytes.

   491 .IP "\fB\-\-listing\-cont\-lines=\fR\fInumber\fR" 4

   492 .IX Item "--listing-cont-lines=number"

   493 Set the maximum number of lines printed in a listing for a single line of input

   494 to \fInumber\fR + 1.

   495 .IP "\fB\-o\fR \fIobjfile\fR" 4

   496 .IX Item "-o objfile"

   497 Name the object-file output from \fBas\fR \fIobjfile\fR.

   498 .IP "\fB\-R\fR" 4

   499 .IX Item "-R"

   500 Fold the data section into the text section.

   501 .Sp

   502 Set the default size of \s-1GAS\s0's hash tables to a prime number close to

   503 \&\fInumber\fR.  Increasing this value can reduce the length of time it takes the

   504 assembler to perform its tasks, at the expense of increasing the assembler's

   505 memory requirements.  Similarly reducing this value can reduce the memory

   506 requirements at the expense of speed.

   507 .IP "\fB\-\-reduce\-memory\-overheads\fR" 4

   508 .IX Item "--reduce-memory-overheads"

   509 This option reduces \s-1GAS\s0's memory requirements, at the expense of making the

   510 assembly processes slower.  Currently this switch is a synonym for

   511 \&\fB\-\-hash\-size=4051\fR, but in the future it may have other effects as well.

   512 .IP "\fB\-\-statistics\fR" 4

   513 .IX Item "--statistics"

   514 Print the maximum space (in bytes) and total time (in seconds) used by

   515 assembly.

   516 .IP "\fB\-\-strip\-local\-absolute\fR" 4

   517 .IX Item "--strip-local-absolute"

   518 Remove local absolute symbols from the outgoing symbol table.

   519 .IP "\fB\-v\fR" 4

   520 .IX Item "-v"

   521 .PD 0

   522 .IP "\fB\-version\fR" 4

   523 .IX Item "-version"

   524 .PD

   525 Print the \fBas\fR version.

   526 .IP "\fB\-\-version\fR" 4

   527 .IX Item "--version"

   528 Print the \fBas\fR version and exit.

   529 .IP "\fB\-W\fR" 4

   530 .IX Item "-W"

   531 .PD 0

   532 .IP "\fB\-\-no\-warn\fR" 4

   533 .IX Item "--no-warn"

   534 .PD

   535 Suppress warning messages.

   536 .IP "\fB\-\-fatal\-warnings\fR" 4

   537 .IX Item "--fatal-warnings"

   538 Treat warnings as errors.

   539 .IP "\fB\-\-warn\fR" 4

   540 .IX Item "--warn"

   541 Don't suppress warning messages or treat them as errors.

   542 .IP "\fB\-w\fR" 4

   543 .IX Item "-w"

   544 Ignored.

   545 .IP "\fB\-x\fR" 4

   546 .IX Item "-x"

   547 Ignored.

   548 .IP "\fB\-Z\fR" 4

   549 .IX Item "-Z"

   550 Generate an object file even after errors.

   551 .IP "\fB\-\- |\fR \fIfiles\fR \fB...\fR" 4

   552 .IX Item "-- | files ..."

   553 Standard input, or source files to assemble.

   554 .PP

   555 The following options are available when as is configured for

   556 an \s-1ARC\s0 processor.

   557 .IP "\fB\-marc[5|6|7|8]\fR" 4

   558 .IX Item "-marc[5|6|7|8]"

   559 This option selects the core processor variant.

   560 .IP "\fB\-EB | \-EL\fR" 4

   561 .IX Item "-EB | -EL"

   562 Select either big-endian (\-EB) or little-endian (\-EL) output.

   563 .PP

   564 The following options are available when as is configured for the \s-1ARM\s0

   565 processor family.

   566 .IP "\fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4

   567 .IX Item "-mcpu=processor[+extension...]"

   568 Specify which \s-1ARM\s0 processor variant is the target.

   569 .IP "\fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4

   570 .IX Item "-march=architecture[+extension...]"

   571 Specify which \s-1ARM\s0 architecture variant is used by the target.

   572 .IP "\fB\-mfpu=\fR\fIfloating-point-format\fR" 4

   573 .IX Item "-mfpu=floating-point-format"

   574 Select which Floating Point architecture is the target.

   575 .IP "\fB\-mfloat\-abi=\fR\fIabi\fR" 4

   576 .IX Item "-mfloat-abi=abi"

   577 Select which floating point \s-1ABI\s0 is in use.

   578 .IP "\fB\-mthumb\fR" 4

   579 .IX Item "-mthumb"

   580 Enable Thumb only instruction decoding.

   581 .IP "\fB\-mapcs\-32 | \-mapcs\-26 | \-mapcs\-float | \-mapcs\-reentrant\fR" 4

   582 .IX Item "-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant"

   583 Select which procedure calling convention is in use.

   584 .IP "\fB\-EB | \-EL\fR" 4

   585 .IX Item "-EB | -EL"

   586 Select either big-endian (\-EB) or little-endian (\-EL) output.

   587 .IP "\fB\-mthumb\-interwork\fR" 4

   588 .IX Item "-mthumb-interwork"

   589 Specify that the code has been generated with interworking between Thumb and

   590 \&\s-1ARM\s0 code in mind.

   591 .IP "\fB\-k\fR" 4

   592 .IX Item "-k"

   593 Specify that \s-1PIC\s0 code has been generated.

   594 .PP

   595 See the info pages for documentation of the CRIS-specific options.

   596 .PP

   597 The following options are available when as is configured for

   598 a D10V processor.

   599 .IP "\fB\-O\fR" 4

   600 .IX Item "-O"

   601 Optimize output by parallelizing instructions.

   602 .PP

   603 The following options are available when as is configured for a D30V

   604 processor.

   605 .IP "\fB\-O\fR" 4

   606 .IX Item "-O"

   607 Optimize output by parallelizing instructions.

   608 .IP "\fB\-n\fR" 4

   609 .IX Item "-n"

   610 Warn when nops are generated.

   611 .IP "\fB\-N\fR" 4

   612 .IX Item "-N"

   613 Warn when a nop after a 32\-bit multiply instruction is generated.

   614 .PP

   615 The following options are available when as is configured for the

   616 Intel 80960 processor.

   617 .IP "\fB\-ACA | \-ACA_A | \-ACB | \-ACC | \-AKA | \-AKB | \-AKC | \-AMC\fR" 4

   618 .IX Item "-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC"

   619 Specify which variant of the 960 architecture is the target.

   620 .IP "\fB\-b\fR" 4

   621 .IX Item "-b"

   622 Add code to collect statistics about branches taken.

   623 .IP "\fB\-no\-relax\fR" 4

   624 .IX Item "-no-relax"

   625 Do not alter compare-and-branch instructions for long displacements;

   626 error if necessary.

   627 .PP

   628 The following options are available when as is configured for the

   629 Ubicom \s-1IP2K\s0 series.

   630 .IP "\fB\-mip2022ext\fR" 4

   631 .IX Item "-mip2022ext"

   632 Specifies that the extended \s-1IP2022\s0 instructions are allowed.

   633 .IP "\fB\-mip2022\fR" 4

   634 .IX Item "-mip2022"

   635 Restores the default behaviour, which restricts the permitted instructions to

   636 just the basic \s-1IP2022\s0 ones.

   637 .PP

   638 The following options are available when as is configured for the

   639 Renesas M32C and M16C processors.

   640 .IP "\fB\-m32c\fR" 4

   641 .IX Item "-m32c"

   642 Assemble M32C instructions.

   643 .IP "\fB\-m16c\fR" 4

   644 .IX Item "-m16c"

   645 Assemble M16C instructions (the default).

   646 .PP

   647 The following options are available when as is configured for the

   648 Renesas M32R (formerly Mitsubishi M32R) series.

   649 .IP "\fB\-\-m32rx\fR" 4

   650 .IX Item "--m32rx"

   651 Specify which processor in the M32R family is the target.  The default

   652 is normally the M32R, but this option changes it to the M32RX.

   653 .IP "\fB\-\-warn\-explicit\-parallel\-conflicts or \-\-Wp\fR" 4

   654 .IX Item "--warn-explicit-parallel-conflicts or --Wp"

   655 Produce warning messages when questionable parallel constructs are

   656 encountered. 

   657 .IP "\fB\-\-no\-warn\-explicit\-parallel\-conflicts or \-\-Wnp\fR" 4

   658 .IX Item "--no-warn-explicit-parallel-conflicts or --Wnp"

   659 Do not produce warning messages when questionable parallel constructs are 

   660 encountered. 

   661 .PP

   662 The following options are available when as is configured for the

   663 Motorola 68000 series.

   664 .IP "\fB\-l\fR" 4

   665 .IX Item "-l"

   666 Shorten references to undefined symbols, to one word instead of two.

   667 .IP "\fB\-m68000 | \-m68008 | \-m68010 | \-m68020 | \-m68030\fR" 4

   668 .IX Item "-m68000 | -m68008 | -m68010 | -m68020 | -m68030"

   669 .PD 0

   670 .IP "\fB| \-m68040 | \-m68060 | \-m68302 | \-m68331 | \-m68332\fR" 4

   671 .IX Item "| -m68040 | -m68060 | -m68302 | -m68331 | -m68332"

   672 .IP "\fB| \-m68333 | \-m68340 | \-mcpu32 | \-m5200\fR" 4

   673 .IX Item "| -m68333 | -m68340 | -mcpu32 | -m5200"

   674 .PD

   675 Specify what processor in the 68000 family is the target.  The default

   676 is normally the 68020, but this can be changed at configuration time.

   677 .IP "\fB\-m68881 | \-m68882 | \-mno\-68881 | \-mno\-68882\fR" 4

   678 .IX Item "-m68881 | -m68882 | -mno-68881 | -mno-68882"

   679 The target machine does (or does not) have a floating-point coprocessor.

   680 The default is to assume a coprocessor for 68020, 68030, and cpu32.  Although

   681 the basic 68000 is not compatible with the 68881, a combination of the

   682 two can be specified, since it's possible to do emulation of the

   683 coprocessor instructions with the main processor.

   684 .IP "\fB\-m68851 | \-mno\-68851\fR" 4

   685 .IX Item "-m68851 | -mno-68851"

   686 The target machine does (or does not) have a memory-management

   687 unit coprocessor.  The default is to assume an \s-1MMU\s0 for 68020 and up.

   688 .PP

   689 For details about the \s-1PDP\-11\s0 machine dependent features options,

   690 see \fBPDP\-11\-Options\fR.

   691 .IP "\fB\-mpic | \-mno\-pic\fR" 4

   692 .IX Item "-mpic | -mno-pic"

   693 Generate position-independent (or position\-dependent) code.  The

   694 default is \fB\-mpic\fR.

   695 .IP "\fB\-mall\fR" 4

   696 .IX Item "-mall"

   697 .PD 0

   698 .IP "\fB\-mall\-extensions\fR" 4

   699 .IX Item "-mall-extensions"

   700 .PD

   701 Enable all instruction set extensions.  This is the default.

   702 .IP "\fB\-mno\-extensions\fR" 4

   703 .IX Item "-mno-extensions"

   704 Disable all instruction set extensions.

   705 .IP "\fB\-m\fR\fIextension\fR \fB| \-mno\-\fR\fIextension\fR" 4

   706 .IX Item "-mextension | -mno-extension"

   707 Enable (or disable) a particular instruction set extension.

   708 .IP "\fB\-m\fR\fIcpu\fR" 4

   709 .IX Item "-mcpu"

   710 Enable the instruction set extensions supported by a particular \s-1CPU\s0, and

   711 disable all other extensions.

   712 .IP "\fB\-m\fR\fImachine\fR" 4

   713 .IX Item "-mmachine"

   714 Enable the instruction set extensions supported by a particular machine

   715 model, and disable all other extensions.

   716 .PP

   717 The following options are available when as is configured for

   718 a picoJava processor.

   719 .IP "\fB\-mb\fR" 4

   720 .IX Item "-mb"

   721 Generate \*(L"big endian\*(R" format output.

   722 .IP "\fB\-ml\fR" 4

   723 .IX Item "-ml"

   724 Generate \*(L"little endian\*(R" format output.

   725 .PP

   726 The following options are available when as is configured for the

   727 Motorola 68HC11 or 68HC12 series.

   728 .IP "\fB\-m68hc11 | \-m68hc12 | \-m68hcs12\fR" 4

   729 .IX Item "-m68hc11 | -m68hc12 | -m68hcs12"

   730 Specify what processor is the target.  The default is

   731 defined by the configuration option when building the assembler.

   732 .IP "\fB\-mshort\fR" 4

   733 .IX Item "-mshort"

   734 Specify to use the 16\-bit integer \s-1ABI\s0.

   735 .IP "\fB\-mlong\fR" 4

   736 .IX Item "-mlong"

   737 Specify to use the 32\-bit integer \s-1ABI\s0.  

   738 .IP "\fB\-mshort\-double\fR" 4

   739 .IX Item "-mshort-double"

   740 Specify to use the 32\-bit double \s-1ABI\s0.  

   741 .IP "\fB\-mlong\-double\fR" 4

   742 .IX Item "-mlong-double"

   743 Specify to use the 64\-bit double \s-1ABI\s0.  

   744 .IP "\fB\-\-force\-long\-branches\fR" 4

   745 .IX Item "--force-long-branches"

   746 Relative branches are turned into absolute ones. This concerns

   747 conditional branches, unconditional branches and branches to a

   748 sub routine.

   749 .IP "\fB\-S | \-\-short\-branches\fR" 4

   750 .IX Item "-S | --short-branches"

   751 Do not turn relative branches into absolute ones

   752 when the offset is out of range.

   753 .IP "\fB\-\-strict\-direct\-mode\fR" 4

   754 .IX Item "--strict-direct-mode"

   755 Do not turn the direct addressing mode into extended addressing mode

   756 when the instruction does not support direct addressing mode.

   757 .IP "\fB\-\-print\-insn\-syntax\fR" 4

   758 .IX Item "--print-insn-syntax"

   759 Print the syntax of instruction in case of error.

   760 .IP "\fB\-\-print\-opcodes\fR" 4

   761 .IX Item "--print-opcodes"

   762 print the list of instructions with syntax and then exit.

   763 .IP "\fB\-\-generate\-example\fR" 4

   764 .IX Item "--generate-example"

   765 print an example of instruction for each possible instruction and then exit.

   766 This option is only useful for testing \fBas\fR.

   767 .PP

   768 The following options are available when \fBas\fR is configured

   769 for the \s-1SPARC\s0 architecture:

   770 .IP "\fB\-Av6 | \-Av7 | \-Av8 | \-Asparclet | \-Asparclite\fR" 4

   771 .IX Item "-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite"

   772 .PD 0

   773 .IP "\fB\-Av8plus | \-Av8plusa | \-Av9 | \-Av9a\fR" 4

   774 .IX Item "-Av8plus | -Av8plusa | -Av9 | -Av9a"

   775 .PD

   776 Explicitly select a variant of the \s-1SPARC\s0 architecture.

   777 .Sp

   778 \&\fB\-Av8plus\fR and \fB\-Av8plusa\fR select a 32 bit environment.

   779 \&\fB\-Av9\fR and \fB\-Av9a\fR select a 64 bit environment.

   780 .Sp

   781 \&\fB\-Av8plusa\fR and \fB\-Av9a\fR enable the \s-1SPARC\s0 V9 instruction set with

   782 UltraSPARC extensions.

   783 .IP "\fB\-xarch=v8plus | \-xarch=v8plusa\fR" 4

   784 .IX Item "-xarch=v8plus | -xarch=v8plusa"

   785 For compatibility with the Solaris v9 assembler.  These options are

   786 equivalent to \-Av8plus and \-Av8plusa, respectively.

   787 .IP "\fB\-bump\fR" 4

   788 .IX Item "-bump"

   789 Warn when the assembler switches to another architecture.

   790 .PP

   791 The following options are available when as is configured for the 'c54x

   792 architecture. 

   793 .IP "\fB\-mfar\-mode\fR" 4

   794 .IX Item "-mfar-mode"

   795 Enable extended addressing mode.  All addresses and relocations will assume

   796 extended addressing (usually 23 bits).

   797 .IP "\fB\-mcpu=\fR\fI\s-1CPU_VERSION\s0\fR" 4

   798 .IX Item "-mcpu=CPU_VERSION"

   799 Sets the \s-1CPU\s0 version being compiled for.

   800 .IP "\fB\-merrors\-to\-file\fR \fI\s-1FILENAME\s0\fR" 4

   801 .IX Item "-merrors-to-file FILENAME"

   802 Redirect error output to a file, for broken systems which don't support such

   803 behaviour in the shell.

   804 .PP

   805 The following options are available when as is configured for

   806 a \s-1MIPS\s0 processor.

   807 .IP "\fB\-G\fR \fInum\fR" 4

   808 .IX Item "-G num"

   809 This option sets the largest size of an object that can be referenced

   810 implicitly with the \f(CW\*(C`gp\*(C'\fR register.  It is only accepted for targets that

   811 use \s-1ECOFF\s0 format, such as a DECstation running Ultrix.  The default value is 8.

   812 .IP "\fB\-EB\fR" 4

   813 .IX Item "-EB"

   814 Generate \*(L"big endian\*(R" format output.

   815 .IP "\fB\-EL\fR" 4

   816 .IX Item "-EL"

   817 Generate \*(L"little endian\*(R" format output.

   818 .IP "\fB\-mips1\fR" 4

   819 .IX Item "-mips1"

   820 .PD 0

   821 .IP "\fB\-mips2\fR" 4

   822 .IX Item "-mips2"

   823 .IP "\fB\-mips3\fR" 4

   824 .IX Item "-mips3"

   825 .IP "\fB\-mips4\fR" 4

   826 .IX Item "-mips4"

   827 .IP "\fB\-mips5\fR" 4

   828 .IX Item "-mips5"

   829 .IP "\fB\-mips32\fR" 4

   830 .IX Item "-mips32"

   831 .IP "\fB\-mips32r2\fR" 4

   832 .IX Item "-mips32r2"

   833 .IP "\fB\-mips64\fR" 4

   834 .IX Item "-mips64"

   835 .IP "\fB\-mips64r2\fR" 4

   836 .IX Item "-mips64r2"

   837 .PD

   838 Generate code for a particular \s-1MIPS\s0 Instruction Set Architecture level.

   839 \&\fB\-mips1\fR is an alias for \fB\-march=r3000\fR, \fB\-mips2\fR is an

   840 alias for \fB\-march=r6000\fR, \fB\-mips3\fR is an alias for

   841 \&\fB\-march=r4000\fR and \fB\-mips4\fR is an alias for \fB\-march=r8000\fR.

   842 \&\fB\-mips5\fR, \fB\-mips32\fR, \fB\-mips32r2\fR, \fB\-mips64\fR, and

   843 \&\fB\-mips64r2\fR

   844 correspond to generic

   845 \&\fB\s-1MIPS\s0 V\fR, \fB\s-1MIPS32\s0\fR, \fB\s-1MIPS32\s0 Release 2\fR, \fB\s-1MIPS64\s0\fR,

   846 and \fB\s-1MIPS64\s0 Release 2\fR

   847 \&\s-1ISA\s0 processors, respectively.

   848 .IP "\fB\-march=\fR\fI\s-1CPU\s0\fR" 4

   849 .IX Item "-march=CPU"

   850 Generate code for a particular \s-1MIPS\s0 cpu.

   851 .IP "\fB\-mtune=\fR\fIcpu\fR" 4

   852 .IX Item "-mtune=cpu"

   853 Schedule and tune for a particular \s-1MIPS\s0 cpu.

   854 .IP "\fB\-mfix7000\fR" 4

   855 .IX Item "-mfix7000"

   856 .PD 0

   857 .IP "\fB\-mno\-fix7000\fR" 4

   858 .IX Item "-mno-fix7000"

   859 .PD

   860 Cause nops to be inserted if the read of the destination register

   861 of an mfhi or mflo instruction occurs in the following two instructions.

   862 .IP "\fB\-mdebug\fR" 4

   863 .IX Item "-mdebug"

   864 .PD 0

   865 .IP "\fB\-no\-mdebug\fR" 4

   866 .IX Item "-no-mdebug"

   867 .PD

   868 Cause stabs-style debugging output to go into an ECOFF-style .mdebug

   869 section instead of the standard \s-1ELF\s0 .stabs sections.

   870 .IP "\fB\-mpdr\fR" 4

   871 .IX Item "-mpdr"

   872 .PD 0

   873 .IP "\fB\-mno\-pdr\fR" 4

   874 .IX Item "-mno-pdr"

   875 .PD

   876 Control generation of \f(CW\*(C`.pdr\*(C'\fR sections.

   877 .IP "\fB\-mgp32\fR" 4

   878 .IX Item "-mgp32"

   879 .PD 0

   880 .IP "\fB\-mfp32\fR" 4

   881 .IX Item "-mfp32"

   882 .PD

   883 The register sizes are normally inferred from the \s-1ISA\s0 and \s-1ABI\s0, but these

   884 flags force a certain group of registers to be treated as 32 bits wide at

   885 all times.  \fB\-mgp32\fR controls the size of general-purpose registers

   886 and \fB\-mfp32\fR controls the size of floating-point registers.

   887 .IP "\fB\-mips16\fR" 4

   888 .IX Item "-mips16"

   889 .PD 0

   890 .IP "\fB\-no\-mips16\fR" 4

   891 .IX Item "-no-mips16"

   892 .PD

   893 Generate code for the \s-1MIPS\s0 16 processor.  This is equivalent to putting

   894 \&\f(CW\*(C`.set mips16\*(C'\fR at the start of the assembly file.  \fB\-no\-mips16\fR

   895 turns off this option.

   896 .IP "\fB\-msmartmips\fR" 4

   897 .IX Item "-msmartmips"

   898 .PD 0

   899 .IP "\fB\-mno\-smartmips\fR" 4

   900 .IX Item "-mno-smartmips"

   901 .PD

   902 Enables the SmartMIPS extension to the \s-1MIPS32\s0 instruction set. This is

   903 equivalent to putting \f(CW\*(C`.set smartmips\*(C'\fR at the start of the assembly file.

   904 \&\fB\-mno\-smartmips\fR turns off this option.

   905 .IP "\fB\-mips3d\fR" 4

   906 .IX Item "-mips3d"

   907 .PD 0

   908 .IP "\fB\-no\-mips3d\fR" 4

   909 .IX Item "-no-mips3d"

   910 .PD

   911 Generate code for the \s-1MIPS\-3D\s0 Application Specific Extension.

   912 This tells the assembler to accept \s-1MIPS\-3D\s0 instructions.

   913 \&\fB\-no\-mips3d\fR turns off this option.

   914 .IP "\fB\-mdmx\fR" 4

   915 .IX Item "-mdmx"

   916 .PD 0

   917 .IP "\fB\-no\-mdmx\fR" 4

   918 .IX Item "-no-mdmx"

   919 .PD

   920 Generate code for the \s-1MDMX\s0 Application Specific Extension.

   921 This tells the assembler to accept \s-1MDMX\s0 instructions.

   922 \&\fB\-no\-mdmx\fR turns off this option.

   923 .IP "\fB\-mdsp\fR" 4

   924 .IX Item "-mdsp"

   925 .PD 0

   926 .IP "\fB\-mno\-dsp\fR" 4

   927 .IX Item "-mno-dsp"

   928 .PD

   929 Generate code for the \s-1DSP\s0 Release 1 Application Specific Extension.

   930 This tells the assembler to accept \s-1DSP\s0 Release 1 instructions.

   931 \&\fB\-mno\-dsp\fR turns off this option.

   932 .IP "\fB\-mdspr2\fR" 4

   933 .IX Item "-mdspr2"

   934 .PD 0

   935 .IP "\fB\-mno\-dspr2\fR" 4

   936 .IX Item "-mno-dspr2"

   937 .PD

   938 Generate code for the \s-1DSP\s0 Release 2 Application Specific Extension.

   939 This option implies \-mdsp.

   940 This tells the assembler to accept \s-1DSP\s0 Release 2 instructions.

   941 \&\fB\-mno\-dspr2\fR turns off this option.

   942 .IP "\fB\-mmt\fR" 4

   943 .IX Item "-mmt"

   944 .PD 0

   945 .IP "\fB\-mno\-mt\fR" 4

   946 .IX Item "-mno-mt"

   947 .PD

   948 Generate code for the \s-1MT\s0 Application Specific Extension.

   949 This tells the assembler to accept \s-1MT\s0 instructions.

   950 \&\fB\-mno\-mt\fR turns off this option.

   951 .IP "\fB\-\-construct\-floats\fR" 4

   952 .IX Item "--construct-floats"

   953 .PD 0

   954 .IP "\fB\-\-no\-construct\-floats\fR" 4

   955 .IX Item "--no-construct-floats"

   956 .PD

   957 The \fB\-\-no\-construct\-floats\fR option disables the construction of

   958 double width floating point constants by loading the two halves of the

   959 value into the two single width floating point registers that make up

   960 the double width register.  By default \fB\-\-construct\-floats\fR is

   961 selected, allowing construction of these floating point constants.

   962 .IP "\fB\-\-emulation=\fR\fIname\fR" 4

   963 .IX Item "--emulation=name"

   964 This option causes \fBas\fR to emulate \fBas\fR configured

   965 for some other target, in all respects, including output format (choosing

   966 between \s-1ELF\s0 and \s-1ECOFF\s0 only), handling of pseudo-opcodes which may generate

   967 debugging information or store symbol table information, and default

   968 endianness.  The available configuration names are: \fBmipsecoff\fR,

   969 \&\fBmipself\fR, \fBmipslecoff\fR, \fBmipsbecoff\fR, \fBmipslelf\fR,

   970 \&\fBmipsbelf\fR.  The first two do not alter the default endianness from that

   971 of the primary target for which the assembler was configured; the others change

   972 the default to little\- or big-endian as indicated by the \fBb\fR or \fBl\fR

   973 in the name.  Using \fB\-EB\fR or \fB\-EL\fR will override the endianness

   974 selection in any case.

   975 .Sp

   976 This option is currently supported only when the primary target

   977 \&\fBas\fR is configured for is a \s-1MIPS\s0 \s-1ELF\s0 or \s-1ECOFF\s0 target.

   978 Furthermore, the primary target or others specified with

   979 \&\fB\-\-enable\-targets=...\fR at configuration time must include support for

   980 the other format, if both are to be available.  For example, the Irix 5

   981 configuration includes support for both.

   982 .Sp

   983 Eventually, this option will support more configurations, with more

   984 fine-grained control over the assembler's behavior, and will be supported for

   985 more processors.

   986 .IP "\fB\-nocpp\fR" 4

   987 .IX Item "-nocpp"

   988 \&\fBas\fR ignores this option.  It is accepted for compatibility with

   989 the native tools.

   990 .IP "\fB\-\-trap\fR" 4

   991 .IX Item "--trap"

   992 .PD 0

   993 .IP "\fB\-\-no\-trap\fR" 4

   994 .IX Item "--no-trap"

   995 .IP "\fB\-\-break\fR" 4

   996 .IX Item "--break"

   997 .IP "\fB\-\-no\-break\fR" 4

   998 .IX Item "--no-break"

   999 .PD

  1000 Control how to deal with multiplication overflow and division by zero.

  1001 \&\fB\-\-trap\fR or \fB\-\-no\-break\fR (which are synonyms) take a trap exception

  1002 (and only work for Instruction Set Architecture level 2 and higher);

  1003 \&\fB\-\-break\fR or \fB\-\-no\-trap\fR (also synonyms, and the default) take a

  1004 break exception.

  1005 .IP "\fB\-n\fR" 4

  1006 .IX Item "-n"

  1007 When this option is used, \fBas\fR will issue a warning every

  1008 time it generates a nop instruction from a macro.

  1009 .PP

  1010 The following options are available when as is configured for

  1011 an MCore processor.

  1012 .IP "\fB\-jsri2bsr\fR" 4

  1013 .IX Item "-jsri2bsr"

  1014 .PD 0

  1015 .IP "\fB\-nojsri2bsr\fR" 4

  1016 .IX Item "-nojsri2bsr"

  1017 .PD

  1018 Enable or disable the \s-1JSRI\s0 to \s-1BSR\s0 transformation.  By default this is enabled.

  1019 The command line option \fB\-nojsri2bsr\fR can be used to disable it.

  1020 .IP "\fB\-sifilter\fR" 4

  1021 .IX Item "-sifilter"

  1022 .PD 0

  1023 .IP "\fB\-nosifilter\fR" 4

  1024 .IX Item "-nosifilter"

  1025 .PD

  1026 Enable or disable the silicon filter behaviour.  By default this is disabled.

  1027 The default can be overridden by the \fB\-sifilter\fR command line option.

  1028 .IP "\fB\-relax\fR" 4

  1029 .IX Item "-relax"

  1030 Alter jump instructions for long displacements.

  1031 .IP "\fB\-mcpu=[210|340]\fR" 4

  1032 .IX Item "-mcpu=[210|340]"

  1033 Select the cpu type on the target hardware.  This controls which instructions

  1034 can be assembled.

  1035 .IP "\fB\-EB\fR" 4

  1036 .IX Item "-EB"

  1037 Assemble for a big endian target.

  1038 .IP "\fB\-EL\fR" 4

  1039 .IX Item "-EL"

  1040 Assemble for a little endian target.

  1041 .PP

  1042 See the info pages for documentation of the MMIX-specific options.

  1043 .PP

  1044 The following options are available when as is configured for

  1045 an Xtensa processor.

  1046 .IP "\fB\-\-text\-section\-literals | \-\-no\-text\-section\-literals\fR" 4

  1047 .IX Item "--text-section-literals | --no-text-section-literals"

  1048 With \fB\-\-text\-section\-literals\fR, literal pools are interspersed

  1049 in the text section.  The default is

  1050 \&\fB\-\-no\-text\-section\-literals\fR, which places literals in a

  1051 separate section in the output file.  These options only affect literals

  1052 referenced via PC-relative \f(CW\*(C`L32R\*(C'\fR instructions; literals for

  1053 absolute mode \f(CW\*(C`L32R\*(C'\fR instructions are handled separately.

  1054 .IP "\fB\-\-absolute\-literals | \-\-no\-absolute\-literals\fR" 4

  1055 .IX Item "--absolute-literals | --no-absolute-literals"

  1056 Indicate to the assembler whether \f(CW\*(C`L32R\*(C'\fR instructions use absolute

  1057 or PC-relative addressing.  The default is to assume absolute addressing

  1058 if the Xtensa processor includes the absolute \f(CW\*(C`L32R\*(C'\fR addressing

  1059 option.  Otherwise, only the PC-relative \f(CW\*(C`L32R\*(C'\fR mode can be used.

  1060 .IP "\fB\-\-target\-align | \-\-no\-target\-align\fR" 4

  1061 .IX Item "--target-align | --no-target-align"

  1062 Enable or disable automatic alignment to reduce branch penalties at the

  1063 expense of some code density.  The default is \fB\-\-target\-align\fR.

  1064 .IP "\fB\-\-longcalls | \-\-no\-longcalls\fR" 4

  1065 .IX Item "--longcalls | --no-longcalls"

  1066 Enable or disable transformation of call instructions to allow calls

  1067 across a greater range of addresses.  The default is

  1068 \&\fB\-\-no\-longcalls\fR.

  1069 .IP "\fB\-\-transform | \-\-no\-transform\fR" 4

  1070 .IX Item "--transform | --no-transform"

  1071 Enable or disable all assembler transformations of Xtensa instructions.

  1072 The default is \fB\-\-transform\fR;

  1073 \&\fB\-\-no\-transform\fR should be used only in the rare cases when the

  1074 instructions must be exactly as specified in the assembly source.

  1075 .IP "\fB\-\-rename\-section\fR \fIoldname\fR\fB=\fR\fInewname\fR" 4

  1076 .IX Item "--rename-section oldname=newname"

  1077 When generating output sections, rename the \fIoldname\fR section to

  1078 \&\fInewname\fR.

  1079 .PP

  1080 The following options are available when as is configured for

  1081 a Z80 family processor.

  1082 .IP "\fB\-z80\fR" 4

  1083 .IX Item "-z80"

  1084 Assemble for Z80 processor.

  1085 .IP "\fB\-r800\fR" 4

  1086 .IX Item "-r800"

  1087 Assemble for R800 processor.

  1088 .IP "\fB\-ignore\-undocumented\-instructions\fR" 4

  1089 .IX Item "-ignore-undocumented-instructions"

  1090 .PD 0

  1091 .IP "\fB\-Wnud\fR" 4

  1092 .IX Item "-Wnud"

  1093 .PD

  1094 Assemble undocumented Z80 instructions that also work on R800 without warning.

  1095 .IP "\fB\-ignore\-unportable\-instructions\fR" 4

  1096 .IX Item "-ignore-unportable-instructions"

  1097 .PD 0

  1098 .IP "\fB\-Wnup\fR" 4

  1099 .IX Item "-Wnup"

  1100 .PD

  1101 Assemble all undocumented Z80 instructions without warning.

  1102 .IP "\fB\-warn\-undocumented\-instructions\fR" 4

  1103 .IX Item "-warn-undocumented-instructions"

  1104 .PD 0

  1105 .IP "\fB\-Wud\fR" 4

  1106 .IX Item "-Wud"

  1107 .PD

  1108 Issue a warning for undocumented Z80 instructions that also work on R800.

  1109 .IP "\fB\-warn\-unportable\-instructions\fR" 4

  1110 .IX Item "-warn-unportable-instructions"

  1111 .PD 0

  1112 .IP "\fB\-Wup\fR" 4

  1113 .IX Item "-Wup"

  1114 .PD

  1115 Issue a warning for undocumented Z80 instructions that do not work on R800.  

  1116 .IP "\fB\-forbid\-undocumented\-instructions\fR" 4

  1117 .IX Item "-forbid-undocumented-instructions"

  1118 .PD 0

  1119 .IP "\fB\-Fud\fR" 4

  1120 .IX Item "-Fud"

  1121 .PD

  1122 Treat all undocumented instructions as errors.

  1123 .IP "\fB\-forbid\-unportable\-instructions\fR" 4

  1124 .IX Item "-forbid-unportable-instructions"

  1125 .PD 0

  1126 .IP "\fB\-Fup\fR" 4

  1127 .IX Item "-Fup"

  1128 .PD

  1129 Treat undocumented Z80 instructions that do not work on R800 as errors.

  1130 .SH "SEE ALSO"

  1131 .IX Header "SEE ALSO"

  1132 \&\fIgcc\fR\|(1), \fIld\fR\|(1), and the Info entries for \fIbinutils\fR and \fIld\fR.

  1133 .SH "COPYRIGHT"

  1134 .IX Header "COPYRIGHT"

  1135 Copyright (c) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002,