| changeset 76 | 0d34a4aa948d |
| parent 34 | 161f6b2f6990 |
| 47:deed9c658f70 | 76:0d34a4aa948d |
|---|---|
15 // omap3530/beagle_drivers/lcd/lcd.cpp |
15 // omap3530/beagle_drivers/lcd/lcd.cpp |
16 // Implementation of an LCD driver. |
16 // Implementation of an LCD driver. |
17 // This file is part of the Beagle Base port |
17 // This file is part of the Beagle Base port |
18 // N.B. This sample code assumes that the display supports setting the backlight on or off, |
18 // N.B. This sample code assumes that the display supports setting the backlight on or off, |
19 // as well as adjusting the contrast and the brightness. |
19 // as well as adjusting the contrast and the brightness. |
20 // |
20 //// |
21 |
|
21 |
22 |
22 #include <videodriver.h> |
23 #include <videodriver.h> |
23 #include <platform.h> |
24 #include <platform.h> |
24 #include <nkern.h> |
25 #include <nkern.h> |
25 #include <kernel.h> |
26 #include <kernel.h> |
37 |
38 |
38 #define DISPC_SYSCONFIG 0x48050410 |
39 #define DISPC_SYSCONFIG 0x48050410 |
39 #define DISPC_CONFIG 0x48050444 |
40 #define DISPC_CONFIG 0x48050444 |
40 #define DISPC_DEFAULT_COLOR0 0x4805044c |
41 #define DISPC_DEFAULT_COLOR0 0x4805044c |
41 #define DISPC_TRANS_COLOR0 0x48050454 |
42 #define DISPC_TRANS_COLOR0 0x48050454 |
43 #define DISPC_LINE_STATUS 0x4805045C |
|
42 |
44 |
43 #define DISPC_TIMING_H 0x48050464 |
45 #define DISPC_TIMING_H 0x48050464 |
44 #define DISPC_TIMING_V 0x48050468 |
46 #define DISPC_TIMING_V 0x48050468 |
45 #define DISPC_POL_FREQ 0x4805046c |
47 #define DISPC_POL_FREQ 0x4805046c |
46 #define DISPC_DIVISOR 0x48050470 |
48 #define DISPC_DIVISOR 0x48050470 |
57 #define DISPC_GFX_ROW_INC 0x480504ac |
59 #define DISPC_GFX_ROW_INC 0x480504ac |
58 #define DISPC_GFX_PIXEL_INC 0x480504b0 |
60 #define DISPC_GFX_PIXEL_INC 0x480504b0 |
59 #define DISPC_GFX_WINDOW_SKIP 0x480504b4 |
61 #define DISPC_GFX_WINDOW_SKIP 0x480504b4 |
60 #define DISPC_GFX_TABLE_BA 0x480504b8 |
62 #define DISPC_GFX_TABLE_BA 0x480504b8 |
61 |
63 |
64 #define VENC_F_CONTROL 0x48050C08 |
|
62 #define DISPC_CONTROL 0x48050440 |
65 #define DISPC_CONTROL 0x48050440 |
63 |
66 |
64 #define GET_REGISTER(Reg) *( (TUint *) Omap3530HwBase::TVirtual<Reg>::Value ) |
67 #define GET_REGISTER(Reg) *( (TUint *) Omap3530HwBase::TVirtual<Reg>::Value ) |
65 #define SET_REGISTER(Reg,Val) *( (TUint *) Omap3530HwBase::TVirtual<Reg>::Value ) = Val |
68 #define SET_REGISTER(Reg,Val) *( (TUint *) Omap3530HwBase::TVirtual<Reg>::Value ) = Val |
66 |
69 |
70 #define GPIO3_OE 0x49052034 |
|
71 #define GPIO3_CLEARDATAOUT 0x49052090 |
|
72 #define GPIO3_SETDATAOUT 0x49052094 |
|
73 #define CONTROL_PADCONF_DSS_DATA18 0x48002100 |
|
74 #define CONTROL_PADCONF_DSS_DATA20 0x48002104 |
|
75 #define CONTROL_PADCONF_DSS_DATA22 0x48002108 |
|
76 |
|
77 //const TUint32 SPICLK=0x01000000,SPISDAO=0x02000000,SPISDAI=0x04000000,SPICS0=0x08000000,SPIRESET=0x10000000; |
|
78 |
|
79 |
|
80 #define GPIO5_OE 0x49056034 |
|
81 #define GPIO5_CLEARDATAOUT 0x49056090 |
|
82 #define GPIO5_SETDATAOUT 0x49056094 |
|
83 #define GPIO5_DATADRAIN 0x49056038 |
|
84 #define CONTROL_PADCONF_MMC2_CLK 0x48002158 |
|
85 #define CONTROL_PADCONF_MMC2_DAT0 0x4800215C |
|
86 #define CONTROL_PADCONF_MMC2_DAT2 0x48002160 |
|
87 #define CONTROL_PADCONF_MMC2_DAT4 0x48002164 |
|
88 |
|
89 #define KEXTENSION KALWAYS |
|
90 |
|
91 //const TUint32 SPICLK=0x00000004,SPISDAO=0x00000008,SPISDAI=0x00000010,SPICS0=0x00000040/*GPIO134*/,SPIRESET=0x00000080; |
|
92 const TUint32 SPICS0=0x00000040/*GPIO134*/,SPICLK=0x01000000,SPISDAO=0x02000000, |
|
93 SPISDAI=0x04000000,SPIRESET=0x20000000; |
|
94 /** |
|
67 #define _MODE_1280x1024_ |
95 #define _MODE_1280x1024_ |
68 //#define _MODE_1024x768_ |
96 //#define _MODE_1024x768_ |
69 |
97 |
70 #ifdef _MODE_800x600_ |
98 #ifdef _MODE_800x600_ |
71 // ModeLine "800x600@60" 40.0 800 840 968 1056 600 601 605 628 +hsync +vsync |
99 // ModeLine "800x600@60" 40.0 800 840 968 1056 600 601 605 628 +hsync +vsync |
113 # define V_SYNC 3 |
141 # define V_SYNC 3 |
114 # define V_BPORCH 38 |
142 # define V_BPORCH 38 |
115 # define V_SYNC_POL 1 |
143 # define V_SYNC_POL 1 |
116 # define INTERLACE_ENABLE 0 |
144 # define INTERLACE_ENABLE 0 |
117 #endif |
145 #endif |
118 |
146 */ |
147 # define PIXEL_CLK 25000 //this value is just the RGB's clk |
|
148 # define H_DISP 480 |
|
149 # define H_FPORCH 20 |
|
150 # define H_SYNC 20 |
|
151 # define H_BPORCH 20 |
|
152 # define H_SYNC_POL 1 |
|
153 # define V_DISP 800 |
|
154 # define V_FPORCH 500 |
|
155 # define V_SYNC 250 |
|
156 # define V_BPORCH 500 |
|
157 # define V_SYNC_POL 1 |
|
158 # define INTERLACE_ENABLE 0 |
|
119 |
159 |
120 |
160 |
121 // TO DO: (mandatory) |
161 // TO DO: (mandatory) |
122 // If the display supports Contrast and/or Brightness control then supply the following defines: |
162 // If the display supports Contrast and/or Brightness control then supply the following defines: |
123 // This is only example code... you may need to modify it for your hardware |
163 // This is only example code... you may need to modify it for your hardware |
137 |
177 |
138 |
178 |
139 // TO DO: (mandatory) |
179 // TO DO: (mandatory) |
140 // define the physical screen dimensions |
180 // define the physical screen dimensions |
141 // This is only example code... you need to modify it for your hardware |
181 // This is only example code... you need to modify it for your hardware |
142 const TUint KConfigLcdWidth = 360;//640; // 640 pixels per line |
182 //const TUint KConfigLcdWidth = 480;//360;//640; // 640 pixels per line |
143 const TUint KConfigLcdHeight = 640;//480; // 480 lines per panel |
183 //const TUint KConfigLcdHeight = 800;//640;//480; // 480 lines per panel |
144 |
184 const TUint KConfigLcdWidth = 360;//360;//640; // 640 pixels per line |
185 const TUint KConfigLcdHeight = 640;//640;//480; // 480 lines per panel |
|
145 // TO DO: (mandatory) |
186 // TO DO: (mandatory) |
146 // define the characteristics of the LCD display |
187 // define the characteristics of the LCD display |
147 // This is only example code... you need to modify it for your hardware |
188 // This is only example code... you need to modify it for your hardware |
148 const TBool KConfigLcdIsMono = EFalse; |
189 const TBool KConfigLcdIsMono = EFalse; |
149 const TBool KConfigLcdPixelOrderLandscape = ETrue; |
190 const TBool KConfigLcdPixelOrderLandscape = EFalse;//ETrue; |
150 const TBool KConfigLcdPixelOrderRGB = ETrue; |
191 const TBool KConfigLcdPixelOrderRGB = ETrue; |
151 const TInt KConfigLcdMaxDisplayColors = 16777216;//65536; //24bit: 16777216; |
192 //const TInt KConfigLcdMaxDisplayColors = 262144;//16777216;//65536; //24bit: 16777216; |
193 const TInt KConfigLcdMaxDisplayColors = 16777216;//262144;//16777216;//65536; //24bit: 16777216; |
|
152 |
194 |
153 |
195 |
154 // TO DO: (mandatory) |
196 // TO DO: (mandatory) |
155 // define the display dimensions in TWIPs |
197 // define the display dimensions in TWIPs |
156 // A TWIP is a 20th of a point. A point is a 72nd of an inch |
198 // A TWIP is a 20th of a point. A point is a 72nd of an inch |
157 // Therefore a TWIP is a 1440th of an inch |
199 // Therefore a TWIP is a 1440th of an inch |
158 // This is only example code... you need to modify it for your hardware |
200 // This is only example code... you need to modify it for your hardware |
159 const TInt KConfigLcdWidthInTwips = 2670; // = 6.69 inches //15*1440; |
201 const TInt KConfigLcdWidthInTwips = 2670;//2670; // = 6.69 inches //15*1440; |
160 const TInt KConfigLcdHeightInTwips = 3550; //5616; // = 5.11 inches //12*1440; |
202 const TInt KConfigLcdHeightInTwips = 3550;//3550; //5616; // = 5.11 inches //12*1440; |
161 |
203 |
162 // TO DO: (mandatory) |
204 // TO DO: (mandatory) |
163 // define the available display modes |
205 // define the available display modes |
164 // This is only example code... you need to modify it for your hardware |
206 // This is only example code... you need to modify it for your hardware |
165 const TInt KConfigLcdNumberOfDisplayModes = 1; |
207 const TInt KConfigLcdNumberOfDisplayModes = 1; |
176 static const SLcdConfig Lcd_Mode_Config[KConfigLcdNumberOfDisplayModes]= |
218 static const SLcdConfig Lcd_Mode_Config[KConfigLcdNumberOfDisplayModes]= |
177 { |
219 { |
178 { |
220 { |
179 0, // iMode |
221 0, // iMode |
180 0, // iOffsetToFirstVideoBuffer |
222 0, // iOffsetToFirstVideoBuffer |
223 // FRAME_BUFFER_SIZE(16/*32*//*16*/, KConfigLcdWidth, KConfigLcdHeight), // iLenghtOfVideoBufferInBytes |
|
224 // KConfigLcdWidth*2/*4*/,//2, // iOffsetBetweenLines |
|
225 // EFalse, // iIsPalettized |
|
226 // 16/*32,*///16 // iBitsPerPixel |
|
181 FRAME_BUFFER_SIZE(32/*16*/, KConfigLcdWidth, KConfigLcdHeight), // iLenghtOfVideoBufferInBytes |
227 FRAME_BUFFER_SIZE(32/*16*/, KConfigLcdWidth, KConfigLcdHeight), // iLenghtOfVideoBufferInBytes |
182 KConfigLcdWidth*4,//2, // iOffsetBetweenLines |
228 KConfigLcdWidth*4,//2, // iOffsetBetweenLines |
183 EFalse, // iIsPalettized |
229 EFalse, // iIsPalettized |
184 32,//16 // iBitsPerPixel |
230 32,//16 // iBitsPerPixel |
231 |
|
185 } |
232 } |
186 }; |
233 }; |
187 |
234 |
188 |
235 |
189 |
236 |
255 TBool iDisplayOn; // to prevent a race condition with WServer trying to power up/down at the same time |
302 TBool iDisplayOn; // to prevent a race condition with WServer trying to power up/down at the same time |
256 DPlatChunkHw* iChunk; |
303 DPlatChunkHw* iChunk; |
257 DPlatChunkHw* iSecureChunk; |
304 DPlatChunkHw* iSecureChunk; |
258 TBool iWsSwitchOnScreen; |
305 TBool iWsSwitchOnScreen; |
259 TBool iSecureDisplay; |
306 TBool iSecureDisplay; |
307 // TDfcQue* iDfcQ; |
|
260 TMessageQue iMsgQ; |
308 TMessageQue iMsgQ; |
261 TDfc iPowerUpDfc; |
309 TDfc iPowerUpDfc; |
262 TDfc iPowerDownDfc; |
310 TDfc iPowerDownDfc; |
263 |
311 |
264 #ifndef ENABLE_GCE_MODE |
312 #ifndef ENABLE_GCE_MODE |
267 TPhysAddr ivRamPhys; |
315 TPhysAddr ivRamPhys; |
268 #endif |
316 #endif |
269 |
317 |
270 TVideoInfoV01 iSecureVideoInfo; |
318 TVideoInfoV01 iSecureVideoInfo; |
271 NFastMutex iLock; // protects against being preempted whilst manipulating iVideoInfo/iSecureVideoInfo |
319 NFastMutex iLock; // protects against being preempted whilst manipulating iVideoInfo/iSecureVideoInfo |
320 // TPhysAddr ivRamPhys; |
|
272 TPhysAddr iSecurevRamPhys; |
321 TPhysAddr iSecurevRamPhys; |
273 |
322 |
274 TBool iBacklightOn; |
323 TBool iBacklightOn; |
275 TInt iContrast; |
324 TInt iContrast; |
276 TInt iBrightness; |
325 TInt iBrightness; |
319 void power_down_dfc(TAny* aPtr) |
368 void power_down_dfc(TAny* aPtr) |
320 { |
369 { |
321 ((DLcdPowerHandler*)aPtr)->PowerDownDfc(); |
370 ((DLcdPowerHandler*)aPtr)->PowerDownDfc(); |
322 } |
371 } |
323 |
372 |
373 void Wait_(void) //Wait_() nearly =1ms |
|
374 { |
|
375 Kern::NanoWait(7000000); |
|
376 // Kern::NanoWait(10000000); |
|
377 // Kern::NanoWait(10000000); |
|
378 // Kern::NanoWait(10000000); |
|
379 |
|
380 } |
|
381 void Wait_1(void) |
|
382 { |
|
383 Kern::NanoWait(700000); |
|
384 } |
|
385 void Wait(int ms) |
|
386 { |
|
387 for(int i=0;i<ms;i++) |
|
388 Wait_(); |
|
389 } |
|
390 void Wait2(int ms) |
|
391 { |
|
392 for(int i=0;i<ms;i++) |
|
393 Wait_(); |
|
394 } |
|
395 void Wait3(int ms) |
|
396 { |
|
397 for(int i=0;i<ms;i++) |
|
398 Wait_1(); |
|
399 } |
|
400 |
|
401 |
|
402 /** |
|
403 set the mux mode to GPIO, used to simulate GPIO function |
|
404 SCL--GPIO88,--output |
|
405 SDO--GPIO89,--output |
|
406 SDI--GPIO90--input |
|
407 CSa--GPIO91--output |
|
408 CSb--GPIO92--output |
|
409 RESET--GPIO93--output |
|
410 CS0--GPIO134--output, LCD's chip select |
|
411 */ |
|
412 void SET_GPIOTOSPI(void) |
|
413 { |
|
414 TUint32 l=0x00; |
|
415 TInt8 n=0x01,n1=0x04; |
|
416 TInt8 muxmode=0x04;//set mode4(GPIO) |
|
417 // l=GET_REGISTER(CONTROL_PADCONF_MMC2_CLK)&0xFFF8FFF8|muxmode|muxmode<<16; //set as GPIO130.131 |
|
418 // SET_REGISTER(CONTROL_PADCONF_MMC2_CLK,l); |
|
419 l=GET_REGISTER(CONTROL_PADCONF_MMC2_DAT0)&0xFFFFFFF8|muxmode; //set as GPIO132 |
|
420 SET_REGISTER(CONTROL_PADCONF_MMC2_DAT0,l); |
|
421 l=GET_REGISTER(CONTROL_PADCONF_MMC2_DAT2)&0xFFFFFFF8|muxmode; //set as GPIO134.135 |
|
422 SET_REGISTER(CONTROL_PADCONF_MMC2_DAT2,l); |
|
423 |
|
424 l=GET_REGISTER(GPIO5_OE)&0xFFFFFF23|n<<4|n<<5;//set GPIO130.131.134.135 as output, 132 as input |
|
425 SET_REGISTER(GPIO5_OE,l); |
|
426 |
|
427 l=GET_REGISTER(CONTROL_PADCONF_DSS_DATA18)&0xFFF8FFF8|muxmode|muxmode<<16; //set as GPIO88,89 |
|
428 SET_REGISTER(CONTROL_PADCONF_DSS_DATA18,l); |
|
429 l=GET_REGISTER(CONTROL_PADCONF_DSS_DATA20)&0xFFF8FFF8|muxmode|muxmode<<16; //set as GPIO90,91 |
|
430 SET_REGISTER(CONTROL_PADCONF_DSS_DATA20,l); |
|
431 l=GET_REGISTER(CONTROL_PADCONF_DSS_DATA22)&0xFFFFFFF8|muxmode|muxmode<<16; //set as GPIO92,93 |
|
432 SET_REGISTER(CONTROL_PADCONF_DSS_DATA22,l); |
|
433 |
|
434 l=GET_REGISTER(GPIO3_OE)&0xC0FFFFFF|n1<<24;//SPI's input and output |
|
435 SET_REGISTER(GPIO3_OE,l); |
|
436 |
|
437 /////////set the init state |
|
438 SET_REGISTER(GPIO5_SETDATAOUT,SPICS0);// |
|
439 SET_REGISTER(GPIO3_CLEARDATAOUT,SPISDAO);// |
|
440 SET_REGISTER(GPIO3_CLEARDATAOUT,SPICLK);// |
|
441 Wait3(1); |
|
442 } |
|
443 void SCLRISING(void) //create a rising edge |
|
444 { |
|
445 SET_REGISTER(GPIO3_SETDATAOUT,SPICLK); |
|
446 Wait3(1); |
|
447 SET_REGISTER(GPIO3_CLEARDATAOUT,SPICLK); |
|
448 //Wait(10); |
|
449 |
|
450 } |
|
451 |
|
452 /** |
|
453 Write_Reg_NT35582() is the function used to initialize LCD with the SPI, it follows the instruction |
|
454 from NT35582 spec page.21 |
|
455 */ |
|
456 void Write_Reg_NT35582(TUint8 highcmd, TUint8 lowcmd, TUint8 lowpara) |
|
457 { |
|
458 int i=0; |
|
459 //Write 1st command |
|
460 SET_REGISTER(GPIO5_CLEARDATAOUT,SPICS0); //set cs0 low |
|
461 //Wait(1); |
|
462 SET_REGISTER(GPIO3_CLEARDATAOUT,SPISDAO); //set R/W=0 |
|
463 Wait3(1); |
|
464 SCLRISING(); |
|
465 SET_REGISTER(GPIO3_CLEARDATAOUT,SPISDAO); //set D/CX=0 |
|
466 Wait3(1); |
|
467 SCLRISING(); |
|
468 SET_REGISTER(GPIO3_SETDATAOUT,SPISDAO); //set H/L=1 |
|
469 Wait3(1); |
|
470 SCLRISING(); |
|
471 for(i=0;i<5;i++) |
|
472 { |
|
473 SET_REGISTER(GPIO3_CLEARDATAOUT,SPISDAO); //set data=0 |
|
474 Wait3(1); |
|
475 SCLRISING(); |
|
476 } |
|
477 for(i=7;i>=0;i--) |
|
478 { |
|
479 if(highcmd>>i&1) |
|
480 { |
|
481 SET_REGISTER(GPIO3_SETDATAOUT,SPISDAO); //set bit=1 |
|
482 Wait3(1); |
|
483 SCLRISING(); |
|
484 } |
|
485 else |
|
486 { |
|
487 SET_REGISTER(GPIO3_CLEARDATAOUT,SPISDAO); //set bit=1 |
|
488 Wait3(1); |
|
489 SCLRISING(); |
|
490 } |
|
491 } |
|
492 SET_REGISTER(GPIO5_SETDATAOUT,SPICS0); //set cs0 high |
|
493 Wait3(1); |
|
494 //Write 2nd command |
|
495 SET_REGISTER(GPIO5_CLEARDATAOUT,SPICS0); //set cs0 low |
|
496 //Wait(1); |
|
497 SET_REGISTER(GPIO3_CLEARDATAOUT,SPISDAO); //set R/W=0 |
|
498 Wait3(1); |
|
499 SCLRISING(); |
|
500 SET_REGISTER(GPIO3_CLEARDATAOUT,SPISDAO); //set D/CX=0 |
|
501 Wait3(1); |
|
502 SCLRISING(); |
|
503 SET_REGISTER(GPIO3_CLEARDATAOUT,SPISDAO); //set H/L=0 |
|
504 Wait3(1); |
|
505 SCLRISING(); |
|
506 for(i=0;i<5;i++) |
|
507 { |
|
508 SET_REGISTER(GPIO3_CLEARDATAOUT,SPISDAO); //set data=0 |
|
509 Wait3(1); |
|
510 SCLRISING(); |
|
511 } |
|
512 for(i=7;i>=0;i--) |
|
513 { |
|
514 if(lowcmd>>i&1) |
|
515 { |
|
516 SET_REGISTER(GPIO3_SETDATAOUT,SPISDAO); //set bit=1 |
|
517 Wait3(1); |
|
518 SCLRISING(); |
|
519 } |
|
520 else |
|
521 { |
|
522 SET_REGISTER(GPIO3_CLEARDATAOUT,SPISDAO); //set bit=1 |
|
523 Wait3(1); |
|
524 SCLRISING(); |
|
525 } |
|
526 } |
|
527 |
|
528 SET_REGISTER(GPIO5_SETDATAOUT,SPICS0); //set cs0 high |
|
529 Wait3(1); |
|
530 //Write parameter |
|
531 SET_REGISTER(GPIO5_CLEARDATAOUT,SPICS0); //set cs0 low |
|
532 //Wait(1); |
|
533 SET_REGISTER(GPIO3_CLEARDATAOUT,SPISDAO); //set R/W=0 |
|
534 Wait3(1); |
|
535 SCLRISING(); |
|
536 SET_REGISTER(GPIO3_SETDATAOUT,SPISDAO); //set D/CX=1 |
|
537 Wait3(1); |
|
538 SCLRISING(); |
|
539 SET_REGISTER(GPIO3_CLEARDATAOUT,SPISDAO); //set H/L=0 |
|
540 Wait3(1); |
|
541 SCLRISING(); |
|
542 for(i=0;i<5;i++) |
|
543 { |
|
544 SET_REGISTER(GPIO3_CLEARDATAOUT,SPISDAO); //set data=0 |
|
545 Wait3(1); |
|
546 SCLRISING(); |
|
547 } |
|
548 for(i=7;i>=0;i--) |
|
549 { |
|
550 if(lowpara>>i&1) |
|
551 { |
|
552 SET_REGISTER(GPIO3_SETDATAOUT,SPISDAO); //set bit=1 |
|
553 Wait3(1); |
|
554 SCLRISING(); |
|
555 } |
|
556 else |
|
557 { |
|
558 SET_REGISTER(GPIO3_CLEARDATAOUT,SPISDAO); //set bit=1 |
|
559 Wait3(1); |
|
560 SCLRISING(); |
|
561 } |
|
562 } |
|
563 SET_REGISTER(GPIO5_SETDATAOUT,SPICS0); //set cs0 high |
|
564 Wait3(1); |
|
565 |
|
566 |
|
567 |
|
568 |
|
569 } |
|
570 void Read_Reg_NT35582(TUint8 highcmd, TUint8 lowcmd) |
|
571 { |
|
572 int i=0; |
|
573 TUint8 lowpara=0; |
|
574 //Write 1st command |
|
575 SET_REGISTER(GPIO5_CLEARDATAOUT,SPICS0); //set cs0 low |
|
576 Wait(1); |
|
577 SET_REGISTER(GPIO3_CLEARDATAOUT,SPISDAO); //set R/W=0 |
|
578 Wait(1); |
|
579 SCLRISING(); |
|
580 SET_REGISTER(GPIO3_CLEARDATAOUT,SPISDAO); //set D/CX=0 |
|
581 Wait(1); |
|
582 SCLRISING(); |
|
583 SET_REGISTER(GPIO3_SETDATAOUT,SPISDAO); //set H/L=1 |
|
584 Wait(1); |
|
585 SCLRISING(); |
|
586 for(i=0;i<5;i++) |
|
587 { |
|
588 SET_REGISTER(GPIO3_CLEARDATAOUT,SPISDAO); //set data=0 |
|
589 Wait(1); |
|
590 SCLRISING(); |
|
591 } |
|
592 for(i=7;i>=0;i--) |
|
593 { |
|
594 if(highcmd>>i&1) |
|
595 { |
|
596 SET_REGISTER(GPIO3_SETDATAOUT,SPISDAO); //set bit=1 |
|
597 Wait(1); |
|
598 SCLRISING(); |
|
599 } |
|
600 else |
|
601 { |
|
602 SET_REGISTER(GPIO3_CLEARDATAOUT,SPISDAO); //set bit=1 |
|
603 Wait(1); |
|
604 SCLRISING(); |
|
605 } |
|
606 } |
|
607 SET_REGISTER(GPIO5_SETDATAOUT,SPICS0); //set cs0 high |
|
608 Wait(1); |
|
609 //Write 2nd command |
|
610 SET_REGISTER(GPIO5_CLEARDATAOUT,SPICS0); //set cs0 low |
|
611 Wait(1); |
|
612 SET_REGISTER(GPIO3_CLEARDATAOUT,SPISDAO); //set R/W=0 |
|
613 Wait(1); |
|
614 SCLRISING(); |
|
615 SET_REGISTER(GPIO3_CLEARDATAOUT,SPISDAO); //set D/CX=0 |
|
616 Wait(1); |
|
617 SCLRISING(); |
|
618 SET_REGISTER(GPIO3_CLEARDATAOUT,SPISDAO); //set H/L=0 |
|
619 Wait(1); |
|
620 SCLRISING(); |
|
621 for(i=0;i<5;i++) |
|
622 { |
|
623 SET_REGISTER(GPIO3_CLEARDATAOUT,SPISDAO); //set data=0 |
|
624 Wait(1); |
|
625 SCLRISING(); |
|
626 } |
|
627 for(i=7;i>=0;i--) |
|
628 { |
|
629 if(lowcmd>>i&1) |
|
630 { |
|
631 SET_REGISTER(GPIO3_SETDATAOUT,SPISDAO); //set bit=1 |
|
632 Wait(1); |
|
633 SCLRISING(); |
|
634 } |
|
635 else |
|
636 { |
|
637 SET_REGISTER(GPIO3_CLEARDATAOUT,SPISDAO); //set bit=1 |
|
638 Wait(1); |
|
639 SCLRISING(); |
|
640 } |
|
641 } |
|
642 |
|
643 SET_REGISTER(GPIO5_SETDATAOUT,SPICS0); //set cs0 high |
|
644 Wait(1); |
|
645 //Read parameter |
|
646 SET_REGISTER(GPIO5_CLEARDATAOUT,SPICS0); //set cs0 low |
|
647 Wait(1); |
|
648 SET_REGISTER(GPIO3_SETDATAOUT,SPISDAO); //set R/W=1 |
|
649 Wait(1); |
|
650 SCLRISING(); |
|
651 SET_REGISTER(GPIO3_SETDATAOUT,SPISDAO); //set D/CX=1 |
|
652 Wait(1); |
|
653 SCLRISING(); |
|
654 SET_REGISTER(GPIO3_CLEARDATAOUT,SPISDAO); //set H/L=0 |
|
655 Wait(1); |
|
656 SCLRISING(); |
|
657 for(i=0;i<5;i++) |
|
658 { |
|
659 SET_REGISTER(GPIO3_CLEARDATAOUT,SPISDAO); //set data=0 |
|
660 Wait(1); |
|
661 SCLRISING(); |
|
662 } |
|
663 for(i=7;i>=0;i--) |
|
664 { |
|
665 SCLRISING(); |
|
666 if(GET_REGISTER(GPIO5_DATADRAIN)&SPISDAI) |
|
667 lowpara|=1<<i; |
|
668 else |
|
669 lowpara|=0<<i; |
|
670 } |
|
671 SET_REGISTER(GPIO5_SETDATAOUT,SPICS0); //set cs0 high |
|
672 Wait(1); |
|
673 Kern::Printf("Get para from Reg %x %x is %x",highcmd,lowcmd,lowpara); |
|
674 |
|
675 |
|
676 |
|
677 } |
|
678 void BYDLCD_INIT(void) |
|
679 { |
|
680 Kern::Printf("Start LCD driver IC NT35582 Init"); |
|
681 SET_GPIOTOSPI(); |
|
682 |
|
683 SET_REGISTER(GPIO3_SETDATAOUT,SPIRESET); |
|
684 Wait(100); |
|
685 SET_REGISTER(GPIO3_CLEARDATAOUT,SPIRESET); |
|
686 Wait(100); |
|
687 SET_REGISTER(GPIO3_SETDATAOUT,SPIRESET); |
|
688 Wait(100); |
|
689 |
|
690 for(int i=0;i<1;i++) |
|
691 { |
|
692 Kern::Printf("init"); |
|
693 Write_Reg_NT35582(0x01,0x00,0x00); |
|
694 //Wait(100); |
|
695 |
|
696 Write_Reg_NT35582(0xC0,0x00,0x86); |
|
697 Write_Reg_NT35582(0xC0,0x01,0x00); |
|
698 Write_Reg_NT35582(0xC0,0x02,0x86); |
|
699 Write_Reg_NT35582(0xC0,0x03,0x00); |
|
700 |
|
701 Write_Reg_NT35582(0xC1,0x00,0x60); |
|
702 |
|
703 Write_Reg_NT35582(0xC2,0x00,0x21); |
|
704 Write_Reg_NT35582(0xC2,0x02,0x70); |
|
705 |
|
706 Write_Reg_NT35582(0xB6,0x00,0x10); |
|
707 Write_Reg_NT35582(0xB6,0x02,0x30); |
|
708 |
|
709 Write_Reg_NT35582(0xC7,0x00,0x8F);// here change the VCOM voltage |
|
710 |
|
711 Write_Reg_NT35582(0x36,0x00,0x41); |
|
712 Write_Reg_NT35582(0x3A,0x00,0x66); |
|
713 |
|
714 Write_Reg_NT35582(0xE0,0x00,0x0E); |
|
715 Write_Reg_NT35582(0xE0,0x01,0x14); |
|
716 Write_Reg_NT35582(0xE0,0x02,0x29); |
|
717 Write_Reg_NT35582(0xE0,0x03,0x3A); |
|
718 Write_Reg_NT35582(0xE0,0x04,0x1D); |
|
719 Write_Reg_NT35582(0xE0,0x05,0x30); |
|
720 Write_Reg_NT35582(0xE0,0x06,0x61); |
|
721 Write_Reg_NT35582(0xE0,0x07,0x3D); |
|
722 Write_Reg_NT35582(0xE0,0x08,0x22); |
|
723 Write_Reg_NT35582(0xE0,0x09,0x2A); |
|
724 Write_Reg_NT35582(0xE0,0x0A,0x87); |
|
725 Write_Reg_NT35582(0xE0,0x0B,0x16); |
|
726 Write_Reg_NT35582(0xE0,0x0C,0x3B); |
|
727 Write_Reg_NT35582(0xE0,0x0D,0x4C); |
|
728 Write_Reg_NT35582(0xE0,0x0E,0x78); |
|
729 Write_Reg_NT35582(0xE0,0x0F,0x96); |
|
730 Write_Reg_NT35582(0xE0,0x10,0x4A); |
|
731 Write_Reg_NT35582(0xE0,0x11,0x4D); |
|
732 |
|
733 Write_Reg_NT35582(0xE1,0x00,0x0E); |
|
734 Write_Reg_NT35582(0xE1,0x01,0x14); |
|
735 Write_Reg_NT35582(0xE1,0x02,0x29); |
|
736 Write_Reg_NT35582(0xE1,0x03,0x3A); |
|
737 Write_Reg_NT35582(0xE1,0x04,0x1D); |
|
738 Write_Reg_NT35582(0xE1,0x05,0x30); |
|
739 Write_Reg_NT35582(0xE1,0x06,0x61); |
|
740 Write_Reg_NT35582(0xE1,0x07,0x3F); |
|
741 Write_Reg_NT35582(0xE1,0x08,0x20); |
|
742 Write_Reg_NT35582(0xE1,0x09,0x26); |
|
743 Write_Reg_NT35582(0xE1,0x0A,0x83); |
|
744 Write_Reg_NT35582(0xE1,0x0B,0x16); |
|
745 Write_Reg_NT35582(0xE1,0x0C,0x3B); |
|
746 Write_Reg_NT35582(0xE1,0x0D,0x4C); |
|
747 Write_Reg_NT35582(0xE1,0x0E,0x78); |
|
748 Write_Reg_NT35582(0xE1,0x0F,0x96); |
|
749 Write_Reg_NT35582(0xE1,0x10,0x4A); |
|
750 Write_Reg_NT35582(0xE1,0x11,0x4D); |
|
751 |
|
752 Write_Reg_NT35582(0xE2,0x00,0x0E); |
|
753 Write_Reg_NT35582(0xE2,0x01,0x14); |
|
754 Write_Reg_NT35582(0xE2,0x02,0x29); |
|
755 Write_Reg_NT35582(0xE2,0x03,0x3A); |
|
756 Write_Reg_NT35582(0xE2,0x04,0x1D); |
|
757 Write_Reg_NT35582(0xE2,0x05,0x30); |
|
758 Write_Reg_NT35582(0xE2,0x06,0x61); |
|
759 Write_Reg_NT35582(0xE2,0x07,0x3D); |
|
760 Write_Reg_NT35582(0xE2,0x08,0x22); |
|
761 Write_Reg_NT35582(0xE2,0x09,0x2A); |
|
762 Write_Reg_NT35582(0xE2,0x0A,0x87); |
|
763 Write_Reg_NT35582(0xE2,0x0B,0x16); |
|
764 Write_Reg_NT35582(0xE2,0x0C,0x3B); |
|
765 Write_Reg_NT35582(0xE2,0x0D,0x4C); |
|
766 Write_Reg_NT35582(0xE2,0x0E,0x78); |
|
767 Write_Reg_NT35582(0xE2,0x0F,0x96); |
|
768 Write_Reg_NT35582(0xE2,0x10,0x4A); |
|
769 Write_Reg_NT35582(0xE2,0x11,0x4D); |
|
770 |
|
771 Write_Reg_NT35582(0xE3,0x00,0x0E); |
|
772 Write_Reg_NT35582(0xE3,0x01,0x14); |
|
773 Write_Reg_NT35582(0xE3,0x02,0x29); |
|
774 Write_Reg_NT35582(0xE3,0x03,0x3A); |
|
775 Write_Reg_NT35582(0xE3,0x04,0x1D); |
|
776 Write_Reg_NT35582(0xE3,0x05,0x30); |
|
777 Write_Reg_NT35582(0xE3,0x06,0x61); |
|
778 Write_Reg_NT35582(0xE3,0x07,0x3F); |
|
779 Write_Reg_NT35582(0xE3,0x08,0x20); |
|
780 Write_Reg_NT35582(0xE3,0x09,0x26); |
|
781 Write_Reg_NT35582(0xE3,0x0A,0x83); |
|
782 Write_Reg_NT35582(0xE3,0x0B,0x16); |
|
783 Write_Reg_NT35582(0xE3,0x0C,0x3B); |
|
784 Write_Reg_NT35582(0xE3,0x0D,0x4C); |
|
785 Write_Reg_NT35582(0xE3,0x0E,0x78); |
|
786 Write_Reg_NT35582(0xE3,0x0F,0x96); |
|
787 Write_Reg_NT35582(0xE3,0x10,0x4A); |
|
788 Write_Reg_NT35582(0xE3,0x11,0x4D); |
|
789 |
|
790 Write_Reg_NT35582(0xE4,0x00,0x0E); |
|
791 Write_Reg_NT35582(0xE4,0x01,0x14); |
|
792 Write_Reg_NT35582(0xE4,0x02,0x29); |
|
793 Write_Reg_NT35582(0xE4,0x03,0x3A); |
|
794 Write_Reg_NT35582(0xE4,0x04,0x1D); |
|
795 Write_Reg_NT35582(0xE4,0x05,0x30); |
|
796 Write_Reg_NT35582(0xE4,0x06,0x61); |
|
797 Write_Reg_NT35582(0xE4,0x07,0x3D); |
|
798 Write_Reg_NT35582(0xE4,0x08,0x22); |
|
799 Write_Reg_NT35582(0xE4,0x09,0x2A); |
|
800 Write_Reg_NT35582(0xE4,0x0A,0x87); |
|
801 Write_Reg_NT35582(0xE4,0x0B,0x16); |
|
802 Write_Reg_NT35582(0xE4,0x0C,0x3B); |
|
803 Write_Reg_NT35582(0xE4,0x0D,0x4C); |
|
804 Write_Reg_NT35582(0xE4,0x0E,0x78); |
|
805 Write_Reg_NT35582(0xE4,0x0F,0x96); |
|
806 Write_Reg_NT35582(0xE4,0x10,0x4A); |
|
807 Write_Reg_NT35582(0xE4,0x11,0x4D); |
|
808 |
|
809 Write_Reg_NT35582(0xE5,0x00,0x0E); |
|
810 Write_Reg_NT35582(0xE5,0x01,0x14); |
|
811 Write_Reg_NT35582(0xE5,0x02,0x29); |
|
812 Write_Reg_NT35582(0xE5,0x03,0x3A); |
|
813 Write_Reg_NT35582(0xE5,0x04,0x1D); |
|
814 Write_Reg_NT35582(0xE5,0x05,0x30); |
|
815 Write_Reg_NT35582(0xE5,0x06,0x61); |
|
816 Write_Reg_NT35582(0xE5,0x07,0x3F); |
|
817 Write_Reg_NT35582(0xE5,0x08,0x20); |
|
818 Write_Reg_NT35582(0xE5,0x09,0x26); |
|
819 Write_Reg_NT35582(0xE5,0x0A,0x83); |
|
820 Write_Reg_NT35582(0xE5,0x0B,0x16); |
|
821 Write_Reg_NT35582(0xE5,0x0C,0x3B); |
|
822 Write_Reg_NT35582(0xE5,0x0D,0x4C); |
|
823 Write_Reg_NT35582(0xE5,0x0E,0x78); |
|
824 Write_Reg_NT35582(0xE5,0x0F,0x96); |
|
825 Write_Reg_NT35582(0xE5,0x10,0x4A); |
|
826 Write_Reg_NT35582(0xE5,0x11,0x4D); |
|
827 |
|
828 |
|
829 Write_Reg_NT35582(0x11,0x00,0x00); |
|
830 Wait(150); |
|
831 Write_Reg_NT35582(0x29,0x00,0x00); |
|
832 Wait(100); |
|
833 } |
|
834 //Kern::Printf("SW RESET"); |
|
835 //Write_Reg_NT35582a(0x01,0x00,0x00); |
|
836 //Wait(2000); |
|
837 |
|
838 //Kern::Printf("SLP Out"); |
|
839 //Write_Reg_NT35582a(0x11,0x00,0x00); |
|
840 //Wait(2000); |
|
841 //Kern::Printf("DISPON"); |
|
842 //Write_Reg_NT35582a(0x29,0x00,0x00); |
|
843 //Wait(2000); |
|
844 |
|
845 Kern::Printf("END driver IC NT35582 Init"); |
|
846 //Wait(2000); |
|
847 } |
|
324 |
848 |
325 /** |
849 /** |
326 Default constructor |
850 Default constructor |
327 */ |
851 */ |
328 DLcdPowerHandler::DLcdPowerHandler() : |
852 DLcdPowerHandler::DLcdPowerHandler() : |
342 |
866 |
343 Called by factory function at ordinal 0 |
867 Called by factory function at ordinal 0 |
344 */ |
868 */ |
345 TInt DLcdPowerHandler::Create() |
869 TInt DLcdPowerHandler::Create() |
346 { |
870 { |
871 BYDLCD_INIT(); |
|
872 Wait2(1000); |
|
873 |
|
347 #ifdef ENABLE_GCE_MODE |
874 #ifdef ENABLE_GCE_MODE |
348 pLcd = this; |
875 pLcd = this; |
349 #endif |
876 #endif |
350 |
|
351 iDfcQ=Kern::DfcQue0(); // use low priority DFC queue for this driver |
877 iDfcQ=Kern::DfcQue0(); // use low priority DFC queue for this driver |
352 |
878 |
353 // map the video RAM |
879 // map the video RAM |
354 |
880 |
355 //TPhysAddr videoRamPhys; |
881 //TPhysAddr videoRamPhys; |
588 l = LOADMOAD<<1; |
1114 l = LOADMOAD<<1; |
589 SET_REGISTER( DISPC_CONFIG, l ); |
1115 SET_REGISTER( DISPC_CONFIG, l ); |
590 |
1116 |
591 SET_REGISTER( DISPC_DEFAULT_COLOR0, 0xFFFFFFFF ); |
1117 SET_REGISTER( DISPC_DEFAULT_COLOR0, 0xFFFFFFFF ); |
592 SET_REGISTER( DISPC_TRANS_COLOR0, 0x00000000 ); |
1118 SET_REGISTER( DISPC_TRANS_COLOR0, 0x00000000 ); |
1119 TUint16 LINENUMBER=799; |
|
1120 l=LINENUMBER; |
|
1121 SET_REGISTER(DISPC_LINE_STATUS, l); |
|
593 |
1122 |
594 TUint8 hbp = H_BPORCH - 1; // Horizontal Back Porch |
1123 TUint8 hbp = H_BPORCH - 1; // Horizontal Back Porch |
595 TUint8 hfp = H_FPORCH - 1; // Horizontal front porch |
1124 TUint8 hfp = H_FPORCH - 1; // Horizontal front porch |
596 TUint8 hsw = H_SYNC - 1; // Horizontal synchronization pulse width |
1125 TUint8 hsw = H_SYNC - 1; // Horizontal synchronization pulse width |
597 if ( hsw > 63 ) |
1126 if ( hsw > 63 ) |
600 Kern::Printf("[LCD] H_SYNC too big"); |
1129 Kern::Printf("[LCD] H_SYNC too big"); |
601 } |
1130 } |
602 l = hbp<<20 | hfp<<8 | hsw; |
1131 l = hbp<<20 | hfp<<8 | hsw; |
603 SET_REGISTER( DISPC_TIMING_H, l ); |
1132 SET_REGISTER( DISPC_TIMING_H, l ); |
604 |
1133 |
605 TUint8 vbp = V_BPORCH; // Vertical back porch |
1134 TUint16 vbp = V_BPORCH; // Vertical back porch |
606 TUint8 vfp = V_FPORCH; // Vertical front porch |
1135 TUint16 vfp = V_FPORCH; // Vertical front porch |
607 TUint8 vsw = V_SYNC; // Vertical synchronization pulse width |
1136 TUint8 vsw = V_SYNC; // Vertical synchronization pulse width |
608 __ASSERT_ALWAYS( vbp<=255, Kern::Fault("LCD", 1) ); |
1137 // __ASSERT_ALWAYS( vbp<=255, Kern::Fault("LCD", 1) ); |
609 __ASSERT_ALWAYS( vfp<=255, Kern::Fault("LCD", 1) ); |
1138 // __ASSERT_ALWAYS( vfp<=255, Kern::Fault("LCD", 1) ); |
610 __ASSERT_ALWAYS( vsw>=1 && vsw<=255, Kern::Fault("LCD", 1) ); |
1139 __ASSERT_ALWAYS( vsw>=1 && vsw<=255, Kern::Fault("LCD", 1) ); |
611 l = vbp<<20 | vfp<<8 | vsw; |
1140 l = vbp<<20 | vfp<<8 | vsw; |
612 SET_REGISTER( DISPC_TIMING_V, l ); |
1141 SET_REGISTER( DISPC_TIMING_V, l ); |
613 |
1142 |
614 TUint8 onoff= 0; |
1143 TUint8 onoff= 0; |
615 TUint8 rf = 0; |
1144 TUint8 rf = 0; |
616 TUint8 ieo = 0; |
1145 TUint8 ieo = 0; |
617 TUint8 ipc = 1; // Invert Pixel Clock |
1146 TUint8 ipc = 0; // Invert Pixel Clock |
618 TUint8 ihs = H_SYNC_POL ? 0 : 1; // Invert HSYNC (0: Positive Sync polarity, 1: Negative Sync polarity) |
1147 TUint8 ihs = H_SYNC_POL ;//? 0 : 1; // Invert HSYNC (0: Positive Sync polarity, 1: Negative Sync polarity) |
619 TUint8 ivs = V_SYNC_POL ? 0 : 1; // Invert VSYNC (0: Positive Sync polarity, 1: Negative Sync polarity) |
1148 TUint8 ivs = V_SYNC_POL ;//? 0 : 1; // Invert VSYNC (0: Positive Sync polarity, 1: Negative Sync polarity) |
620 TUint8 acbi = 0; |
1149 TUint8 acbi = 0; |
621 TUint16 acb = 0x28; // AC-bias pin frequency |
1150 TUint8 acb = 0x28; // AC-bias pin frequency |
622 l = onoff<<17 | rf<<16 | ieo<<15 | ipc<<14 | ihs<<13 | ivs<<12 | acbi<<8 | acb; |
1151 l = onoff<<17 | rf<<16 | ieo<<15 | ipc<<14 | ihs<<13 | ivs<<12 | acbi<<8 | acb; |
623 SET_REGISTER( DISPC_POL_FREQ, l ); |
1152 SET_REGISTER( DISPC_POL_FREQ, l ); |
624 |
1153 |
625 TUint8 lcd = 1; // Display Controller Logic Clock Divisor |
1154 TUint8 lcd = 1; // Display Controller Logic Clock Divisor |
626 TUint8 pcd = ( 432000 + (PIXEL_CLK - 1) ) / PIXEL_CLK; // Pixel Clock Divisor - add (PIXEL_CLK - 1) to avoid rounding error |
1155 TUint8 pcd = ( 432000 + (PIXEL_CLK - 1) ) / PIXEL_CLK; // Pixel Clock Divisor - add (PIXEL_CLK - 1) to avoid rounding error |
654 l = gfxsizey<<16 | gfxsizex; |
1183 l = gfxsizey<<16 | gfxsizex; |
655 SET_REGISTER( DISPC_GFX_SIZE, l ); |
1184 SET_REGISTER( DISPC_GFX_SIZE, l ); |
656 |
1185 |
657 TInt8 GFXSELFREFRESH = 0x0; |
1186 TInt8 GFXSELFREFRESH = 0x0; |
658 TInt8 GFXARBITRATION = 0x0; |
1187 TInt8 GFXARBITRATION = 0x0; |
659 TInt8 GFXROTATION = 0x0; |
1188 TInt8 GFXROTATION = 0x2; |
660 TInt8 GFXFIFOPRELOAD = 0x0; |
1189 TInt8 GFXFIFOPRELOAD = 0x0; |
661 TInt8 GFXENDIANNESS = 0x0; |
1190 TInt8 GFXENDIANNESS = 0x0; |
662 TInt8 GFXNIBBLEMODE = 0x0; |
1191 TInt8 GFXNIBBLEMODE = 0x0; |
663 TInt8 GFXCHANNELOUT = 0x0; |
1192 TInt8 GFXCHANNELOUT = 0x0; |
664 TInt8 GFXBURSTSIZE = 0x2; // 16x32bit bursts |
1193 TInt8 GFXBURSTSIZE = 0x2; // 16x32bit bursts |
665 TInt8 GFXREPLICATIONENABLE = 0x0; // Disable Graphics replication logic |
1194 TInt8 GFXREPLICATIONENABLE = 0x0; // Disable Graphics replication logic |
666 TInt8 GFXFORMAT = 0x8;//0x6; // RGB16=0x6, RGB24-unpacked=0x8, RGB24-packed=0x9 |
1195 TInt8 GFXFORMAT = 0x8;//0x6;//0x6; // RGB16=0x6, RGB24-unpacked=0x8, RGB24-packed=0x9 |
667 TInt8 GFXENABLE = 0x1; // Graphics enabled |
1196 TInt8 GFXENABLE = 0x1; // Graphics enabled |
668 l = GFXSELFREFRESH<<15 | GFXARBITRATION<<14 | GFXROTATION<<12 | GFXFIFOPRELOAD<<11 | GFXENDIANNESS<<10 | GFXNIBBLEMODE<<9 | GFXCHANNELOUT<8 | GFXBURSTSIZE<<6 | GFXREPLICATIONENABLE<<5 | GFXFORMAT<<1 | GFXENABLE; |
1197 l = GFXSELFREFRESH<<15 | GFXARBITRATION<<14 | GFXROTATION<<12 | GFXFIFOPRELOAD<<11 | GFXENDIANNESS<<10 | GFXNIBBLEMODE<<9 | GFXCHANNELOUT<8 | GFXBURSTSIZE<<6 | GFXREPLICATIONENABLE<<5 | GFXFORMAT<<1 | GFXENABLE; |
669 SET_REGISTER( DISPC_GFX_ATTRIBUTES, l ); |
1198 SET_REGISTER( DISPC_GFX_ATTRIBUTES, l ); |
670 |
1199 |
671 TInt16 GFXFIFOHIGHTHRESHOLD = 0x3fc; // Graphics FIFO High Threshold |
1200 TInt16 GFXFIFOHIGHTHRESHOLD = 0x3fc; // Graphics FIFO High Threshold |
697 |
1226 |
698 // Propigate all the shadowed registers |
1227 // Propigate all the shadowed registers |
699 |
1228 |
700 TInt8 SPATIALTEMPORALDITHERINGFRAMES = 0; |
1229 TInt8 SPATIALTEMPORALDITHERINGFRAMES = 0; |
701 TInt8 LCDENABLEPOL = 0; |
1230 TInt8 LCDENABLEPOL = 0; |
702 TInt8 LCDENABLESIGNAL = 0; |
1231 TInt8 LCDENABLESIGNAL = 1; |
703 TInt8 PCKFREEENABLE = 0; |
1232 TInt8 PCKFREEENABLE = 0; |
704 TInt8 TDMUNUSEDBITS = 0; |
1233 TInt8 TDMUNUSEDBITS = 0; |
705 TInt8 TDMCYCLEFORMAT = 0; |
1234 TInt8 TDMCYCLEFORMAT = 0; |
706 TInt8 TDMPARALLELMODE = 0; |
1235 TInt8 TDMPARALLELMODE = 0; |
707 TInt8 TDMENABLE = 0; |
1236 TInt8 TDMENABLE = 0; |
711 TInt8 GPIN1 = 0; |
1240 TInt8 GPIN1 = 0; |
712 TInt8 GPIN0 = 0; |
1241 TInt8 GPIN0 = 0; |
713 TInt8 OVERLAYOPTIMIZATION = 0; |
1242 TInt8 OVERLAYOPTIMIZATION = 0; |
714 TInt8 RFBIMODE = 0; |
1243 TInt8 RFBIMODE = 0; |
715 TInt8 SECURE = 0; |
1244 TInt8 SECURE = 0; |
716 TInt8 TFTDATALINES = 0x3; |
1245 TInt8 TFTDATALINES = 0x2;//0x3;//0x2; |
717 TInt8 STDITHERENABLE = 0; |
1246 TInt8 STDITHERENABLE = 0; |
718 TInt8 GODIGITAL = 1; |
1247 TInt8 GODIGITAL = 0; |
719 TInt8 GOLCD = 1; |
1248 TInt8 GOLCD = 1; |
720 TInt8 M8B = 0; |
1249 TInt8 M8B = 0; |
721 TInt8 STNTFT = 1; |
1250 TInt8 STNTFT = 1; |
722 TInt8 MONOCOLOR = 0; |
1251 TInt8 MONOCOLOR = 0; |
723 TInt8 DIGITALENABLE = 1; |
1252 TInt8 DIGITALENABLE = 0; |
724 TInt8 LCDENABLE = 1; |
1253 TInt8 LCDENABLE = 1; |
725 l = SPATIALTEMPORALDITHERINGFRAMES<<30 | LCDENABLEPOL<<29 | LCDENABLESIGNAL<<28 | PCKFREEENABLE<<27 | |
1254 l = SPATIALTEMPORALDITHERINGFRAMES<<30 | LCDENABLEPOL<<29 | LCDENABLESIGNAL<<28 | PCKFREEENABLE<<27 | |
726 TDMUNUSEDBITS<<25 | TDMCYCLEFORMAT<<23 | TDMPARALLELMODE<<21 | TDMENABLE<<20 | HT<<17 | GPOUT1<<16 | |
1255 TDMUNUSEDBITS<<25 | TDMCYCLEFORMAT<<23 | TDMPARALLELMODE<<21 | TDMENABLE<<20 | HT<<17 | GPOUT1<<16 | |
727 GPOUT0<<15 | GPIN1<<14 | GPIN0<<13 | OVERLAYOPTIMIZATION<<12 | RFBIMODE<<11 | SECURE<<10 | |
1256 GPOUT0<<15 | GPIN1<<14 | GPIN0<<13 | OVERLAYOPTIMIZATION<<12 | RFBIMODE<<11 | SECURE<<10 | |
728 TFTDATALINES<<8 | STDITHERENABLE<<7 | GODIGITAL<<6 | GOLCD<<5 | M8B<<4 | STNTFT<<3 | |
1257 TFTDATALINES<<8 | STDITHERENABLE<<7 | GODIGITAL<<6 | GOLCD<<5 | M8B<<4 | STNTFT<<3 | |
930 TInt DLcdPowerHandler::SetDisplayMode(TInt aMode) |
1459 TInt DLcdPowerHandler::SetDisplayMode(TInt aMode) |
931 { |
1460 { |
932 |
1461 |
933 __KTRACE_OPT(KEXTENSION,Kern::Printf("SetDisplayMode = %d", aMode)); |
1462 __KTRACE_OPT(KEXTENSION,Kern::Printf("SetDisplayMode = %d", aMode)); |
934 |
1463 |
1464 Kern::Printf("SetDisplayMode = %d", aMode); |
|
935 if (aMode < 0 || aMode >= KConfigLcdNumberOfDisplayModes) |
1465 if (aMode < 0 || aMode >= KConfigLcdNumberOfDisplayModes) |
936 return KErrArgument; |
1466 return KErrArgument; |
937 |
1467 |
938 NKern::FMWait(&iLock); |
1468 NKern::FMWait(&iLock); |
939 |
1469 |
957 // |
1487 // |
958 NKern::FMSignal(&iLock); |
1488 NKern::FMSignal(&iLock); |
959 |
1489 |
960 __KTRACE_OPT(KEXTENSION,Kern::Printf("SetDisplayMode mode = %d, otfp = %d, palettized = %d, bpp = %d, obl = %d", |
1490 __KTRACE_OPT(KEXTENSION,Kern::Printf("SetDisplayMode mode = %d, otfp = %d, palettized = %d, bpp = %d, obl = %d", |
961 aMode, iVideoInfo.iOffsetToFirstPixel, iVideoInfo.iIsPalettized, iVideoInfo.iBitsPerPixel, iVideoInfo.iOffsetBetweenLines)); |
1491 aMode, iVideoInfo.iOffsetToFirstPixel, iVideoInfo.iIsPalettized, iVideoInfo.iBitsPerPixel, iVideoInfo.iOffsetBetweenLines)); |
962 |
1492 Kern::Printf("SetDisplayMode mode = %d, otfp = %d, palettized = %d, bpp = %d, obl = %d", |
1493 aMode, iVideoInfo.iOffsetToFirstPixel, iVideoInfo.iIsPalettized, iVideoInfo.iBitsPerPixel, iVideoInfo.iOffsetBetweenLines); |
|
963 return KErrNone; |
1494 return KErrNone; |
964 } |
1495 } |
965 |
1496 |
966 /** |
1497 /** |
967 Fill the video memory with an initial pattern or image |
1498 Fill the video memory with an initial pattern or image |