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1 // Copyright (c) 1994-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // omap3530/beagle_drivers/wb/cyashalbeagleboard_spi.cpp |
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15 // |
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16 |
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17 #include <kern_priv.h> |
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18 #include <beagle/beagle_gpio.h> |
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19 #include <beagle/variant.h> |
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20 #include <assp/omap3530_assp/omap3530_assp_priv.h> |
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21 #include <assp/omap3530_assp/omap3530_irqmap.h> // GPIO interrupts |
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22 #include <assp/omap3530_assp/omap3530_gpio.h> |
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23 |
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24 #include <assp.h> // Required for definition of TIsr |
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25 |
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26 #include <cyasregs.h> // Astoria register definitions |
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27 #include <cyashalbeagleboard_spi.h> |
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28 #include <cyashalbeagleboard.h> |
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29 |
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30 int gConfigured = 0 ; |
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31 |
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32 /***********************************************************************/ |
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33 /******************************* ISR **********************************/ |
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34 /***********************************************************************/ |
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35 |
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36 int |
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37 CyAsHalBeagleBoard__SetupISR(void* handler, void* ptr) |
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38 { |
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39 |
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40 //Set up the button to proivde a panic button invoking Fault() |
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41 if(KErrNone != GPIO::SetPinDirection(KGPIO_INT, GPIO::EInput)) |
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42 return KErrArgument; |
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43 |
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44 GPIO::SetPinMode(KGPIO_INT, GPIO::EEnabled); |
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45 |
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46 if(KErrNone !=GPIO::BindInterrupt(KGPIO_INT, (TGpioIsr)handler, (TAny*)ptr)) |
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47 return KErrArgument; |
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48 |
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49 /*EEdgeFalling*/ |
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50 if(KErrNone !=GPIO::SetInterruptTrigger(KGPIO_INT, GPIO::ELevelLow)) |
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51 return KErrArgument; |
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52 |
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53 if(KErrNone !=GPIO::EnableInterrupt(KGPIO_INT)) |
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54 { |
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55 GPIO::UnbindInterrupt(KGPIO_INT); |
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56 return KErrInUse; |
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57 } |
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58 return 0 ; |
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59 } |
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60 |
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61 static void |
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62 ManualTriggerISRTest(void) |
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63 { |
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64 GPIO::TGpioState intState = GPIO::EHigh ; |
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65 |
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66 GPIO::GetInputState(KGPIO_INT, intState); |
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67 Kern::Printf("KGPIO_INT before INT is %d", intState); |
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68 |
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69 //Set INT to LOW state |
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70 CyAsHalBeagleBoardMcSPI4Ch0_WriteReg(CY_AS_MEM_P0_VM_SET, 0x0545) ; |
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71 GPIO::GetInputState(KGPIO_INT, intState); |
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72 Kern::Printf("KGPIO_INT after INT is %d", intState); |
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73 |
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74 //return INT to HIGH state |
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75 CyAsHalBeagleBoardMcSPI4Ch0_WriteReg(CY_AS_MEM_P0_VM_SET, 0x0745) ; |
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76 GPIO::GetInputState(KGPIO_INT, intState); |
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77 Kern::Printf("KGPIO_INT after INT is %d", intState); |
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78 } |
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79 |
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80 TUint32 gISRCnt = 1 ; |
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81 TDfc* gpMyDfc; |
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82 |
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83 static void myTestDFCFn( |
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84 TAny *aPtr) |
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85 { |
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86 |
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87 TUint32* gpISRCnt = (TUint32*)aPtr ; |
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88 Kern::Printf("myTestDFCFn called (%d)",*gpISRCnt); |
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89 |
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90 *gpISRCnt += 1; |
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91 |
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92 Kern::Printf("Enable interrupt"); |
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93 GPIO::EnableInterrupt(KGPIO_INT) ; |
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94 } |
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95 |
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96 static void myISR(TAny* aPtr) |
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97 { |
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98 Kern::Printf("AstoriaISR"); |
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99 gpMyDfc->Add(); |
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100 |
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101 Kern::Printf("Disable interrupt"); |
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102 /* Disable Interrupt Here, it will be re-enabled by DFCs |
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103 GPIO::DisableInterrupt(KGPIO_INT) ;*/ |
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104 } |
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105 |
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106 /***********************************************************************/ |
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107 /**************************** SPI Driver *******************************/ |
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108 /***********************************************************************/ |
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109 |
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110 extern void |
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111 McSPI4Ch0_SetXFERLEVEL(TUint16 wcnt, TUint8 afl, TUint8 ael) |
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112 { |
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113 TUint32 r = wcnt ; |
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114 |
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115 r <<= 16 ; |
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116 r |= (afl & 0x3f) << 8 ; |
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117 r |= (ael & 0x3f) ; |
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118 |
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119 AsspRegister::Write32(KMcSPI4_XFERLEVEL, r); |
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120 } |
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121 |
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122 inline void McSPI4Ch0_Enable(void) |
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123 { |
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124 /* Enable channel 0 */ |
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125 AsspRegister::Write32(KMcSPI4_CH0CTRL, 0x1); |
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126 } |
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127 |
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128 inline void McSPI4Ch0_Disable(void) |
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129 { |
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130 /* Disable channel 0 */ |
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131 AsspRegister::Write32(KMcSPI4_CH0CTRL, 0x0); |
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132 } |
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133 |
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134 inline void McSPI4Ch0_TransmitMode(void) |
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135 { |
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136 AsspRegister::Modify32(KMcSPI4_CH0CONF, 0x0, 0x1<<13); |
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137 } |
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138 |
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139 inline void McSPI4Ch0_TransmitAndReceiveMode(void) |
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140 { |
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141 AsspRegister::Modify32(KMcSPI4_CH0CONF, 0x1<<13, 0x0); |
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142 } |
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143 |
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144 extern |
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145 void McSPI4Ch0_SyncSlave(void) |
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146 { |
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147 Kern::Printf("Sync With SPI slave not implemented\n"); |
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148 } |
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149 |
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150 inline void CheckForTxEmpty(void) |
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151 { |
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152 TUint32 r ; |
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153 for(;;) |
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154 { |
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155 r = AsspRegister::Read32(KMcSPI4_CH0STAT); |
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156 if ( r & 0x2) |
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157 { |
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158 break; |
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159 } |
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160 Kern::Printf("Waiting for TX empty."); |
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161 } |
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162 } |
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163 |
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164 inline void CheckForRxFull(void) |
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165 { |
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166 TUint32 r ; |
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167 for(;;) |
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168 { |
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169 r = AsspRegister::Read32(KMcSPI4_CH0STAT); |
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170 if ( r & 0x1) |
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171 { |
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172 break; |
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173 } |
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174 Kern::Printf("Waiting for RX full."); |
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175 } |
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176 } |
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177 |
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178 inline void CheckForTxEmptyRxFull(void) |
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179 { |
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180 TUint32 r ; |
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181 for(;;) |
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182 { |
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183 r = AsspRegister::Read32(KMcSPI4_CH0STAT); |
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184 if ( r & 0x3) |
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185 { |
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186 break; |
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187 } |
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188 Kern::Printf("Waiting for TX empty and RX full."); |
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189 } |
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190 } |
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191 |
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192 extern void |
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193 McSPI4Ch0_DumpAstoriaRegs(int allReg) |
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194 { |
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195 int i ; |
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196 TUint16 regVal = 0 ; |
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197 |
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198 for ( i = 0x80 ; i < 0xfb ; i++ ) |
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199 { |
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200 if ( (i == 0x84) || |
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201 ((i >= 0x87) && (i <= 0x8f)) || |
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202 (i == 0x93) || |
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203 ((i >= 0x96) && (i <= 0x97)) || |
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204 (i == 0x99) || |
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205 ((i >= 0x9b) && (i <= 0x9f)) || |
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206 ((i >= 0xb0) && (i <= 0xbf)) || |
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207 ((i >= 0xc6) && (i <= 0xd8)) || |
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208 ((i >= 0xe3) && (i <= 0xef)) || |
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209 ((i >= 0xf4) && (i <= 0xf7)) ) |
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210 { |
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211 /*skip*/ |
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212 continue ; |
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213 } |
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214 |
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215 regVal = 0 ; |
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216 if ( allReg ) |
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217 CyAsHalBeagleBoardMcSPI4Ch0_ReadReg(i, ®Val) ; |
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218 else |
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219 CyAsHalBeagleBoardMcSPI4Ch0_ReadReg(CY_AS_MEM_CM_WB_CFG_ID, ®Val) ; |
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220 Kern::Printf("REG[%02x] = 0x%04x", i, regVal); |
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221 } |
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222 } |
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223 |
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224 static int |
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225 AstoriaRegTest(int type) |
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226 { |
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227 int errCnt = 0 ; |
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228 int i ; |
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229 for ( i= 0 ; i < 100 ; i++ ) |
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230 { |
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231 TUint16 regVal0 = 0, regVal1 = 0, regVal2 = 0, regVal3 = 0 ; |
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232 TUint16 expVal = 0 ; |
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233 |
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234 if ( type == 1 ) |
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235 { |
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236 Kern::Printf("Write/Read Register with sequential value..."); |
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237 CyAsHalBeagleBoardMcSPI4Ch0_WriteReg(0xf8, (i+1)) ; |
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238 CyAsHalBeagleBoardMcSPI4Ch0_WriteReg(0xf9, (i+2)) ; |
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239 CyAsHalBeagleBoardMcSPI4Ch0_WriteReg(0xfa, (i+3)) ; |
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240 CyAsHalBeagleBoardMcSPI4Ch0_WriteReg(0xfb, (i+4)) ; |
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241 } |
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242 else if ( type == 2 ) |
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243 { |
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244 Kern::Printf("Write/Read 0xffff and 0x0 ..."); |
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245 if ( i % 2 == 0 ) |
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246 { |
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247 expVal = 0xffff ; |
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248 CyAsHalBeagleBoardMcSPI4Ch0_WriteReg(0xf8, expVal) ; |
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249 CyAsHalBeagleBoardMcSPI4Ch0_WriteReg(0xf9, ~expVal) ; |
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250 CyAsHalBeagleBoardMcSPI4Ch0_WriteReg(0xfa, expVal) ; |
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251 CyAsHalBeagleBoardMcSPI4Ch0_WriteReg(0xfb, ~expVal) ; |
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252 |
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253 } |
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254 else |
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255 { |
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256 expVal = 0x0 ; |
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257 CyAsHalBeagleBoardMcSPI4Ch0_WriteReg(0xf8, expVal) ; |
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258 CyAsHalBeagleBoardMcSPI4Ch0_WriteReg(0xf9, ~expVal) ; |
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259 CyAsHalBeagleBoardMcSPI4Ch0_WriteReg(0xfa, expVal) ; |
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260 CyAsHalBeagleBoardMcSPI4Ch0_WriteReg(0xfb, ~expVal) ; |
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261 } |
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262 } |
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263 else if ( type == 3 ) |
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264 { |
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265 Kern::Printf("Write/Read 0x5555 and 0xaaaa ..."); |
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266 if ( i % 2 == 0 ) |
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267 { |
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268 expVal = 0x5555 ; |
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269 CyAsHalBeagleBoardMcSPI4Ch0_WriteReg(0xf8, expVal) ; |
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270 CyAsHalBeagleBoardMcSPI4Ch0_WriteReg(0xf9, ~expVal) ; |
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271 CyAsHalBeagleBoardMcSPI4Ch0_WriteReg(0xfa, expVal) ; |
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272 CyAsHalBeagleBoardMcSPI4Ch0_WriteReg(0xfb, ~expVal) ; |
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273 } |
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274 else |
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275 { |
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276 expVal = 0xaaaa ; |
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277 CyAsHalBeagleBoardMcSPI4Ch0_WriteReg(0xf8, expVal) ; |
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278 CyAsHalBeagleBoardMcSPI4Ch0_WriteReg(0xf9, ~expVal) ; |
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279 CyAsHalBeagleBoardMcSPI4Ch0_WriteReg(0xfa, expVal) ; |
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280 CyAsHalBeagleBoardMcSPI4Ch0_WriteReg(0xfb, ~expVal) ; |
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281 } |
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282 } |
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283 |
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284 CyAsHalBeagleBoardMcSPI4Ch0_ReadReg(0xf8, ®Val0) ; |
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285 CyAsHalBeagleBoardMcSPI4Ch0_ReadReg(0xf9, ®Val1) ; |
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286 CyAsHalBeagleBoardMcSPI4Ch0_ReadReg(0xfa, ®Val2) ; |
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287 CyAsHalBeagleBoardMcSPI4Ch0_ReadReg(0xfb, ®Val3) ; |
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288 |
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289 if ( (type == 1) && |
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290 ( (regVal0 != (i+1)) || |
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291 (regVal1 != (i+2)) || |
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292 (regVal2 != (i+3)) || |
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293 (regVal3 != (i+4)) )) |
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294 { |
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295 Kern::Printf("ERROR: Write register failed (%d)\n",i); |
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296 Kern::Printf("ERROR: Exp[0]: 0x%04x\n",i+1); |
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297 Kern::Printf("ERROR: Act[0]: 0x%04x\n",regVal0); |
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298 Kern::Printf("ERROR: Exp[1]: 0x%04x\n",i+2); |
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299 Kern::Printf("ERROR: Act[1]: 0x%04x\n",regVal1); |
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300 Kern::Printf("ERROR: Exp[2]: 0x%04x\n",i+3); |
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301 Kern::Printf("ERROR: Act[2]: 0x%04x\n",regVal2); |
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302 Kern::Printf("ERROR: Exp[3]: 0x%04x\n",i+4); |
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303 Kern::Printf("ERROR: Act[3]: 0x%04x\n",regVal3); |
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304 |
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305 errCnt++ ; |
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306 if ( errCnt > 10 ) |
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307 return 1; |
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308 } |
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309 else if ( (type != 1 ) && |
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310 ((regVal0 != expVal) || |
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311 (regVal1 != ((~expVal)&0xffff)) || |
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312 (regVal2 != expVal) || |
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313 (regVal3 != ((~expVal)&0xffff)) )) |
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314 { |
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315 Kern::Printf("ERROR: Write register failed (%d)\n",i); |
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316 Kern::Printf("ERROR: Exp[0]: 0x%04x\n",expVal); |
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317 Kern::Printf("ERROR: Act[0]: 0x%04x\n",regVal0); |
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318 Kern::Printf("ERROR: Exp[1]: 0x%04x\n",(~expVal)&0xffff); |
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319 Kern::Printf("ERROR: Act[1]: 0x%04x\n",regVal1); |
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320 Kern::Printf("ERROR: Exp[2]: 0x%04x\n",expVal); |
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321 Kern::Printf("ERROR: Act[2]: 0x%04x\n",regVal2); |
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322 Kern::Printf("ERROR: Exp[3]: 0x%04x\n",(~expVal)&0xffff); |
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323 Kern::Printf("ERROR: Act[3]: 0x%04x\n",regVal3); |
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324 |
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325 errCnt++ ; |
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326 if ( errCnt > 10 ) |
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327 return 1 ; |
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328 } |
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329 |
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330 } |
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331 Kern::Printf("Register test PASSED!!\n"); |
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332 return 0 ; |
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333 } |
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334 |
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335 /******************************************************************************/ |
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336 /******************************************************************************/ |
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337 /******************************************************************************/ |
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338 |
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339 static void |
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340 DumpMcSPI4Reg(void) |
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341 { |
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342 TUint32 r ; |
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343 TUint32 i; |
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344 |
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345 for ( i = KMcSPI4_SYSCONFIG ; i <= KMcSPI4_RX0 ; i+=0x4 ) |
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346 { |
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347 r = AsspRegister::Read32(i); |
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348 switch (i) |
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349 { |
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350 case KMcSPI4_SYSCONFIG: |
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351 Kern::Printf("KMcSPI4_SYSCONFIG = (0x%08x)", r); |
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352 break; |
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353 case KMcSPI4_SYSSTATUS: |
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354 Kern::Printf("KMcSPI4_SYSSTATUS = (0x%08x)", r); |
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355 break; |
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356 case KMcSPI4_IRQSTATUS: |
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357 Kern::Printf("KMcSPI4_IRQSTATUS = (0x%08x)", r); |
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358 break; |
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359 case KMcSPI4_IRQENABLE: |
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360 Kern::Printf("KMcSPI4_IRQENABLE = (0x%08x)", r); |
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361 break; |
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362 case KMcSPI4_WAKEUPEN: |
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363 Kern::Printf("KMcSPI4_WAKEUPEN = (0x%08x)", r); |
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364 break; |
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365 case KMcSPI4_SYST: |
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366 Kern::Printf("KMcSPI4_SYST = (0x%08x)", r); |
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367 break; |
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368 case KMcSPI4_MODULCTRL: |
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369 Kern::Printf("KMcSPI4_MODULCTRL = (0x%08x)", r); |
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370 break; |
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371 case KMcSPI4_CH0CONF: |
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372 Kern::Printf("KMcSPI4_CH0CONF = (0x%08x)", r); |
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373 break; |
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374 case KMcSPI4_CH0STAT: |
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375 Kern::Printf("KMcSPI4_CH0STAT = (0x%08x)", r); |
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376 break; |
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377 case KMcSPI4_CH0CTRL: |
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378 Kern::Printf("KMcSPI4_CH0CTRL = (0x%08x)", r); |
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379 break; |
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380 case KMcSPI4_TX0: |
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381 Kern::Printf("KMcSPI4_TX0 = (0x%08x)", r); |
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382 break; |
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383 case KMcSPI4_RX0: |
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384 Kern::Printf("KMcSPI4_RX0 = (0x%08x)", r); |
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385 break; |
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386 case KMcSPI4_XFERLEVEL: |
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387 Kern::Printf("KMcSPI4_XFERLEVEL = (0x%08x)", r); |
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388 break; |
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389 default: |
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390 Kern::Printf("ERROR: unknow register value", r); |
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391 } |
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392 } |
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393 |
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394 r = AsspRegister::Read32(KMcSPI4_XFERLEVEL); |
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395 Kern::Printf("KMcSPI4_XFERLEVEL = (0x%08x)\n", r); |
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396 } |
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397 |
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398 inline TUint32 constructSPIConfigReg( |
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399 TUint8 PHA, |
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400 TUint8 POL, |
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401 TUint8 CLKD, |
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402 TUint8 EPOL, |
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403 TUint8 WL, |
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404 TUint8 TRM, |
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405 TUint8 DMAW, |
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406 TUint8 DMAR, |
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407 TUint8 DPE0, |
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408 TUint8 DPE1, |
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409 TUint8 IS, |
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410 TUint8 TURBO, |
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411 TUint8 FORCE, |
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412 TUint8 SPIENSLV, |
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413 TUint8 SBE, |
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414 TUint8 SBPOL, |
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415 TUint8 TCS, |
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416 TUint8 FFEW, |
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417 TUint8 FFER, |
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418 TUint8 CLKG) |
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419 { |
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420 TUint32 r = 0 ; |
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421 |
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422 r = ( CLKG & 0x1 ) << 29; |
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423 r |= ( FFER & 0x1 ) << 28; |
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424 r |= ( FFEW & 0x1 ) << 27; |
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425 r |= ( TCS & 0x3 ) << 25; |
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426 r |= ( SBPOL & 0x1 ) << 24; |
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427 r |= ( SBE & 0x1 ) << 23; |
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428 r |= ( SPIENSLV & 0x3 ) << 21; |
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429 r |= ( FORCE & 0x1 ) << 20; |
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430 r |= ( TURBO & 0x1 ) << 19; |
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431 r |= ( IS & 0x1 ) << 18; |
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432 r |= ( DPE1 & 0x1 ) << 17; |
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433 r |= ( DPE0 & 0x1 ) << 16; |
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434 r |= ( DMAR & 0x1 ) << 15; |
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435 r |= ( DMAW & 0x1 ) << 14; |
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436 r |= ( TRM & 0x3 ) << 12; |
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437 r |= ( WL & 0x1f ) << 7; |
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438 r |= ( EPOL & 0x1 ) << 6; |
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439 r |= ( CLKD & 0xf ) << 2; |
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440 r |= ( POL & 0x1 ) << 1; |
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441 r |= PHA & 0x1; |
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442 return r ; |
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443 } |
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444 |
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445 static void ConfigMcSPI4Ch0(void) |
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446 { |
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447 TUint32 r ; |
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448 Kern::Printf("Configure McSPI4 CH0...\n"); |
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449 |
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450 /* Enable McSPI4 functional clock */ |
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451 r = AsspRegister::Read32(KCM_FCLKEN1_CORE); |
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452 AsspRegister::Write32(KCM_FCLKEN1_CORE, (r | 0x200000)); |
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453 |
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454 /* Enable McSPI4 interface clock */ |
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455 r = AsspRegister::Read32(KCM_ICLKEN1_CORE); |
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456 AsspRegister::Write32(KCM_ICLKEN1_CORE, (r | 0x200000)); |
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457 |
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458 /* Software reset McSPI4 */ |
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459 AsspRegister::Write32(KMcSPI4_SYSCONFIG, 0x1); |
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460 |
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461 /* Wait until RESETDONE is set in SYSSTATUS */ |
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462 do |
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463 { |
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464 r = AsspRegister::Read32(KMcSPI4_SYSSTATUS); |
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465 Kern::Printf("KMcSPI4_SYSSTATUS = (0x%08x)\n", r); |
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466 }while((r & 0x1) != 1); |
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467 |
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468 /* Disable channel 0 */ |
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469 McSPI4Ch0_Disable(); |
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470 |
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471 /* Disable all interrupts */ |
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472 AsspRegister::Write32(KMcSPI4_IRQENABLE, 0x0); |
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473 |
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474 /* Clear all interrupts */ |
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475 AsspRegister::Write32(KMcSPI4_IRQSTATUS, 0x1777f); |
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476 |
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477 /* Set Master mode */ |
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478 #ifdef SINGLE_CHANNEL_MASTER_MODE |
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479 AsspRegister::Write32(KMcSPI4_MODULCTRL, 0x1); |
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480 #else |
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481 AsspRegister::Write32(KMcSPI4_MODULCTRL, 0x0); |
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482 #endif |
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483 |
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484 |
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485 /* Config clock, wl */ |
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486 r = constructSPIConfigReg( |
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487 0x0, /*PHA*/ |
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488 0x0, /*POL*/ |
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489 0x2, /*CLKD (divider 2 = 12MHz)3 = 6MHz*/ |
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490 0x1, /*EPOL (active low)*/ |
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491 0x7, /*WL (8bit)*/ |
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492 0x0, /*TRM (Transmit and receive mode)*/ |
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493 0x0, /*DMAW (DMAW disable) TODO*/ |
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494 0x0, /*DMAR (DMAR disable) TODO*/ |
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495 0x1, /*DPE0 (spim_somi no transmission)*/ |
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496 0x0, /*DPE1 (spim_simo transmission)*/ |
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497 0x0, /*IS (spim_somi reception)*/ |
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498 0x0, /*TURBO (mutli spi-word transfer)*/ |
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499 0x0, /*FORCE TODO*/ |
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500 0x0, /*SPIENSLV (not used)*/ |
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501 0x0, /*SBE (no start bit) TODO*/ |
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502 0x0, /*SBPOL (start bit polarity) */ |
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503 0x0, /*TCS (cs time control) TODO*/ |
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504 0x0, /*FFEW (FIFO enabled) TODO*/ |
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505 0x0, /*FFER (FIFO enabled) TODO*/ |
|
506 0x0 /*CLKG (One clock cycle granularity)*/ |
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507 ); |
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508 |
|
509 AsspRegister::Write32(KMcSPI4_CH0CONF, r); |
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510 |
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511 } |
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512 |
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513 static void |
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514 SetPADConfigRegister(void) |
|
515 { |
|
516 TUint32 r ; |
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517 Kern::Printf("Set PAD configuration registers...\n"); |
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518 |
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519 /* MUXMODE = 1, INPUTENABLE for SOMI */ |
|
520 AsspRegister::Write32(KPADCONFIG_McSPI4_SIMO_P12_0, 0x1010001); |
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521 |
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522 r = AsspRegister::Read32(KPADCONFIG_McSPI4_CS0_P16_16); |
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523 AsspRegister::Write32(KPADCONFIG_McSPI4_CS0_P16_16, ((r & 0xffff) | 0x10000)); |
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524 |
|
525 /* NOTE: |
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526 we must set SPI clock INPUTENABLE bit otherwise the RX register will not |
|
527 latch any data */ |
|
528 AsspRegister::Write32(KPADCONFIG_McSPI4_CLK_P20_0, 0x40001 | 0x0100); |
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529 |
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530 /* MUXMODE = 4 */ |
|
531 r = AsspRegister::Read32(KPADCONFIG_GPIO183_P23_0); |
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532 //AsspRegister::Write32(KPADCONFIG_GPIO183_P23_0, ((r & 0xffff0000) | 0x4 | 0x8 | 0x0100)); |
|
533 AsspRegister::Write32(KPADCONFIG_GPIO183_P23_0, ((r & 0xffff0000) | 0x4 )); |
|
534 |
|
535 r = AsspRegister::Read32(KPADCONFIG_GPIO168_P24_16); |
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536 AsspRegister::Write32(KPADCONFIG_GPIO168_P24_16, ((r & 0xffff) | 0x40000 | 0x01000000)); |
|
537 |
|
538 } |
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539 |
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540 static void |
|
541 ReadPADConfigRegister(void) |
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542 { |
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543 TUint32 r ; |
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544 |
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545 Kern::Printf("Reading PAD configuration registers..."); |
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546 r = AsspRegister::Read32(KPADCONFIG_McSPI4_SIMO_P12_0); |
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547 Kern::Printf("KPADCONFIG_McSPI4_SIMO_P12_0 = (0x%08x)", r); |
|
548 |
|
549 r = AsspRegister::Read32(KPADCONFIG_McSPI4_SIMO_P18_16); |
|
550 Kern::Printf("KPADCONFIG_McSPI4_SIMO_P18_16 = (0x%08x)", r); |
|
551 |
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552 r = AsspRegister::Read32(KPADCONFIG_McSPI4_CS0_P16_16); |
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553 Kern::Printf("KPADCONFIG_McSPI4_CS0_P16_16 = (0x%08x)", r); |
|
554 |
|
555 r = AsspRegister::Read32(KPADCONFIG_McSPI4_CLK_P20_0); |
|
556 Kern::Printf("KPADCONFIG_McSPI4_CLK_P20_0 = (0x%08x)", r); |
|
557 |
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558 r = AsspRegister::Read32(KPADCONFIG_GPIO157_P22_16); |
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559 Kern::Printf("KPADCONFIG_GPIO157_P22_16 = (0x%08x)", r); |
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560 |
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561 r = AsspRegister::Read32(KPADCONFIG_GPIO183_P23_0); |
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562 Kern::Printf("KPADCONFIG_GPIO183_P23_0 = (0x%08x)", r); |
|
563 |
|
564 r = AsspRegister::Read32(KPADCONFIG_GPIO168_P24_16); |
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565 Kern::Printf("KPADCONFIG_GPIO168_P24_16 = (0x%08x)", r); |
|
566 |
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567 } |
|
568 |
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569 /***********************************************************************/ |
|
570 /**************************** Public *******************************/ |
|
571 /***********************************************************************/ |
|
572 |
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573 void |
|
574 CyAsHalBeagleBoardMcSPI4Ch0_WriteEP(TUint32 addr, TUint8* buff, TUint16 size) |
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575 { |
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576 TUint8 size_l = size ; |
|
577 TUint8 size_h = (size >> 8)&0x7f ; |
|
578 TUint16 size16 = size / 2 ; |
|
579 TUint8* p = buff ; |
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580 |
|
581 TUint32 r ; |
|
582 |
|
583 r = 0x00800000; |
|
584 r |= (addr & 0xff) << 8 ; |
|
585 r |= size_l << 24 ; |
|
586 r |= size_h << 16 ; |
|
587 #ifdef SPI_DEBUG_LOG |
|
588 Kern::Printf("WB SPI write packet header = (0x%08x)", r); |
|
589 #endif |
|
590 /* Set McSPI4Ch0 to Transmit only mode for write */ |
|
591 McSPI4Ch0_TransmitMode(); |
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592 |
|
593 McSPI4Ch0_Enable(); |
|
594 |
|
595 CheckForTxEmpty(); |
|
596 AsspRegister::Write32(KMcSPI4_TX0, r); |
|
597 CheckForTxEmpty(); |
|
598 AsspRegister::Write32(KMcSPI4_TX0, r>>8); |
|
599 CheckForTxEmpty(); |
|
600 AsspRegister::Write32(KMcSPI4_TX0, r>>16); |
|
601 CheckForTxEmpty(); |
|
602 AsspRegister::Write32(KMcSPI4_TX0, r>>24); |
|
603 |
|
604 while(size16 != 0) |
|
605 { |
|
606 CheckForTxEmpty(); |
|
607 AsspRegister::Write32(KMcSPI4_TX0, *(p+1)); |
|
608 CheckForTxEmpty(); |
|
609 AsspRegister::Write32(KMcSPI4_TX0, *p); |
|
610 |
|
611 /*#ifdef SPI_DEBUG_LOG |
|
612 Kern::Printf("0x%02x", *(p+1)); |
|
613 Kern::Printf("0x%02x", *p); |
|
614 #endif*/ |
|
615 p+=2 ; |
|
616 size16-- ; |
|
617 } |
|
618 |
|
619 CheckForTxEmpty(); |
|
620 |
|
621 McSPI4Ch0_Disable(); |
|
622 |
|
623 /* |
|
624 * Change back to Transmit and Receive mode for RegRead |
|
625 */ |
|
626 McSPI4Ch0_TransmitAndReceiveMode(); |
|
627 |
|
628 } |
|
629 |
|
630 void |
|
631 CyAsHalBeagleBoardMcSPI4Ch0_ReadEP(TUint32 addr, TUint8* buff, TUint16 size) |
|
632 { |
|
633 TUint8 size_l = size ; |
|
634 TUint8 size_h = (size >> 8)&0x7f ; |
|
635 TUint16 size16 = size / 2 ; |
|
636 TUint32 r ; |
|
637 |
|
638 r = 0x00000000; |
|
639 r |= (addr & 0xff) << 8 ; |
|
640 r |= size_l << 24 ; |
|
641 r |= size_h << 16 ; |
|
642 #ifdef SPI_DEBUG_LOG |
|
643 Kern::Printf("WB SPI read packet header = (0x%08x)", r); |
|
644 #endif |
|
645 |
|
646 McSPI4Ch0_Enable(); |
|
647 |
|
648 { |
|
649 CheckForTxEmpty(); |
|
650 AsspRegister::Write32(KMcSPI4_TX0, r); |
|
651 CheckForTxEmptyRxFull(); |
|
652 AsspRegister::Read32(KMcSPI4_RX0); |
|
653 |
|
654 AsspRegister::Write32(KMcSPI4_TX0, r>>8); |
|
655 CheckForTxEmptyRxFull(); |
|
656 AsspRegister::Read32(KMcSPI4_RX0); |
|
657 |
|
658 |
|
659 AsspRegister::Write32(KMcSPI4_TX0, r>>16); |
|
660 CheckForTxEmptyRxFull(); |
|
661 AsspRegister::Read32(KMcSPI4_RX0); |
|
662 |
|
663 AsspRegister::Write32(KMcSPI4_TX0, r>>24); |
|
664 CheckForTxEmptyRxFull(); |
|
665 AsspRegister::Read32(KMcSPI4_RX0); |
|
666 |
|
667 while(size16 != 0) |
|
668 { |
|
669 AsspRegister::Write32(KMcSPI4_TX0, 0); |
|
670 CheckForTxEmptyRxFull(); |
|
671 *(buff+1) = AsspRegister::Read32(KMcSPI4_RX0); |
|
672 |
|
673 AsspRegister::Write32(KMcSPI4_TX0, 0); |
|
674 CheckForTxEmptyRxFull(); |
|
675 *buff = AsspRegister::Read32(KMcSPI4_RX0); |
|
676 |
|
677 buff+=2; |
|
678 size16--; |
|
679 |
|
680 } |
|
681 |
|
682 } |
|
683 |
|
684 McSPI4Ch0_Disable(); |
|
685 |
|
686 } |
|
687 |
|
688 void |
|
689 CyAsHalBeagleBoardMcSPI4Ch0_WriteReg(TUint32 addr, TUint16 value) |
|
690 { |
|
691 TUint32 r ; |
|
692 |
|
693 r = 0x02800000; |
|
694 r |= (addr & 0xff) << 8 ; |
|
695 #ifdef SPI_DEBUG_LOG |
|
696 Kern::Printf("WB SPI write packet header = (0x%08x), value = (0x%04x)", r, value); |
|
697 #endif |
|
698 |
|
699 /* Set McSPI4Ch0 to Transmit only mode for write */ |
|
700 McSPI4Ch0_TransmitMode(); |
|
701 |
|
702 McSPI4Ch0_Enable(); |
|
703 |
|
704 CheckForTxEmpty(); |
|
705 AsspRegister::Write32(KMcSPI4_TX0, r); |
|
706 CheckForTxEmpty(); |
|
707 AsspRegister::Write32(KMcSPI4_TX0, r>>8); |
|
708 CheckForTxEmpty(); |
|
709 AsspRegister::Write32(KMcSPI4_TX0, r>>16); |
|
710 CheckForTxEmpty(); |
|
711 AsspRegister::Write32(KMcSPI4_TX0, r>>24); |
|
712 CheckForTxEmpty(); |
|
713 AsspRegister::Write32(KMcSPI4_TX0, value>>8); |
|
714 CheckForTxEmpty(); |
|
715 AsspRegister::Write32(KMcSPI4_TX0, value & 0xff ); |
|
716 CheckForTxEmpty(); |
|
717 |
|
718 McSPI4Ch0_Disable(); |
|
719 |
|
720 /* |
|
721 * Change back to Transmit and Receive mode for RegRead |
|
722 */ |
|
723 McSPI4Ch0_TransmitAndReceiveMode(); |
|
724 } |
|
725 |
|
726 void |
|
727 CyAsHalBeagleBoardMcSPI4Ch0_ReadReg(TUint32 addr, TUint16* value) |
|
728 { |
|
729 TUint32 r ; |
|
730 |
|
731 r = 0x02000000; |
|
732 r |= (addr & 0xff) << 8 ; |
|
733 #ifdef SPI_DEBUG_LOG |
|
734 Kern::Printf("WB SPI read packet header = (0x%08x)", r); |
|
735 #endif |
|
736 |
|
737 McSPI4Ch0_Enable(); |
|
738 |
|
739 { |
|
740 TUint16 v ; |
|
741 |
|
742 CheckForTxEmpty(); |
|
743 AsspRegister::Write32(KMcSPI4_TX0, r); |
|
744 CheckForTxEmptyRxFull(); |
|
745 AsspRegister::Read32(KMcSPI4_RX0); |
|
746 |
|
747 AsspRegister::Write32(KMcSPI4_TX0, r>>8); |
|
748 CheckForTxEmptyRxFull(); |
|
749 AsspRegister::Read32(KMcSPI4_RX0); |
|
750 |
|
751 |
|
752 AsspRegister::Write32(KMcSPI4_TX0, r>>16); |
|
753 CheckForTxEmptyRxFull(); |
|
754 AsspRegister::Read32(KMcSPI4_RX0); |
|
755 |
|
756 AsspRegister::Write32(KMcSPI4_TX0, r>>24); |
|
757 CheckForTxEmptyRxFull(); |
|
758 AsspRegister::Read32(KMcSPI4_RX0); |
|
759 |
|
760 AsspRegister::Write32(KMcSPI4_TX0, 0); |
|
761 CheckForTxEmptyRxFull(); |
|
762 v = AsspRegister::Read32(KMcSPI4_RX0); |
|
763 *value = v << 8; |
|
764 |
|
765 AsspRegister::Write32(KMcSPI4_TX0, 0); |
|
766 CheckForTxEmptyRxFull(); |
|
767 v = AsspRegister::Read32(KMcSPI4_RX0); |
|
768 *value |= v & 0xff; |
|
769 |
|
770 } |
|
771 |
|
772 McSPI4Ch0_Disable(); |
|
773 |
|
774 } |
|
775 |
|
776 int |
|
777 CyAsHalBeagleBoard__ConfigureSPI(void) |
|
778 { |
|
779 /*Configure PAD*/ |
|
780 ReadPADConfigRegister(); |
|
781 SetPADConfigRegister(); |
|
782 ReadPADConfigRegister(); |
|
783 |
|
784 /*Configure McSPI4*/ |
|
785 ConfigMcSPI4Ch0(); |
|
786 DumpMcSPI4Reg(); |
|
787 |
|
788 McSPI4Ch0_Enable(); |
|
789 |
|
790 if(KErrNone != GPIO::SetPinMode(KGPIO_183, GPIO::EEnabled)) |
|
791 Kern::Printf("ERROR: SetPinMode failed!"); |
|
792 |
|
793 if(KErrNone != GPIO::SetPinDirection(KGPIO_183, GPIO::EOutput)) |
|
794 Kern::Printf("ERROR: SetPinDirection failed!"); |
|
795 |
|
796 if(KErrNone != GPIO::SetOutputState(KGPIO_183, GPIO::EHigh)) |
|
797 Kern::Printf("ERROR: SetOutputState failed!"); |
|
798 |
|
799 gConfigured = 1 ; |
|
800 return 0 ; |
|
801 } |
|
802 |
|
803 /*****************************************************************************/ |
|
804 /*****************************************************************************/ |
|
805 /*****************************************************************************/ |
|
806 |
|
807 extern int |
|
808 CyAsHalBeagleBoard__Test(void) |
|
809 { |
|
810 int i ; |
|
811 int errCnt = 0 ; |
|
812 |
|
813 if ( !gConfigured ) |
|
814 { |
|
815 CyAsHalBeagleBoard__ConfigureSPI(); |
|
816 } |
|
817 |
|
818 { |
|
819 TUint16 regVal = 0 ; |
|
820 |
|
821 Kern::Printf("Read Astoria ID register\n"); |
|
822 |
|
823 CyAsHalBeagleBoardMcSPI4Ch0_ReadReg(0x80, ®Val) ; |
|
824 |
|
825 if ( regVal != 0xA200 ) |
|
826 { |
|
827 Kern::Printf("ERROR: Wrong ID register value\n"); |
|
828 Kern::Printf("ERROR: Exp: 0x%04x\n",0xa200); |
|
829 Kern::Printf("ERROR: Act: 0x%04x\n",regVal); |
|
830 errCnt++; |
|
831 return errCnt ; |
|
832 } |
|
833 else |
|
834 { |
|
835 Kern::Printf("ID register read successful 0x%04x\n",regVal); |
|
836 } |
|
837 } |
|
838 |
|
839 { |
|
840 Kern::Printf("Register test...\n"); |
|
841 for ( i = 1 ; i < 4 ; i++ ) |
|
842 { |
|
843 if ( AstoriaRegTest(i) != 0 ) |
|
844 { |
|
845 errCnt++ ; |
|
846 return errCnt ; |
|
847 } |
|
848 } |
|
849 |
|
850 } |
|
851 |
|
852 { |
|
853 |
|
854 Kern::Printf("Interrupt test...\n"); |
|
855 |
|
856 /* Setup DFC */ |
|
857 gpMyDfc = new TDfc( myTestDFCFn, (void*)(&gISRCnt), Kern::DfcQue0(), 1 ) ; |
|
858 CyAsHalBeagleBoard__SetupISR((void*)myISR,(void*)(0)); |
|
859 |
|
860 for ( i = 0 ; i < 5 ; i++ ) |
|
861 { |
|
862 Kern::Printf("Manually trigger interrupt (%d)\n",i); |
|
863 |
|
864 ManualTriggerISRTest(); |
|
865 |
|
866 |
|
867 if (gISRCnt != i+1) |
|
868 { |
|
869 Kern::Printf("ISR called (%d)\n",gISRCnt); |
|
870 } |
|
871 else |
|
872 { |
|
873 Kern::Printf("ISR didn't call (%d)\n",gISRCnt); |
|
874 Kern::Printf("Interrupt test failed\n"); |
|
875 errCnt++ ; |
|
876 return errCnt ; |
|
877 } |
|
878 } |
|
879 } |
|
880 |
|
881 Kern::Printf("CyAsHalBeagleBoard__Test Successful!\n"); |
|
882 |
|
883 /*if ( gIndex == 1 ) |
|
884 { |
|
885 GPIO::TGpioState aState ; |
|
886 |
|
887 GPIO::GetOutputState(KGPIO_183, aState); |
|
888 |
|
889 if ( aState == GPIO::EHigh ) |
|
890 { |
|
891 if(KErrNone != GPIO::SetOutputState(KGPIO_183, GPIO::ELow)) |
|
892 Kern::Printf("ERROR: SetOutputState failed!"); |
|
893 } |
|
894 else |
|
895 { |
|
896 if(KErrNone != GPIO::SetOutputState(KGPIO_183, GPIO::EHigh)) |
|
897 Kern::Printf("ERROR: SetOutputState failed!"); |
|
898 } |
|
899 gIndex = 0 ; |
|
900 }*/ |
|
901 |
|
902 /* |
|
903 if ( gIndex == 2 ) |
|
904 { |
|
905 McSPI4Ch0_DumpAstoriaRegs(0); |
|
906 } |
|
907 |
|
908 if ( gIndex == 3 ) |
|
909 { |
|
910 McSPI4Ch0_DumpAstoriaRegs(1); |
|
911 gIndex = 0 ; |
|
912 } |
|
913 */ |
|
914 return 0 ; |
|
915 } |
|
916 |
|
917 /******************************************************************************/ |
|
918 /******************************************************************************/ |
|
919 /******************************************************************************/ |
|
920 |
|
921 |
|
922 |
|
923 |
|
924 |
|
925 |
|
926 |
|
927 |