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1 /* Cypress West Bridge API header file (cyasregs.h) |
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2 ## =========================== |
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3 ## |
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4 ## Copyright Cypress Semiconductor Corporation, 2006-2009, |
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5 ## All Rights Reserved |
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6 ## UNPUBLISHED, LICENSED SOFTWARE. |
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7 ## |
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8 ## CONFIDENTIAL AND PROPRIETARY INFORMATION |
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9 ## WHICH IS THE PROPERTY OF CYPRESS. |
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10 ## |
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11 ## Use of this file is governed |
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12 ## by the license agreement included in the file |
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13 ## |
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14 ## <install>/license/license.txt |
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15 ## |
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16 ## where <install> is the Cypress software |
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17 ## installation root directory path. |
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18 ## |
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19 ## =========================== |
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20 */ |
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21 |
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22 #ifndef _INCLUDED_CYASREG_H_ |
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23 #define _INCLUDED_CYASREG_H_ |
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24 |
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25 #if !defined(__doxygen__) |
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26 |
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27 #define CY_AS_MEM_CM_WB_CFG_ID (0x80) |
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28 #define CY_AS_MEM_CM_WB_CFG_ID_VER_MASK (0x000F) |
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29 #define CY_AS_MEM_CM_WB_CFG_ID_HDID_MASK (0xFFF0) |
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30 #define CY_AS_MEM_CM_WB_CFG_ID_HDID_ANTIOCH_VALUE (0xA100) |
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31 #define CY_AS_MEM_CM_WB_CFG_ID_HDID_ASTORIA_FPGA_VALUE (0x6800) |
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32 #define CY_AS_MEM_CM_WB_CFG_ID_HDID_ASTORIA_VALUE (0xA200) |
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33 |
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34 |
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35 #define CY_AS_MEM_RST_CTRL_REG (0x81) |
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36 #define CY_AS_MEM_RST_CTRL_REG_HARD (0x0003) |
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37 #define CY_AS_MEM_RST_CTRL_REG_SOFT (0x0001) |
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38 #define CY_AS_MEM_RST_RSTCMPT (0x0004) |
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39 |
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40 #define CY_AS_MEM_P0_ENDIAN (0x82) |
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41 #define CY_AS_LITTLE_ENDIAN (0x0000) |
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42 #define CY_AS_BIG_ENDIAN (0x0101) |
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43 |
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44 #define CY_AS_MEM_P0_VM_SET (0x83) |
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45 #define CY_AS_MEM_P0_VM_SET_VMTYPE_MASK (0x0007) |
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46 #define CY_AS_MEM_P0_VM_SET_VMTYPE_RAM (0x0005) |
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47 #define CY_AS_MEM_P0_VM_SET_VMTYPE_SRAM (0x0007) |
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48 #define CY_AS_MEM_P0_VM_SET_VMTYPE_VMWIDTH (0x0008) |
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49 #define CY_AS_MEM_P0_VM_SET_VMTYPE_FLOWCTRL (0x0010) |
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50 #define CY_AS_MEM_P0_VM_SET_IFMODE (0x0020) |
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51 #define CY_AS_MEM_P0_VM_SET_CFGMODE (0x0040) |
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52 #define CY_AS_MEM_P0_VM_SET_DACKEOB (0x0080) |
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53 #define CY_AS_MEM_P0_VM_SET_OVERRIDE (0x0100) |
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54 #define CY_AS_MEM_P0_VM_SET_INTOVERD (0x0200) |
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55 #define CY_AS_MEM_P0_VM_SET_DRQOVERD (0x0400) |
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56 #define CY_AS_MEM_P0_VM_SET_DRQPOL (0x0800) |
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57 #define CY_AS_MEM_P0_VM_SET_DACKPOL (0x1000) |
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58 |
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59 |
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60 #define CY_AS_MEM_P0_NV_SET (0x84) |
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61 #define CY_AS_MEM_P0_NV_SET_WPSWEN (0x0001) |
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62 #define CY_AS_MEM_P0_NV_SET_WPPOLAR (0x0002) |
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63 |
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64 #define CY_AS_MEM_PMU_UPDATE (0x85) |
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65 #define CY_AS_MEM_PMU_UPDATE_UVALID (0x0001) |
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66 #define CY_AS_MEM_PMU_UPDATE_USBUPDATE (0x0002) |
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67 #define CY_AS_MEM_PMU_UPDATE_SDIOUPDATE (0x0004) |
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68 |
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69 #define CY_AS_MEM_P0_INTR_REG (0x90) |
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70 #define CY_AS_MEM_P0_INTR_REG_MCUINT (0x0020) |
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71 #define CY_AS_MEM_P0_INTR_REG_DRQINT (0x0800) |
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72 #define CY_AS_MEM_P0_INTR_REG_MBINT (0x1000) |
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73 #define CY_AS_MEM_P0_INTR_REG_PMINT (0x2000) |
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74 #define CY_AS_MEM_P0_INTR_REG_PLLLOCKINT (0x4000) |
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75 |
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76 #define CY_AS_MEM_P0_INT_MASK_REG (0x91) |
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77 #define CY_AS_MEM_P0_INT_MASK_REG_MMCUINT (0x0020) |
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78 #define CY_AS_MEM_P0_INT_MASK_REG_MDRQINT (0x0800) |
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79 #define CY_AS_MEM_P0_INT_MASK_REG_MMBINT (0x1000) |
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80 #define CY_AS_MEM_P0_INT_MASK_REG_MPMINT (0x2000) |
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81 #define CY_AS_MEM_P0_INT_MASK_REG_MPLLLOCKINT (0x4000) |
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82 |
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83 #define CY_AS_MEM_MCU_MB_STAT (0x92) |
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84 #define CY_AS_MEM_P0_MCU_MBNOTRD (0x0001) |
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85 |
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86 #define CY_AS_MEM_P0_MCU_STAT (0x94) |
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87 #define CY_AS_MEM_P0_MCU_STAT_CARDINS (0x0001) |
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88 #define CY_AS_MEM_P0_MCU_STAT_CARDREM (0x0002) |
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89 |
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90 #define CY_AS_MEM_PWR_MAGT_STAT (0x95) |
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91 #define CY_AS_MEM_PWR_MAGT_STAT_WAKEUP (0x0001) |
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92 |
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93 #define CY_AS_MEM_P0_RSE_ALLOCATE (0x98) |
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94 #define CY_AS_MEM_P0_RSE_ALLOCATE_SDIOAVI (0x0001) |
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95 #define CY_AS_MEM_P0_RSE_ALLOCATE_SDIOALLO (0x0002) |
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96 #define CY_AS_MEM_P0_RSE_ALLOCATE_NANDAVI (0x0004) |
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97 #define CY_AS_MEM_P0_RSE_ALLOCATE_NANDALLO (0x0008) |
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98 #define CY_AS_MEM_P0_RSE_ALLOCATE_USBAVI (0x0010) |
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99 #define CY_AS_MEM_P0_RSE_ALLOCATE_USBALLO (0x0020) |
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100 |
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101 #define CY_AS_MEM_P0_RSE_MASK (0x9A) |
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102 #define CY_AS_MEM_P0_RSE_MASK_MSDIOBUS_RW (0x0003) |
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103 #define CY_AS_MEM_P0_RSE_MASK_MNANDBUS_RW (0x00C0) |
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104 #define CY_AS_MEM_P0_RSE_MASK_MUSBBUS_RW (0x0030) |
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105 |
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106 #define CY_AS_MEM_P0_DRQ (0xA0) |
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107 #define CY_AS_MEM_P0_DRQ_EP2DRQ (0x0004) |
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108 #define CY_AS_MEM_P0_DRQ_EP3DRQ (0x0008) |
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109 #define CY_AS_MEM_P0_DRQ_EP4DRQ (0x0010) |
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110 #define CY_AS_MEM_P0_DRQ_EP5DRQ (0x0020) |
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111 #define CY_AS_MEM_P0_DRQ_EP6DRQ (0x0040) |
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112 #define CY_AS_MEM_P0_DRQ_EP7DRQ (0x0080) |
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113 #define CY_AS_MEM_P0_DRQ_EP8DRQ (0x0100) |
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114 #define CY_AS_MEM_P0_DRQ_EP9DRQ (0x0200) |
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115 #define CY_AS_MEM_P0_DRQ_EP10DRQ (0x0400) |
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116 #define CY_AS_MEM_P0_DRQ_EP11DRQ (0x0800) |
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117 #define CY_AS_MEM_P0_DRQ_EP12DRQ (0x1000) |
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118 #define CY_AS_MEM_P0_DRQ_EP13DRQ (0x2000) |
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119 #define CY_AS_MEM_P0_DRQ_EP14DRQ (0x4000) |
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120 #define CY_AS_MEM_P0_DRQ_EP15DRQ (0x8000) |
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121 |
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122 #define CY_AS_MEM_P0_DRQ_MASK (0xA1) |
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123 #define CY_AS_MEM_P0_DRQ_MASK_MEP2DRQ (0x0004) |
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124 #define CY_AS_MEM_P0_DRQ_MASK_MEP3DRQ (0x0008) |
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125 #define CY_AS_MEM_P0_DRQ_MASK_MEP4DRQ (0x0010) |
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126 #define CY_AS_MEM_P0_DRQ_MASK_MEP5DRQ (0x0020) |
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127 #define CY_AS_MEM_P0_DRQ_MASK_MEP6DRQ (0x0040) |
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128 #define CY_AS_MEM_P0_DRQ_MASK_MEP7DRQ (0x0080) |
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129 #define CY_AS_MEM_P0_DRQ_MASK_MEP8DRQ (0x0100) |
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130 #define CY_AS_MEM_P0_DRQ_MASK_MEP9DRQ (0x0200) |
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131 #define CY_AS_MEM_P0_DRQ_MASK_MEP10DRQ (0x0400) |
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132 #define CY_AS_MEM_P0_DRQ_MASK_MEP11DRQ (0x0800) |
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133 #define CY_AS_MEM_P0_DRQ_MASK_MEP12DRQ (0x1000) |
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134 #define CY_AS_MEM_P0_DRQ_MASK_MEP13DRQ (0x2000) |
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135 #define CY_AS_MEM_P0_DRQ_MASK_MEP14DRQ (0x4000) |
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136 #define CY_AS_MEM_P0_DRQ_MASK_MEP15DRQ (0x8000) |
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137 |
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138 #define CY_AS_MEM_P0_EP2_DMA_REG (0xA2) |
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139 #define CY_AS_MEM_P0_EPn_DMA_REG_COUNT_MASK (0x7FF) |
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140 #define CY_AS_MEM_P0_EPn_DMA_REG_DMAVAL (1 << 12) |
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141 #define CY_AS_MEM_P0_EP3_DMA_REG (0xA3) |
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142 #define CY_AS_MEM_P0_EP4_DMA_REG (0xA4) |
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143 #define CY_AS_MEM_P0_EP5_DMA_REG (0xA5) |
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144 #define CY_AS_MEM_P0_EP6_DMA_REG (0xA6) |
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145 #define CY_AS_MEM_P0_EP7_DMA_REG (0xA7) |
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146 #define CY_AS_MEM_P0_EP8_DMA_REG (0xA8) |
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147 #define CY_AS_MEM_P0_EP9_DMA_REG (0xA9) |
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148 #define CY_AS_MEM_P0_EP10_DMA_REG (0xAA) |
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149 #define CY_AS_MEM_P0_EP11_DMA_REG (0xAB) |
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150 #define CY_AS_MEM_P0_EP12_DMA_REG (0xAC) |
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151 #define CY_AS_MEM_P0_EP13_DMA_REG (0xAD) |
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152 #define CY_AS_MEM_P0_EP14_DMA_REG (0xAE) |
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153 #define CY_AS_MEM_P0_EP15_DMA_REG (0xAF) |
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154 |
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155 #define CY_AS_MEM_IROS_SLB_DATARET (0xC0) |
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156 |
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157 #define CY_AS_MEM_IROS_IO_CFG (0xC1) |
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158 #define CY_AS_MEM_IROS_IO_CFG_GPIODRVST_MASK (0x0003) |
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159 #define CY_AS_MEM_IROS_IO_CFG_GPIOSLEW_MASK (0x0004) |
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160 #define CY_AS_MEM_IROS_IO_CFG_PPIODRVST_MASK (0x0018) |
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161 #define CY_AS_MEM_IROS_IO_CFG_PPIOSLEW_MASK (0x0020) |
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162 #define CY_AS_MEM_IROS_IO_CFG_SSIODRVST_MASK (0x0300) |
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163 #define CY_AS_MEM_IROS_IO_CFG_SSIOSLEW_MASK (0x0400) |
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164 #define CY_AS_MEM_IROS_IO_CFG_SNIODRVST_MASK (0x1800) |
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165 #define CY_AS_MEM_IROS_IO_CFG_SNIOSLEW_MASK (0x2000) |
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166 |
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167 #define CY_AS_MEM_IROS_PLL_CFG (0xC2) |
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168 |
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169 #define CY_AS_MEM_IROS_PXB_DATARET (0xC3) |
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170 |
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171 #define CY_AS_MEM_PLL_LOCK_LOSS_STAT (0xC4) |
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172 #define CY_AS_MEM_PLL_LOCK_LOSS_STAT_PLLSTAT (0x0800) |
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173 |
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174 #define CY_AS_MEM_IROS_SLEEP_CFG (0xC5) |
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175 |
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176 #define CY_AS_MEM_PNAND_CFG (0xDA) |
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177 #define CY_AS_MEM_PNAND_CFG_IOWIDTH_MASK (0x0001) |
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178 #define CY_AS_MEM_PNAND_CFG_IOWIDTH_8BIT (0x0000) |
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179 #define CY_AS_MEM_PNAND_CFG_IOWIDTH_16BIT (0x0001) |
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180 #define CY_AS_MEM_PNAND_CFG_BLKTYPE_MASK (0x0002) |
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181 #define CY_AS_MEM_PNAND_CFG_BLKTYPE_SMALL (0x0002) |
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182 #define CY_AS_MEM_PNAND_CFG_BLKTYPE_LARGE (0x0000) |
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183 #define CY_AS_MEM_PNAND_CFG_EPABYTE_POS (4) |
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184 #define CY_AS_MEM_PNAND_CFG_EPABYTE_MASK (0x0030) |
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185 #define CY_AS_MEM_PNAND_CFG_EPABIT_POS (6) |
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186 #define CY_AS_MEM_PNAND_CFG_EPABIT_MASK (0x00C0) |
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187 #define CY_AS_MEM_PNAND_CFG_LNAEN_MASK (0x0100) |
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188 |
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189 #define CY_AS_MEM_P0_MAILBOX0 (0xF0) |
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190 #define CY_AS_MEM_P0_MAILBOX1 (0xF1) |
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191 #define CY_AS_MEM_P0_MAILBOX2 (0xF2) |
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192 #define CY_AS_MEM_P0_MAILBOX3 (0xF3) |
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193 |
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194 #define CY_AS_MEM_MCU_MAILBOX0 (0xF8) |
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195 #define CY_AS_MEM_MCU_MAILBOX1 (0xF9) |
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196 #define CY_AS_MEM_MCU_MAILBOX2 (0xFA) |
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197 #define CY_AS_MEM_MCU_MAILBOX3 (0xFB) |
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198 |
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199 #endif /* !defined(__doxygen__) */ |
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200 |
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201 #endif /* _INCLUDED_CYASREG_H_ */ |