omap3530/beagle_drivers/usbv/usbv.cpp
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     1 // Copyright (c) 2004-2009 Nokia Corporation and/or its subsidiary(-ies).
       
     2 // All rights reserved.
       
     3 // This component and the accompanying materials are made available
       
     4 // under the terms of the License "Eclipse Public License v1.0"
       
     5 // which accompanies this distribution, and is available
       
     6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".
       
     7 //
       
     8 // Initial Contributors:
       
     9 // Nokia Corporation - initial contribution.
       
    10 //
       
    11 // Contributors:
       
    12 //
       
    13 // Description:
       
    14 // omap3530/beagle_drivers/usb/usbv.cpp
       
    15 //
       
    16 
       
    17 #include <kernel.h>
       
    18 #include <assp/omap3530_assp/omap3530_usbc.h>
       
    19 // Platform-dependent USB client controller layer (USB PSL).
       
    20 #include <assp/omap3530_assp/omap3530_i2c.h>
       
    21 #include <assp/omap3530_assp/omap3530_i2creg.h>
       
    22 #include <assp/omap3530_shared/tps65950.h>
       
    23 
       
    24 
       
    25 // I2C Bit definitions
       
    26 // PHY_CLK_CTRL
       
    27 const TUint KCLK32K_EN = KBit1;
       
    28 const TUint KREQ_PHY_DPLL_CLK = KBit0;
       
    29 // PHY_CLK_STS
       
    30 const TUint KPHY_DPLL_CLK = KBit0;
       
    31 // MCPC_CTRL2
       
    32 const TUint KMPC_CLK_EN = KBit0;
       
    33 // FUNC_CTRL
       
    34 const TUint KXCVRSELECT_HS = 0x0;
       
    35 const TUint KXCVRSELECT_FS = KBit0;
       
    36 const TUint KXCVRSELECT_MASK = 0x3;
       
    37 const TUint KTERMSELECT = KBit2;
       
    38 const TUint KOPMODE_DISABLED = KBit4;
       
    39 const TUint KOPMODE_MASK = KBit3 | KBit4;
       
    40 // MCPC_IO_CTRL
       
    41 const TUint KRXD_PU = KBit3;
       
    42 // OTG_CTRL
       
    43 const TUint KDPPULLDOWN = KBit1;
       
    44 const TUint KDMPULLDOWN = KBit2;
       
    45 // POWER_CTRL
       
    46 const TUint KOTG_EN = KBit5;
       
    47 // VUSB???_DEV_GRP
       
    48 const TUint KDEV_GRP_P1 = KBit5;
       
    49 // CFG_BOOT
       
    50 const TUint KHFCLK_FREQ_26Mhz = KBit1;
       
    51 
       
    52 
       
    53 NONSHARABLE_CLASS( TBeagleUsbPhy ) : public MOmap3530UsbPhy
       
    54 	{
       
    55 public:
       
    56 	TBeagleUsbPhy();
       
    57 	TInt Construct();
       
    58 
       
    59 	virtual void StartPHY();
       
    60 	virtual void SetPHYMode( DOmap3530Usbcc::TPHYMode aMode );
       
    61 	virtual void EnablePHY();
       
    62 	virtual void DisablePHY();
       
    63 
       
    64 private:
       
    65 	TInt iPHYEnabled;
       
    66 	};
       
    67 
       
    68 
       
    69 
       
    70 TBeagleUsbPhy::TBeagleUsbPhy()
       
    71 	{
       
    72 	}
       
    73 
       
    74 TInt TBeagleUsbPhy::Construct()
       
    75 	{
       
    76 	return KErrNone;
       
    77 	}
       
    78 
       
    79 
       
    80 void TBeagleUsbPhy::StartPHY()
       
    81 	{
       
    82 	// PHY clock must be enabled before this point (can't enable it in this function as it is called from an ISR context)
       
    83 	TPS65950::DisableProtect();
       
    84 	
       
    85 	// Enable the USB LDO's (low-dropout regulators)
       
    86 	TPS65950::ClearSetSync(TPS65950::Register::VUSB1V5_DEV_GRP,0x00,KDEV_GRP_P1);
       
    87 	TPS65950::ClearSetSync(TPS65950::Register::VUSB1V8_DEV_GRP,0x00,KDEV_GRP_P1);
       
    88 	TPS65950::ClearSetSync(TPS65950::Register::VUSB3V1_DEV_GRP,0x00,KDEV_GRP_P1);
       
    89 
       
    90 	TPS65950::ClearSetSync(TPS65950::Register::CFG_BOOT,0x00, KHFCLK_FREQ_26Mhz);	
       
    91 	
       
    92 	TPS65950::RestoreProtect();
       
    93 	}
       
    94 
       
    95 void TBeagleUsbPhy::SetPHYMode( DOmap3530Usbcc::TPHYMode aMode )
       
    96 	{
       
    97 	EnablePHY();
       
    98 	switch(aMode)
       
    99 		{
       
   100 		// Configure trancever (see swcu05b.pdf table 15-21 D+/D- Termination settings) 
       
   101 		case DOmap3530Usbcc::ENormal:
       
   102 			TPS65950::WriteSync(TPS65950::Register::MCPC_CTRL2_CLR, KMPC_CLK_EN); // Not UART Mode
       
   103 			TPS65950::WriteSync(TPS65950::Register::FUNC_CTRL_CLR,(KXCVRSELECT_MASK | KTERMSELECT | KOPMODE_DISABLED ));	 // XCVRSELECT high speed mode (HS), TERM SELECT=0, OPMODE=0 (normal operation)	
       
   104 			TPS65950::WriteSync(TPS65950::Register::MCPC_IO_CTRL_CLR, KRXD_PU);
       
   105 			TPS65950::WriteSync(TPS65950::Register::OTG_CTRL_CLR, KDPPULLDOWN | KDMPULLDOWN); // Disable DP pulldown 
       
   106 			TPS65950::WriteSync(TPS65950::Register::POWER_CTRL_SET, KOTG_EN);
       
   107 			break;
       
   108 		case DOmap3530Usbcc::EPowerUp:
       
   109 			// Power up or VBUS<VSESSEND			
       
   110 			TPS65950::WriteSync(TPS65950::Register::MCPC_CTRL2_CLR, KMPC_CLK_EN); // Not UART Mode
       
   111 			TPS65950::WriteSync(TPS65950::Register::FUNC_CTRL, KXCVRSELECT_FS);		 // XXcvr Select 01, Term select 0, opmode 0,
       
   112 			TPS65950::WriteSync(TPS65950::Register::OTG_CTRL_SET, KDPPULLDOWN | KDMPULLDOWN); // Disable DP pulldown 
       
   113 			TPS65950::WriteSync(TPS65950::Register::POWER_CTRL_CLR, KOTG_EN); // Power down OTG
       
   114 			break;
       
   115 		case DOmap3530Usbcc::EPeripheralChirp:
       
   116 			// OTG device Peripheral chirp			
       
   117 			TPS65950::WriteSync(TPS65950::Register::MCPC_CTRL2_CLR, KMPC_CLK_EN); // Not UART Mode
       
   118 			TPS65950::WriteSync(TPS65950::Register::FUNC_CTRL,(KXCVRSELECT_HS | KTERMSELECT | KOPMODE_MASK )); //Term select 1, opmode 10,  Xcvr Select 00,
       
   119 			TPS65950::WriteSync(TPS65950::Register::MCPC_IO_CTRL_CLR, KRXD_PU);
       
   120 			TPS65950::WriteSync(TPS65950::Register::OTG_CTRL_CLR, KDPPULLDOWN | KDMPULLDOWN); // Disable DP pulldown 
       
   121 			TPS65950::WriteSync(TPS65950::Register::POWER_CTRL_SET, KOTG_EN);
       
   122 			
       
   123 			break;
       
   124 		case DOmap3530Usbcc::EUART:
       
   125 			// UART Mode
       
   126 			TPS65950::WriteSync(TPS65950::Register::MCPC_CTRL2_SET, KMPC_CLK_EN); // Not UART Mode
       
   127 			TPS65950::WriteSync(TPS65950::Register::MCPC_IO_CTRL_SET, KRXD_PU);
       
   128 			break;
       
   129 		default:
       
   130 			// Don't change mode
       
   131 			break;
       
   132 		}
       
   133 	DisablePHY();
       
   134 	}
       
   135 
       
   136 // The PHY 60Mhz clock must be enabled before Register accesses are attempted.
       
   137 void TBeagleUsbPhy::EnablePHY()
       
   138 	{
       
   139 	__KTRACE_OPT(KUSB, Kern::Printf("TBeagleUsbPhy::EnablePHY"));	
       
   140 	if(iPHYEnabled==0)
       
   141 		{		
       
   142 		TPS65950::WriteSync(TPS65950::Register::PHY_CLK_CTRL, KREQ_PHY_DPLL_CLK | KCLK32K_EN);
       
   143 		TUint8 val=0;
       
   144 		TInt retries =0;
       
   145 		do
       
   146 			{
       
   147 			TPS65950::ReadSync(TPS65950::Register::PHY_CLK_CTRL_STS, val);
       
   148 			NKern::Sleep( NKern::TimerTicks( 1 ) );
       
   149 			//Kern::NanoWait(50000); // wait 1/2 millis to prevent soak
       
   150 			retries++;
       
   151 			}
       
   152 		while(! (val & KPHY_DPLL_CLK) && (retries < 1000) );
       
   153 		
       
   154 		__ASSERT_ALWAYS(retries < 1000,Kern::Fault("TBeagleUsbPhy::EnablePHY Cant enable in 5s ",__LINE__));		
       
   155 		__KTRACE_OPT(KUSB, Kern::Printf("TBeagleUsbPhy: PHY Enabled"));
       
   156 		}
       
   157 	iPHYEnabled++;
       
   158 	}
       
   159 	
       
   160 void TBeagleUsbPhy::DisablePHY()
       
   161 	{
       
   162 	__KTRACE_OPT(KUSB, Kern::Printf("TBeagleUsbPhy::DisablePHY"));
       
   163 	if(iPHYEnabled==1)
       
   164 		{
       
   165 		TPS65950::WriteSync(TPS65950::Register::PHY_CLK_CTRL, 0x0);			
       
   166 		}
       
   167 	if(iPHYEnabled>0)
       
   168 		{
       
   169 		iPHYEnabled--;
       
   170 		}
       
   171 	}
       
   172 
       
   173 
       
   174 EXPORT_C MOmap3530UsbPhy* MOmap3530UsbPhy::New()
       
   175 	{
       
   176 	__KTRACE_OPT(KUSB, Kern::Printf(" > Initializing USB PHY"));
       
   177 
       
   178 	TBeagleUsbPhy* const phy = new TBeagleUsbPhy;
       
   179 	if (!phy)
       
   180 		{
       
   181 		__KTRACE_OPT(KPANIC, Kern::Printf("  Error: Memory allocation for TBeagleUsbPhy failed"));
       
   182 		return NULL;
       
   183 		}
       
   184 
       
   185 	TInt r;
       
   186 	if ((r = phy->Construct()) != KErrNone)
       
   187 		{
       
   188 		__KTRACE_OPT(KPANIC, Kern::Printf("  Error: Construction of TBeagleUsbPhy failed (%d)", r));
       
   189 		delete phy;
       
   190 		return NULL;
       
   191 		}
       
   192 
       
   193 	return phy;
       
   194 	}
       
   195 
       
   196 
       
   197 DECLARE_STANDARD_EXTENSION()
       
   198 	{
       
   199 	return KErrNone;
       
   200 	}
       
   201 
       
   202