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1 // Copyright (c) 2004-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // omap3530/beagle_drivers/usb/usbv.cpp |
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15 // |
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16 |
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17 #include <kernel.h> |
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18 #include <assp/omap3530_assp/omap3530_usbc.h> |
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19 // Platform-dependent USB client controller layer (USB PSL). |
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20 #include <assp/omap3530_assp/omap3530_i2c.h> |
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21 #include <assp/omap3530_assp/omap3530_i2creg.h> |
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22 #include <assp/omap3530_shared/tps65950.h> |
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23 |
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24 |
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25 // I2C Bit definitions |
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26 // PHY_CLK_CTRL |
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27 const TUint KCLK32K_EN = KBit1; |
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28 const TUint KREQ_PHY_DPLL_CLK = KBit0; |
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29 // PHY_CLK_STS |
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30 const TUint KPHY_DPLL_CLK = KBit0; |
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31 // MCPC_CTRL2 |
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32 const TUint KMPC_CLK_EN = KBit0; |
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33 // FUNC_CTRL |
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34 const TUint KXCVRSELECT_HS = 0x0; |
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35 const TUint KXCVRSELECT_FS = KBit0; |
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36 const TUint KXCVRSELECT_MASK = 0x3; |
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37 const TUint KTERMSELECT = KBit2; |
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38 const TUint KOPMODE_DISABLED = KBit4; |
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39 const TUint KOPMODE_MASK = KBit3 | KBit4; |
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40 // MCPC_IO_CTRL |
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41 const TUint KRXD_PU = KBit3; |
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42 // OTG_CTRL |
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43 const TUint KDPPULLDOWN = KBit1; |
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44 const TUint KDMPULLDOWN = KBit2; |
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45 // POWER_CTRL |
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46 const TUint KOTG_EN = KBit5; |
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47 // VUSB???_DEV_GRP |
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48 const TUint KDEV_GRP_P1 = KBit5; |
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49 // CFG_BOOT |
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50 const TUint KHFCLK_FREQ_26Mhz = KBit1; |
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51 |
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52 |
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53 NONSHARABLE_CLASS( TBeagleUsbPhy ) : public MOmap3530UsbPhy |
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54 { |
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55 public: |
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56 TBeagleUsbPhy(); |
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57 TInt Construct(); |
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58 |
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59 virtual void StartPHY(); |
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60 virtual void SetPHYMode( DOmap3530Usbcc::TPHYMode aMode ); |
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61 virtual void EnablePHY(); |
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62 virtual void DisablePHY(); |
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63 |
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64 private: |
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65 TInt iPHYEnabled; |
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66 }; |
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67 |
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68 |
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69 |
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70 TBeagleUsbPhy::TBeagleUsbPhy() |
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71 { |
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72 } |
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73 |
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74 TInt TBeagleUsbPhy::Construct() |
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75 { |
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76 return KErrNone; |
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77 } |
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78 |
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79 |
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80 void TBeagleUsbPhy::StartPHY() |
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81 { |
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82 // PHY clock must be enabled before this point (can't enable it in this function as it is called from an ISR context) |
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83 TPS65950::DisableProtect(); |
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84 |
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85 // Enable the USB LDO's (low-dropout regulators) |
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86 TPS65950::ClearSetSync(TPS65950::Register::VUSB1V5_DEV_GRP,0x00,KDEV_GRP_P1); |
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87 TPS65950::ClearSetSync(TPS65950::Register::VUSB1V8_DEV_GRP,0x00,KDEV_GRP_P1); |
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88 TPS65950::ClearSetSync(TPS65950::Register::VUSB3V1_DEV_GRP,0x00,KDEV_GRP_P1); |
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89 |
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90 TPS65950::ClearSetSync(TPS65950::Register::CFG_BOOT,0x00, KHFCLK_FREQ_26Mhz); |
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91 |
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92 TPS65950::RestoreProtect(); |
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93 } |
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94 |
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95 void TBeagleUsbPhy::SetPHYMode( DOmap3530Usbcc::TPHYMode aMode ) |
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96 { |
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97 EnablePHY(); |
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98 switch(aMode) |
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99 { |
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100 // Configure trancever (see swcu05b.pdf table 15-21 D+/D- Termination settings) |
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101 case DOmap3530Usbcc::ENormal: |
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102 TPS65950::WriteSync(TPS65950::Register::MCPC_CTRL2_CLR, KMPC_CLK_EN); // Not UART Mode |
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103 TPS65950::WriteSync(TPS65950::Register::FUNC_CTRL_CLR,(KXCVRSELECT_MASK | KTERMSELECT | KOPMODE_DISABLED )); // XCVRSELECT high speed mode (HS), TERM SELECT=0, OPMODE=0 (normal operation) |
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104 TPS65950::WriteSync(TPS65950::Register::MCPC_IO_CTRL_CLR, KRXD_PU); |
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105 TPS65950::WriteSync(TPS65950::Register::OTG_CTRL_CLR, KDPPULLDOWN | KDMPULLDOWN); // Disable DP pulldown |
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106 TPS65950::WriteSync(TPS65950::Register::POWER_CTRL_SET, KOTG_EN); |
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107 break; |
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108 case DOmap3530Usbcc::EPowerUp: |
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109 // Power up or VBUS<VSESSEND |
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110 TPS65950::WriteSync(TPS65950::Register::MCPC_CTRL2_CLR, KMPC_CLK_EN); // Not UART Mode |
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111 TPS65950::WriteSync(TPS65950::Register::FUNC_CTRL, KXCVRSELECT_FS); // XXcvr Select 01, Term select 0, opmode 0, |
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112 TPS65950::WriteSync(TPS65950::Register::OTG_CTRL_SET, KDPPULLDOWN | KDMPULLDOWN); // Disable DP pulldown |
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113 TPS65950::WriteSync(TPS65950::Register::POWER_CTRL_CLR, KOTG_EN); // Power down OTG |
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114 break; |
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115 case DOmap3530Usbcc::EPeripheralChirp: |
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116 // OTG device Peripheral chirp |
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117 TPS65950::WriteSync(TPS65950::Register::MCPC_CTRL2_CLR, KMPC_CLK_EN); // Not UART Mode |
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118 TPS65950::WriteSync(TPS65950::Register::FUNC_CTRL,(KXCVRSELECT_HS | KTERMSELECT | KOPMODE_MASK )); //Term select 1, opmode 10, Xcvr Select 00, |
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119 TPS65950::WriteSync(TPS65950::Register::MCPC_IO_CTRL_CLR, KRXD_PU); |
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120 TPS65950::WriteSync(TPS65950::Register::OTG_CTRL_CLR, KDPPULLDOWN | KDMPULLDOWN); // Disable DP pulldown |
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121 TPS65950::WriteSync(TPS65950::Register::POWER_CTRL_SET, KOTG_EN); |
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122 |
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123 break; |
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124 case DOmap3530Usbcc::EUART: |
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125 // UART Mode |
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126 TPS65950::WriteSync(TPS65950::Register::MCPC_CTRL2_SET, KMPC_CLK_EN); // Not UART Mode |
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127 TPS65950::WriteSync(TPS65950::Register::MCPC_IO_CTRL_SET, KRXD_PU); |
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128 break; |
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129 default: |
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130 // Don't change mode |
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131 break; |
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132 } |
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133 DisablePHY(); |
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134 } |
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135 |
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136 // The PHY 60Mhz clock must be enabled before Register accesses are attempted. |
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137 void TBeagleUsbPhy::EnablePHY() |
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138 { |
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139 __KTRACE_OPT(KUSB, Kern::Printf("TBeagleUsbPhy::EnablePHY")); |
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140 if(iPHYEnabled==0) |
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141 { |
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142 TPS65950::WriteSync(TPS65950::Register::PHY_CLK_CTRL, KREQ_PHY_DPLL_CLK | KCLK32K_EN); |
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143 TUint8 val=0; |
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144 TInt retries =0; |
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145 do |
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146 { |
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147 TPS65950::ReadSync(TPS65950::Register::PHY_CLK_CTRL_STS, val); |
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148 NKern::Sleep( NKern::TimerTicks( 1 ) ); |
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149 //Kern::NanoWait(50000); // wait 1/2 millis to prevent soak |
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150 retries++; |
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151 } |
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152 while(! (val & KPHY_DPLL_CLK) && (retries < 1000) ); |
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153 |
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154 __ASSERT_ALWAYS(retries < 1000,Kern::Fault("TBeagleUsbPhy::EnablePHY Cant enable in 5s ",__LINE__)); |
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155 __KTRACE_OPT(KUSB, Kern::Printf("TBeagleUsbPhy: PHY Enabled")); |
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156 } |
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157 iPHYEnabled++; |
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158 } |
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159 |
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160 void TBeagleUsbPhy::DisablePHY() |
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161 { |
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162 __KTRACE_OPT(KUSB, Kern::Printf("TBeagleUsbPhy::DisablePHY")); |
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163 if(iPHYEnabled==1) |
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164 { |
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165 TPS65950::WriteSync(TPS65950::Register::PHY_CLK_CTRL, 0x0); |
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166 } |
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167 if(iPHYEnabled>0) |
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168 { |
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169 iPHYEnabled--; |
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170 } |
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171 } |
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172 |
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173 |
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174 EXPORT_C MOmap3530UsbPhy* MOmap3530UsbPhy::New() |
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175 { |
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176 __KTRACE_OPT(KUSB, Kern::Printf(" > Initializing USB PHY")); |
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177 |
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178 TBeagleUsbPhy* const phy = new TBeagleUsbPhy; |
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179 if (!phy) |
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180 { |
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181 __KTRACE_OPT(KPANIC, Kern::Printf(" Error: Memory allocation for TBeagleUsbPhy failed")); |
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182 return NULL; |
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183 } |
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184 |
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185 TInt r; |
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186 if ((r = phy->Construct()) != KErrNone) |
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187 { |
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188 __KTRACE_OPT(KPANIC, Kern::Printf(" Error: Construction of TBeagleUsbPhy failed (%d)", r)); |
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189 delete phy; |
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190 return NULL; |
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191 } |
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192 |
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193 return phy; |
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194 } |
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195 |
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196 |
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197 DECLARE_STANDARD_EXTENSION() |
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198 { |
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199 return KErrNone; |
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200 } |
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201 |
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202 |