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1 // Copyright (c) 1994-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // omap3530/omap3530_drivers/gpio/gpio.cpp |
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15 // |
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16 |
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17 #include <kern_priv.h> |
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18 #include <assp/omap3530_assp/omap3530_gpio.h> |
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19 #include <assp/omap3530_assp/omap3530_hardware_base.h> |
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20 #include <assp/omap3530_assp/omap3530_irqmap.h> |
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21 |
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22 #include <assp.h> |
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23 //#include <nkern.h> |
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24 #include <assp/omap3530_assp/gpio.h> |
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25 |
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26 GLREF_C TInt InitGpioInterrupts(); |
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27 |
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28 |
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29 TSpinLock GPIOModeLock(/*TSpinLock::EOrderNone*/); |
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30 TSpinLock GPIOWakeLock(/*TSpinLock::EOrderNone*/); |
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31 TSpinLock GPIOLevelLock(/*TSpinLock::EOrderNone*/); |
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32 |
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33 GPIO::TGpioMode ThePinMode[ KHwGpioPinMax ]; |
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34 TUint32 ThePinIsEnabled[ KHwGpioBanks ]; |
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35 __ASSERT_COMPILE( KHwGpioPinsPerBank <= 32 ); |
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36 |
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37 #if 0 |
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38 static void dumpGpioBank(TUint aBankAddr) |
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39 { |
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40 Kern::Printf("GPIO_SYSCONFIG at %x is %x",aBankAddr +KGPIO_SYSCONFIG,AsspRegister::Read32(aBankAddr +KGPIO_SYSCONFIG) ); |
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41 Kern::Printf("GPIO_SYSSTATUS at %x is %x",aBankAddr +KGPIO_SYSSTATUS,AsspRegister::Read32(aBankAddr +KGPIO_SYSSTATUS)); |
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42 Kern::Printf("GPIO_IRQSTATUS1 at %x is %x",aBankAddr +KGPIO_IRQSTATUS1,AsspRegister::Read32(aBankAddr +KGPIO_IRQSTATUS1) ); |
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43 Kern::Printf("GPIO_IRQENABLE1 at %x is %x",aBankAddr +KGPIO_IRQENABLE1,AsspRegister::Read32(aBankAddr +KGPIO_IRQENABLE1) ); |
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44 Kern::Printf("GPIO_WAKEUPENABLE at %x is %x",aBankAddr +KGPIO_WAKEUPENABLE,AsspRegister::Read32(aBankAddr +KGPIO_WAKEUPENABLE) ); |
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45 Kern::Printf("GPIO_CTRL at %x is %x",aBankAddr +KGPIO_CTRL,AsspRegister::Read32(aBankAddr +KGPIO_CTRL) ); |
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46 Kern::Printf("GPIO_OE at %x is %x",aBankAddr +KGPIO_CTRL,AsspRegister::Read32(aBankAddr +KGPIO_OE) ); |
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47 } |
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48 #endif |
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49 |
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50 |
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51 EXPORT_C TInt GPIO::SetPinMode(TInt aId, TGpioMode aMode) |
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52 { |
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53 TInt irq = __SPIN_LOCK_IRQSAVE(GPIOModeLock); |
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54 if(ThePinMode[ aId ] != aMode) |
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55 { |
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56 ThePinMode[ aId ] = aMode; |
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57 TUint bank = GPIO_PIN_BANK( aId ); |
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58 TUint pinMask = 1 << GPIO_PIN_OFFSET( aId ); |
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59 |
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60 if( aMode == GPIO::EEnabled) |
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61 { |
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62 if( 0 == ThePinIsEnabled[ bank ] ) |
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63 { |
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64 // First enabled pin in bank |
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65 AsspRegister::Modify32(GPIO_BASE_ADDRESS( aId ) +KGPIO_CTRL,KClearNone,0x1); |
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66 } |
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67 |
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68 ThePinIsEnabled[ bank ] |= pinMask; |
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69 } |
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70 else |
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71 { |
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72 ThePinIsEnabled[ bank ] &= ~pinMask; |
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73 |
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74 if( 0 == ThePinIsEnabled[ bank ] ) |
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75 { |
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76 // Bank can be disabled |
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77 AsspRegister::Modify32(GPIO_BASE_ADDRESS( aId ) +KGPIO_CTRL,0x1, KSetNone); |
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78 } |
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79 } |
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80 } |
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81 __SPIN_UNLOCK_IRQRESTORE(GPIOModeLock,irq); |
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82 return KErrNone; |
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83 } |
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84 |
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85 EXPORT_C TInt GPIO::GetPinMode(TInt aId, TGpioMode & aMode) |
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86 { |
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87 aMode = ThePinMode[ aId ]; |
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88 return KErrNone; |
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89 } |
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90 |
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91 EXPORT_C TInt GPIO::SetPinDirection(TInt aId, TGpioDirection aDirection) |
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92 { |
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93 __ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::SetPinBias OOB ",KErrArgument)); |
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94 |
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95 if (aDirection == ETriStated) |
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96 { |
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97 return KErrNotSupported; |
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98 } |
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99 |
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100 if (aDirection == EInput) |
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101 { |
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102 AsspRegister::Modify32(GPIO_BASE_ADDRESS(aId)+KGPIO_OE, KClearNone, GPIO_PIN_OFFSET(aId)); |
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103 } |
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104 else |
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105 { |
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106 AsspRegister::Modify32(GPIO_BASE_ADDRESS(aId)+KGPIO_OE, GPIO_PIN_OFFSET(aId), KSetNone); |
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107 } |
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108 return KErrNone; |
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109 } |
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110 |
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111 EXPORT_C TInt GPIO::GetPinDirection(TInt aId, TGpioDirection& aDirection) |
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112 { |
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113 __ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::GetPinDirection OOB ",KErrArgument)); |
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114 |
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115 if(AsspRegister::Read32(GPIO_BASE_ADDRESS(aId)+KGPIO_OE) & GPIO_PIN_OFFSET(aId)) |
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116 aDirection=EInput; |
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117 else |
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118 aDirection=EOutput; |
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119 |
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120 return KErrNone; |
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121 } |
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122 |
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123 EXPORT_C TInt GPIO::SetPinBias(TInt aId, TGpioBias aBias) |
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124 { |
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125 __ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::SetPinBias OOB ",KErrArgument)); |
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126 return KErrNotSupported; |
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127 } |
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128 |
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129 EXPORT_C TInt GPIO::GetPinBias(TInt aId, TGpioBias& aBias) |
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130 { |
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131 __ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::GetPinBias OOB ",KErrArgument)); |
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132 return KErrNotSupported; |
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133 } |
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134 |
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135 EXPORT_C TInt GPIO::SetPinIdleConfigurationAndState(TInt aId, TInt /*aConf*/) |
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136 { |
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137 __ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::SetPinIdleConfigurationAndState OOB ",KErrArgument)); |
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138 return KErrNotSupported; |
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139 } |
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140 |
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141 EXPORT_C TInt GPIO::GetPinIdleConfigurationAndState(TInt aId, TInt& aBias) |
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142 { |
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143 __ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::GetPinIdleConfigurationAndState OOB ",KErrArgument)); |
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144 return KErrNotSupported; |
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145 } |
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146 |
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147 EXPORT_C TInt GPIO::BindInterrupt(TInt aId, TGpioIsr aIsr, TAny* aPtr) |
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148 { |
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149 return Interrupt::Bind( EGPIOIRQ_FIRST + aId,aIsr,aPtr); |
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150 } |
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151 |
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152 EXPORT_C TInt GPIO::UnbindInterrupt(TInt aId) |
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153 { |
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154 return Interrupt::Unbind( EGPIOIRQ_FIRST + aId ); |
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155 } |
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156 |
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157 EXPORT_C TInt GPIO::EnableInterrupt(TInt aId) |
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158 { |
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159 return Interrupt::Enable( EGPIOIRQ_FIRST + aId ); |
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160 } |
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161 |
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162 EXPORT_C TInt GPIO::DisableInterrupt(TInt aId) |
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163 { |
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164 return Interrupt::Disable( EGPIOIRQ_FIRST + aId ); |
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165 } |
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166 |
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167 EXPORT_C TInt GPIO::ClearInterrupt(TInt aId) |
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168 { |
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169 return Interrupt::Clear( EGPIOIRQ_FIRST + aId ); |
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170 } |
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171 |
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172 EXPORT_C TInt GPIO::IsInterruptEnabled(TInt aId, TBool& aEnable) |
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173 { |
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174 aEnable = AsspRegister::Read32(GPIO_BASE_ADDRESS( aId ) + KGPIO_IRQENABLE1) & GPIO_PIN_OFFSET(aId); |
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175 return KErrNone; |
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176 } |
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177 |
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178 EXPORT_C TInt GPIO::GetMaskedInterruptState(TInt aId, TBool& aActive) |
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179 { |
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180 __ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::GetMaskedInterruptState OOB ",KErrArgument)); |
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181 aActive = AsspRegister::Read32(GPIO_BASE_ADDRESS(aId)+KGPIO_IRQSTATUS1) & GPIO_PIN_OFFSET(aId); |
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182 |
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183 return KErrNone; |
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184 } |
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185 |
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186 EXPORT_C TInt GPIO::GetRawInterruptState(TInt aId, TBool& aActive) |
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187 { |
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188 __ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::GetRawInterruptState OOB ",KErrArgument)); |
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189 |
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190 aActive = AsspRegister::Read32(GPIO_BASE_ADDRESS(aId)+KGPIO_IRQSTATUS1) & GPIO_PIN_OFFSET(aId); |
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191 |
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192 return KErrNone; |
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193 } |
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194 |
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195 EXPORT_C TInt GPIO::SetInterruptTrigger(TInt aId, TGpioDetectionTrigger aTrigger) |
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196 { |
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197 __ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::SetInterruptTrigger OOB ",KErrArgument)); |
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198 |
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199 TInt baseAddr = GPIO_BASE_ADDRESS(aId); |
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200 TUint irqFlags=0; |
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201 //first we clear the current trigger(s) |
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202 //then set the new for each case |
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203 switch (aTrigger) |
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204 { |
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205 case ELevelLow: |
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206 |
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207 irqFlags = NKern::DisableAllInterrupts();//__SPIN_LOCK_IRQSAVE_W(GPIOLevelSpinLock); |
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208 AsspRegister::Modify32(baseAddr+KGPIO_LEVELDETECT1, GPIO_PIN_OFFSET(aId),KSetNone); |
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209 AsspRegister::Modify32(baseAddr+KGPIO_FALLINGDETECT, GPIO_PIN_OFFSET(aId),KSetNone); |
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210 AsspRegister::Modify32(baseAddr+KGPIO_RISINGDETECT, GPIO_PIN_OFFSET(aId),KSetNone); |
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211 |
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212 AsspRegister::Modify32(baseAddr+KGPIO_LEVELDETECT0, KClearNone, GPIO_PIN_OFFSET(aId)); |
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213 NKern::RestoreInterrupts(irqFlags);//__SPIN_UNLOCK_IRQRESTORE_W(GPIOLevelSpinLock,irqFlags); |
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214 break; |
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215 case ELevelHigh: |
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216 |
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217 irqFlags = NKern::DisableAllInterrupts();//__SPIN_LOCK_IRQSAVE_W(GPIOLevelSpinLock); |
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218 AsspRegister::Modify32(baseAddr+KGPIO_LEVELDETECT0, GPIO_PIN_OFFSET(aId),KSetNone); |
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219 AsspRegister::Modify32(baseAddr+KGPIO_FALLINGDETECT, GPIO_PIN_OFFSET(aId),KSetNone); |
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220 AsspRegister::Modify32(baseAddr+KGPIO_RISINGDETECT, GPIO_PIN_OFFSET(aId),KSetNone); |
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221 |
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222 AsspRegister::Modify32(baseAddr+KGPIO_LEVELDETECT1, KClearNone, GPIO_PIN_OFFSET(aId)); |
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223 NKern::RestoreInterrupts(irqFlags);//__SPIN_UNLOCK_IRQRESTORE_W(GPIOLevelSpinLock,irqFlags); |
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224 |
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225 break; |
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226 case EEdgeFalling: |
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227 |
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228 irqFlags = NKern::DisableAllInterrupts();//__SPIN_LOCK_IRQSAVE_W(GPIOLevelSpinLock); |
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229 AsspRegister::Modify32(baseAddr+KGPIO_LEVELDETECT0, GPIO_PIN_OFFSET(aId),KSetNone); |
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230 AsspRegister::Modify32(baseAddr+KGPIO_LEVELDETECT1, GPIO_PIN_OFFSET(aId),KSetNone); |
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231 AsspRegister::Modify32(baseAddr+KGPIO_RISINGDETECT, GPIO_PIN_OFFSET(aId),KSetNone); |
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232 |
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233 AsspRegister::Modify32(baseAddr+KGPIO_FALLINGDETECT, KClearNone, GPIO_PIN_OFFSET(aId)); |
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234 NKern::RestoreInterrupts(irqFlags);//__SPIN_UNLOCK_IRQRESTORE_W(GPIOLevelSpinLock,irqFlags); |
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235 break; |
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236 case EEdgeRising: |
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237 |
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238 irqFlags = NKern::DisableAllInterrupts();//__SPIN_LOCK_IRQSAVE_W(GPIOLevelSpinLock); |
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239 AsspRegister::Modify32(baseAddr+KGPIO_LEVELDETECT0, GPIO_PIN_OFFSET(aId),KSetNone); |
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240 AsspRegister::Modify32(baseAddr+KGPIO_LEVELDETECT1, GPIO_PIN_OFFSET(aId),KSetNone); |
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241 AsspRegister::Modify32(baseAddr+KGPIO_FALLINGDETECT, GPIO_PIN_OFFSET(aId),KSetNone); |
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242 |
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243 AsspRegister::Modify32(baseAddr+KGPIO_RISINGDETECT, KClearNone, GPIO_PIN_OFFSET(aId)); |
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244 NKern::RestoreInterrupts(irqFlags);//__SPIN_UNLOCK_IRQRESTORE_W(GPIOLevelSpinLock,irqFlags); |
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245 break; |
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246 case EEdgeBoth: |
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247 |
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248 irqFlags = NKern::DisableAllInterrupts();//__SPIN_LOCK_IRQSAVE_W(GPIOLevelSpinLock); |
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249 AsspRegister::Modify32(baseAddr+KGPIO_LEVELDETECT0, GPIO_PIN_OFFSET(aId),KSetNone); |
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250 AsspRegister::Modify32(baseAddr+KGPIO_LEVELDETECT1, GPIO_PIN_OFFSET(aId),KSetNone); |
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251 |
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252 AsspRegister::Modify32(baseAddr+KGPIO_FALLINGDETECT, KClearNone, GPIO_PIN_OFFSET(aId)); |
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253 AsspRegister::Modify32(baseAddr+KGPIO_RISINGDETECT, KClearNone, GPIO_PIN_OFFSET(aId)); |
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254 NKern::RestoreInterrupts(irqFlags);//__SPIN_UNLOCK_IRQRESTORE_W(GPIOLevelSpinLock,irqFlags); |
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255 |
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256 break; |
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257 default: |
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258 return KErrArgument; |
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259 } |
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260 |
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261 return KErrNone; |
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262 } |
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263 |
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264 |
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265 EXPORT_C TInt GPIO::EnableWakeup(TInt aId) |
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266 { |
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267 __ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::EnableWakeup OOB ",KErrArgument)); |
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268 |
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269 TInt baseAddr = GPIO_BASE_ADDRESS(aId); |
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270 |
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271 TInt irq = __SPIN_LOCK_IRQSAVE(GPIOWakeLock); |
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272 AsspRegister::Modify32(baseAddr+KGPIO_SYSCONFIG,KClearNone, 1 << 2 ); |
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273 AsspRegister::Modify32(baseAddr+KGPIO_SETWKUENA,KClearNone ,GPIO_PIN_OFFSET(aId)); |
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274 __SPIN_UNLOCK_IRQRESTORE(GPIOWakeLock,irq); |
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275 |
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276 return KErrNone; |
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277 } |
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278 |
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279 EXPORT_C TInt GPIO::DisableWakeup(TInt aId) |
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280 { |
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281 __ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::DisableWakeup OOB ",KErrArgument)); |
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282 |
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283 TInt baseAddr = GPIO_BASE_ADDRESS(aId); |
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284 |
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285 TInt irq = __SPIN_LOCK_IRQSAVE(GPIOWakeLock); |
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286 AsspRegister::Modify32(baseAddr+KGPIO_SYSCONFIG,1 << 2 ,KSetNone); |
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287 AsspRegister::Modify32(baseAddr+KGPIO_CLEARWKUENA,KClearNone,GPIO_PIN_OFFSET(aId)); |
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288 __SPIN_UNLOCK_IRQRESTORE(GPIOWakeLock,irq); |
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289 return KErrNone; |
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290 } |
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291 |
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292 EXPORT_C TInt GPIO::IsWakeupEnabled(TInt aId, TBool& aEnable) |
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293 { |
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294 __ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::IsWakeupEnabled OOB ",KErrArgument)); |
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295 |
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296 aEnable = AsspRegister::Read32(GPIO_BASE_ADDRESS(aId)+KGPIO_WAKEUPENABLE) & GPIO_PIN_OFFSET(aId); |
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297 return KErrNone; |
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298 } |
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299 |
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300 EXPORT_C TInt GPIO::SetWakeupTrigger(TInt aId, TGpioDetectionTrigger aTrigger) |
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301 { |
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302 __ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::SetWakeupTrigger OOB ",KErrArgument)); |
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303 return KErrNotSupported; |
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304 } |
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305 |
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306 // WARNING: Changing debouncing time will change it for all pins in the bank |
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307 EXPORT_C TInt GPIO::SetDebounceTime(TInt aId, TInt aTime) |
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308 { |
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309 TGpioDirection direction; |
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310 GetPinDirection(aId, direction); |
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311 |
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312 if(direction==EOutput) |
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313 { |
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314 // The pin must be configured as input. |
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315 return KErrNotSupported; |
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316 } |
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317 |
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318 //convert the Ms input time into units of 31us |
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319 TInt timeSteps = aTime / 31; |
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320 if(timeSteps>127) |
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321 { |
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322 #ifdef _DEBUG |
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323 Kern::Printf("Warning: Tried to set the GPIO debounce time to %dus, \ |
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324 which is greater than the maximum supported 3937us.", aTime); |
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325 #endif |
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326 timeSteps=127; // The maximum debounce value. |
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327 } |
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328 |
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329 TInt baseAddr = GPIO_BASE_ADDRESS(aId); |
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330 |
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331 TUint irqFlags = __SPIN_LOCK_IRQSAVE(gpio::GPIODebounceSpinLock); |
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332 AsspRegister::Write32(baseAddr+KGPIO_DEBOUNCINGTIME, timeSteps & KGPIO_DEBOUNCE_TIME_MASK); |
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333 AsspRegister::Modify32(baseAddr+KGPIO_DEBOUNCENABLE, KClearNone, GPIO_PIN_OFFSET(aId)); |
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334 __SPIN_UNLOCK_IRQRESTORE(gpio::GPIODebounceSpinLock,irqFlags); |
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335 |
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336 return KErrNone; |
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337 } |
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338 |
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339 EXPORT_C TInt GPIO::GetDebounceTime(TInt aId, TInt& aTime) |
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340 { |
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341 __ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::GetDebounceTime OOB ",KErrArgument)); |
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342 aTime=AsspRegister::Read32(GPIO_BASE_ADDRESS(aId)+KGPIO_DEBOUNCINGTIME); // The time in in multiples of 31 microseconds. We should probably use a nicer unit.. |
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343 |
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344 return KErrNone; |
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345 } |
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346 |
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347 EXPORT_C TInt GPIO::SetOutputState(TInt aId, TGpioState aState) |
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348 { |
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349 if(aState==GPIO::ELow) |
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350 { |
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351 AsspRegister::Modify32(GPIO_BASE_ADDRESS(aId) + KGPIO_DATAOUT, GPIO_PIN_OFFSET(aId), KSetNone); |
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352 } |
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353 else |
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354 { |
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355 AsspRegister::Modify32(GPIO_BASE_ADDRESS(aId) + KGPIO_DATAOUT, KClearNone, GPIO_PIN_OFFSET(aId)); |
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356 } |
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357 return KErrNone; |
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358 } |
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359 |
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360 EXPORT_C TInt GPIO::GetInputState(TInt aId, TGpioState& aState) |
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361 { |
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362 __ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::GetInputState OOB ",KErrArgument)); |
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363 |
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364 aState= ( AsspRegister::Read32(GPIO_BASE_ADDRESS(aId) + KGPIO_DATAIN) & GPIO_PIN_OFFSET(aId) ? |
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365 GPIO::EHigh: |
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366 GPIO::ELow); |
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367 |
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368 return KErrNone; |
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369 } |
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370 |
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371 EXPORT_C TInt GPIO::GetOutputState(TInt aId, TGpioState& aState) |
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372 { |
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373 __ASSERT_ALWAYS(GPIO_PIN_BOUNDS(aId),Kern::Fault(" GPIO::GetOutputState OOB ",KErrArgument)); |
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374 |
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375 aState = (AsspRegister::Read32(GPIO_BASE_ADDRESS(aId)+KGPIO_DATAOUT)& GPIO_PIN_OFFSET(aId) ? |
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376 aState=GPIO::EHigh: |
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377 aState=GPIO::ELow); |
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378 return KErrNone; |
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379 } |
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380 |
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381 EXPORT_C TInt GPIO::GetInputState(TInt aId, TGpioCallback* /*aCb*/) |
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382 { |
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383 return KErrNotSupported; |
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384 } |
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385 |
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386 EXPORT_C TInt GPIO::SetOutputState(TInt aId, TGpioState aState, TGpioCallback* /*aCb*/) |
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387 { |
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388 return KErrNotSupported; |
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389 } |
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390 |
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391 |
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392 DECLARE_STANDARD_EXTENSION() |
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393 { |
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394 |
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395 TInt i=0; |
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396 for(;i<KHwGpioBanks;i++) |
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397 { |
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398 //spins here |
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399 AsspRegister::Write32(GPIO_BASE_ADDRESS(i*KHwGpioPinsPerBank)+KGPIO_SYSCONFIG,0x01 | 1 <<2); |
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400 AsspRegister::Write32(GPIO_BASE_ADDRESS(i*KHwGpioPinsPerBank)+KGPIO_CTRL,0x00); |
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401 ThePinIsEnabled[i]=0; |
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402 } |
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403 |
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404 for(i=0; i<KHwGpioPinMax; i++) |
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405 { |
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406 //ThePinMode[ i ]=GPIO::EIdle; |
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407 } |
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408 return InitGpioInterrupts(); |
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409 } |