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1 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // omap3530/omap3530_drivers/gpio/omap3530_gpio.h |
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15 // This file is part of the Beagle Base port |
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16 // |
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17 |
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18 #ifndef __OMAP3530_GPIO_H__ |
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19 #define __OMAP3530_GPIO_H__ |
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20 |
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21 #include <assp/omap3530_assp/omap3530_hardware_base.h> |
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22 #include <assp/omap3530_assp/omap3530_irqmap.h> |
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23 //#include <drivers/gpio.h> |
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24 |
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25 #include <assp/omap3530_assp/gpio.h> |
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26 #include <assp.h> |
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27 |
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28 const TUint KGPIO1 = Omap3530HwBase::TVirtual<0x48310000>::Value; |
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29 const TUint KGPIO2 = Omap3530HwBase::TVirtual<0x49050000>::Value; |
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30 const TUint KGPIO3 = Omap3530HwBase::TVirtual<0x49052000>::Value; |
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31 const TUint KGPIO4 = Omap3530HwBase::TVirtual<0x49054000>::Value; |
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32 const TUint KGPIO5 = Omap3530HwBase::TVirtual<0x49056000>::Value; |
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33 const TUint KGPIO6 = Omap3530HwBase::TVirtual<0x49058000>::Value; |
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34 |
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35 |
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36 const TUint KGPIO_REVISION = 0x000; |
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37 const TUint KGPIO_SYSCONFIG = 0x010; |
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38 const TUint KGPIO_SYSSTATUS = 0x014; |
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39 const TUint KGPIO_IRQSTATUS1 = 0x018; |
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40 const TUint KGPIO_IRQENABLE1 = 0x01C; |
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41 const TUint KGPIO_WAKEUPENABLE = 0x020; |
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42 const TUint KGPIO_IRQSTATUS2 = 0x028; |
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43 const TUint KGPIO_IRQENABLE2 = 0x02C; |
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44 const TUint KGPIO_CTRL = 0x030; |
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45 const TUint KGPIO_OE = 0x034; |
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46 const TUint KGPIO_DATAIN = 0x038; |
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47 const TUint KGPIO_DATAOUT = 0x03C; |
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48 const TUint KGPIO_LEVELDETECT0 = 0x040; |
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49 const TUint KGPIO_LEVELDETECT1 = 0x044; |
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50 const TUint KGPIO_RISINGDETECT = 0x048; |
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51 const TUint KGPIO_FALLINGDETECT = 0x04C; |
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52 const TUint KGPIO_DEBOUNCENABLE = 0x050; |
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53 const TUint KGPIO_DEBOUNCINGTIME = 0x054; |
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54 const TUint KGPIO_CLEARIRQENABLE1 = 0x060; |
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55 const TUint KGPIO_SETIRQENABLE1 = 0x064; |
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56 const TUint KGPIO_CLEARIRQENABLE2 = 0x070; |
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57 const TUint KGPIO_SETIRQENABLE2 = 0x074; |
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58 const TUint KGPIO_CLEARWKUENA = 0x080; |
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59 const TUint KGPIO_SETWKUENA = 0x084; |
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60 const TUint KGPIO_CLEARDATAOUT = 0x090; |
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61 const TUint KGPIO_SETDATAOUT = 0x094; |
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62 |
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63 const TUint KGPIO_DEBOUNCE_TIME_MASK = 0xF; |
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64 |
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65 |
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66 enum TGPIO_InterruptId |
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67 { |
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68 EGPIOIRQ_FIRST = (EIrqRangeBaseGpio << KIrqRangeIndexShift), |
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69 EGPIOIRQ_PIN_0 = EGPIOIRQ_FIRST, |
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70 EGPIOIRQ_PIN_1, |
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71 EGPIOIRQ_PIN_2, |
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72 EGPIOIRQ_PIN_3, |
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73 EGPIOIRQ_PIN_4, |
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74 EGPIOIRQ_PIN_5, |
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75 EGPIOIRQ_PIN_6, |
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76 EGPIOIRQ_PIN_7, |
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77 EGPIOIRQ_PIN_8, |
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78 EGPIOIRQ_PIN_9, |
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79 EGPIOIRQ_PIN_10, |
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80 EGPIOIRQ_PIN_11, |
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81 EGPIOIRQ_PIN_12, |
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82 EGPIOIRQ_PIN_13, |
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83 EGPIOIRQ_PIN_14, |
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84 EGPIOIRQ_PIN_15, |
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85 EGPIOIRQ_PIN_16, |
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86 EGPIOIRQ_PIN_17, |
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87 EGPIOIRQ_PIN_18, |
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88 EGPIOIRQ_PIN_19, |
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89 EGPIOIRQ_PIN_20, |
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90 EGPIOIRQ_PIN_21, |
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91 EGPIOIRQ_PIN_22, |
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92 EGPIOIRQ_PIN_23, |
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93 EGPIOIRQ_PIN_24, |
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94 EGPIOIRQ_PIN_25, |
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95 EGPIOIRQ_PIN_26, |
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96 EGPIOIRQ_PIN_27, |
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97 EGPIOIRQ_PIN_28, |
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98 EGPIOIRQ_PIN_29, |
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99 EGPIOIRQ_PIN_30, |
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100 EGPIOIRQ_PIN_31, |
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101 EGPIOIRQ_PIN_32, |
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102 EGPIOIRQ_PIN_33, |
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103 EGPIOIRQ_PIN_34, |
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104 EGPIOIRQ_PIN_35, |
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105 EGPIOIRQ_PIN_36, |
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106 EGPIOIRQ_PIN_37, |
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107 EGPIOIRQ_PIN_38, |
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108 EGPIOIRQ_PIN_39, |
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109 EGPIOIRQ_PIN_40, |
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110 EGPIOIRQ_PIN_41, |
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111 EGPIOIRQ_PIN_42, |
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112 EGPIOIRQ_PIN_43, |
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113 EGPIOIRQ_PIN_44, |
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114 EGPIOIRQ_PIN_45, |
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115 EGPIOIRQ_PIN_46, |
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116 EGPIOIRQ_PIN_47, |
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117 EGPIOIRQ_PIN_48, |
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118 EGPIOIRQ_PIN_49, |
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119 EGPIOIRQ_PIN_50, |
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120 EGPIOIRQ_PIN_51, |
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121 EGPIOIRQ_PIN_52, |
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122 EGPIOIRQ_PIN_53, |
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123 EGPIOIRQ_PIN_54, |
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124 EGPIOIRQ_PIN_55, |
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125 EGPIOIRQ_PIN_56, |
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126 EGPIOIRQ_PIN_57, |
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127 EGPIOIRQ_PIN_58, |
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128 EGPIOIRQ_PIN_59, |
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129 EGPIOIRQ_PIN_60, |
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130 EGPIOIRQ_PIN_61, |
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131 EGPIOIRQ_PIN_62, |
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132 EGPIOIRQ_PIN_63, |
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133 EGPIOIRQ_PIN_64, |
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134 EGPIOIRQ_PIN_65, |
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135 EGPIOIRQ_PIN_66, |
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136 EGPIOIRQ_PIN_67, |
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137 EGPIOIRQ_PIN_68, |
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138 EGPIOIRQ_PIN_69, |
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139 EGPIOIRQ_PIN_70, |
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140 EGPIOIRQ_PIN_71, |
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141 EGPIOIRQ_PIN_72, |
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142 EGPIOIRQ_PIN_73, |
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143 EGPIOIRQ_PIN_74, |
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144 EGPIOIRQ_PIN_75, |
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145 EGPIOIRQ_PIN_76, |
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146 EGPIOIRQ_PIN_77, |
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147 EGPIOIRQ_PIN_78, |
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148 EGPIOIRQ_PIN_79, |
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149 EGPIOIRQ_PIN_80, |
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150 EGPIOIRQ_PIN_81, |
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151 EGPIOIRQ_PIN_82, |
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152 EGPIOIRQ_PIN_83, |
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153 EGPIOIRQ_PIN_84, |
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154 EGPIOIRQ_PIN_85, |
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155 EGPIOIRQ_PIN_86, |
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156 EGPIOIRQ_PIN_87, |
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157 EGPIOIRQ_PIN_88, |
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158 EGPIOIRQ_PIN_89, |
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159 EGPIOIRQ_PIN_90, |
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160 EGPIOIRQ_PIN_91, |
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161 EGPIOIRQ_PIN_92, |
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162 EGPIOIRQ_PIN_93, |
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163 EGPIOIRQ_PIN_94, |
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164 EGPIOIRQ_PIN_95, |
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165 EGPIOIRQ_PIN_96, |
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166 EGPIOIRQ_PIN_97, |
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167 EGPIOIRQ_PIN_98, |
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168 EGPIOIRQ_PIN_99, |
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169 EGPIOIRQ_PIN_100, |
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170 EGPIOIRQ_PIN_101, |
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171 EGPIOIRQ_PIN_102, |
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172 EGPIOIRQ_PIN_103, |
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173 EGPIOIRQ_PIN_104, |
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174 EGPIOIRQ_PIN_105, |
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175 EGPIOIRQ_PIN_106, |
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176 EGPIOIRQ_PIN_107, |
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177 EGPIOIRQ_PIN_108, |
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178 EGPIOIRQ_PIN_109, |
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179 EGPIOIRQ_PIN_110, |
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180 EGPIOIRQ_PIN_111, |
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181 EGPIOIRQ_PIN_112, |
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182 EGPIOIRQ_PIN_113, |
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183 EGPIOIRQ_PIN_114, |
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184 EGPIOIRQ_PIN_115, |
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185 EGPIOIRQ_PIN_116, |
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186 EGPIOIRQ_PIN_117, |
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187 EGPIOIRQ_PIN_118, |
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188 EGPIOIRQ_PIN_119, |
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189 EGPIOIRQ_PIN_120, |
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190 EGPIOIRQ_PIN_121, |
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191 EGPIOIRQ_PIN_122, |
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192 EGPIOIRQ_PIN_123, |
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193 EGPIOIRQ_PIN_124, |
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194 EGPIOIRQ_PIN_125, |
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195 EGPIOIRQ_PIN_126, |
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196 EGPIOIRQ_PIN_127, |
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197 EGPIOIRQ_PIN_128, |
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198 EGPIOIRQ_PIN_129, |
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199 EGPIOIRQ_PIN_130, |
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200 EGPIOIRQ_PIN_131, |
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201 EGPIOIRQ_PIN_132, |
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202 EGPIOIRQ_PIN_133, |
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203 EGPIOIRQ_PIN_134, |
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204 EGPIOIRQ_PIN_135, |
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205 EGPIOIRQ_PIN_136, |
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206 EGPIOIRQ_PIN_137, |
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207 EGPIOIRQ_PIN_138, |
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208 EGPIOIRQ_PIN_139, |
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209 EGPIOIRQ_PIN_140, |
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210 EGPIOIRQ_PIN_141, |
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211 EGPIOIRQ_PIN_142, |
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212 EGPIOIRQ_PIN_143, |
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213 EGPIOIRQ_PIN_144, |
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214 EGPIOIRQ_PIN_145, |
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215 EGPIOIRQ_PIN_146, |
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216 EGPIOIRQ_PIN_147, |
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217 EGPIOIRQ_PIN_148, |
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218 EGPIOIRQ_PIN_149, |
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219 EGPIOIRQ_PIN_150, |
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220 EGPIOIRQ_PIN_151, |
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221 EGPIOIRQ_PIN_152, |
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222 EGPIOIRQ_PIN_153, |
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223 EGPIOIRQ_PIN_154, |
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224 EGPIOIRQ_PIN_155, |
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225 EGPIOIRQ_PIN_156, |
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226 EGPIOIRQ_PIN_157, |
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227 EGPIOIRQ_PIN_158, |
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228 EGPIOIRQ_PIN_159, |
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229 EGPIOIRQ_PIN_160, |
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230 EGPIOIRQ_PIN_161, |
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231 EGPIOIRQ_PIN_162, |
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232 EGPIOIRQ_PIN_163, |
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233 EGPIOIRQ_PIN_164, |
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234 EGPIOIRQ_PIN_165, |
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235 EGPIOIRQ_PIN_166, |
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236 EGPIOIRQ_PIN_167, |
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237 EGPIOIRQ_PIN_168, |
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238 EGPIOIRQ_PIN_169, |
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239 EGPIOIRQ_PIN_170, |
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240 EGPIOIRQ_PIN_171, |
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241 EGPIOIRQ_PIN_172, |
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242 EGPIOIRQ_PIN_173, |
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243 EGPIOIRQ_PIN_174, |
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244 EGPIOIRQ_PIN_175, |
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245 EGPIOIRQ_PIN_176, |
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246 EGPIOIRQ_PIN_177, |
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247 EGPIOIRQ_PIN_178, |
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248 EGPIOIRQ_PIN_179, |
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249 EGPIOIRQ_PIN_180, |
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250 EGPIOIRQ_PIN_181, |
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251 EGPIOIRQ_PIN_182, |
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252 EGPIOIRQ_PIN_183, |
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253 EGPIOIRQ_PIN_184, |
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254 EGPIOIRQ_PIN_185, |
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255 EGPIOIRQ_PIN_186, |
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256 EGPIOIRQ_PIN_187, |
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257 EGPIOIRQ_PIN_188, |
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258 EGPIOIRQ_PIN_189, |
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259 EGPIOIRQ_PIN_190, |
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260 EGPIOIRQ_PIN_191, |
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261 |
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262 EGPIOIRQ_END |
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263 }; |
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264 |
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265 |
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266 |
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267 const TInt32 KHwGpioPinMax = 192; // 32*6 pins |
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268 const TInt32 KHwGpioPinsPerBank = 32; |
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269 const TInt32 KHwGpioBanks = KHwGpioPinMax / KHwGpioPinsPerBank ; |
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270 |
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271 // Utility code to convert a pin number to a GPIO bank |
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272 const TUint KGPIO_BASE_ADDRESSES[] = { KGPIO1, KGPIO2, KGPIO3, KGPIO4, KGPIO5, KGPIO6 }; |
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273 |
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274 |
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275 |
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276 |
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277 |
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278 inline TUint GPIO_BASE_ADDRESS(TInt aPin) {return KGPIO_BASE_ADDRESSES[(TInt)(aPin/KHwGpioPinsPerBank)];}; |
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279 #define GPIO_PIN_BANK(aId) ((aId)/KHwGpioPinsPerBank) |
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280 #define GPIO_PIN_OFFSET(aId) (1 << (aId%KHwGpioPinsPerBank)) |
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281 #define GPIO_PIN_BOUNDS(aId)((aId > 0) && (aId <KHwGpioPinMax)) |
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282 |
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283 class GpioPin |
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284 { |
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285 public: |
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286 GPIO::TGpioMode iMode; |
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287 TUint iBankAddr; |
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288 TUint iBank; |
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289 SInterruptHandler irq; |
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290 TUint iIrqVector; |
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291 }; |
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292 |
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293 #endif // __OMAP3530_GPIO_H__ |
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294 |
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295 |