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1 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // \omap3530\omap3530_assp\prcm.h |
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15 // Access to PRCM. |
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16 // This file is part of the Beagle Base port |
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17 // |
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18 |
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19 #ifndef PRCM_H__ |
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20 #define PRCM_H__ |
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21 |
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22 #include <e32cmn.h> |
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23 #include <assp/omap3530_assp/omap3530_irqmap.h> |
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24 |
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25 namespace Prcm |
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26 { |
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27 enum TPanic |
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28 { |
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29 ESetPllConfigBadPll, ///< bad PLL ID in SetPllConfiguration() |
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30 EGetPllConfigBadPll, ///< bad PLL ID in PllConfiguration() |
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31 ESetPllConfigBadFreqRange, ///< bad PLL frequency range in SetPllConfiguration() |
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32 ESetPllConfigBadRamp, ///< bad PLL ramp setting in SetPllConfiguration() |
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33 ESetPllConfigBadDrift, ///< bad PLL drift setting in SetPllConfiguration() |
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34 ESetPllConfigBadDivider, ///< bad divider setting in SetPllConfiguration() |
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35 ESetPllConfigBadMultiplier, ///< bad divider setting in SetPllConfiguration() |
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36 ESetPllLpBadPll, ///< bad PLL ID in SetPllLp() |
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37 EGetPllLpBadPll, ///< bad PLL ID in PllLp() |
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38 ESetPllLpBadMode, ///< bad PLL LP mode in SetPllLp() |
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39 ESetDividerBadClock, ///< bad clock ID in SetDivider() |
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40 EGetDividerBadClock, ///< bad clock ID in Divider() |
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41 ESetStateBadClock, ///< bad clock ID in SetClockState() |
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42 ESetWakeupBadClock, ///< bad clock ID in SetWakeupMode() |
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43 ESetPllModeBadClock, |
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44 ESetPllModeBadMode, |
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45 EGetStateBadClock, ///< bad clock ID in ClockState() |
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46 EGetWakeupBadClock, ///< bad clock ID in WakeupMode() |
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47 ESetGptClockBadGpt, ///< bad GPT ID in SetGptClockSource() |
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48 EGetWakeupGroupBadClock, |
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49 EGetWakeupGroupBadGroup, |
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50 EAddWakeupGroupBadClock, |
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51 EAddWakeupGroupBadGroup, |
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52 ERemoveWakeupGroupBadClock, |
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53 ERemoveWakeupGroupBadGroup, |
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54 EAddDomainBadClock, ///< bad clock in call to AddToWakeupDomain() |
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55 ERemoveDomainBadClock, ///< bad clock in call to RemoveFromWakeupDomain() |
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56 ECheckDomainBadClock, ///< bad clock in call to IsInWakeupDomain() |
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57 EAddDomainBadDomain, ///< bad domain in call to AddToWakeupDomain() |
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58 ERemoveDomainBadDomain, ///< bad domain in call to RemoveFromWakeupDomain() |
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59 ECheckDomainBadDomain, ///< bad domain in call to IsInWakeupDomain() |
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60 ESetDividerUnsupportedClock, ///< attempt to set divider on clock that does not have divider |
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61 ESetDividerBadDivider, ///< bad divider value in SetDivider() |
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62 EGetNameBadClock, ///< bad clock ID in PrmName() |
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63 EClockFrequencyBadClock, ///< bad clock ID in ClockFrequency() |
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64 ESetClockMuxBadClock, ///< bad clock ID in SetClockMux() |
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65 ESetClockMuxBadSource, ///< bad source clock ID in SetClockMux() |
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66 EGetClockMuxBadClock, ///< bad clock ID in ClockMux() |
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67 ESetDomainModeBadDomain, ///< bad domain in SetPowerDomainMode() |
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68 ESetDomainModeBadMode, ///< bad mode in SetPowerDomainMode() |
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69 EGetDomainModeBadDomain, ///< bad domain in PowerDomainMode() |
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70 ESetDomainModeUnsupportedMode, ///< mode requested in SetPowerDomainMode() not supported by that domain |
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71 EPllIsLockedBadPll, ///< bad PLL ID in PllIsLocked() |
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72 EWaitForPllLockBadPll, ///< bad PLL ID in WaitForPllLocked() |
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73 ESetPllBypassDividerBadPll, ///< bad PLL ID in SetPllBypassDivider() |
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74 EPllBypassDividerBadPll, ///< bad PLL ID in PllBypassDivider() |
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75 ESetPllBypassDividerBadDivider, ///< bad dividier value in SetPllBypassDivider() |
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76 EPllInternalFrequencyOutOfRange ///< PLL internal frequency out of range in AutoSetPllFrequencyRange() |
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77 }; |
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78 |
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79 enum TClock |
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80 { |
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81 EClkMpu, ///< DPLL1 |
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82 EClkIva2Pll, ///< DPLL2 |
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83 EClkCore, ///< DPLL3 |
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84 EClkPeriph, ///< DPLL4 |
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85 EClkPeriph2, ///< DPLL5 |
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86 |
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87 EClkPrcmInterface, |
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88 |
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89 EClkEmu, ///< Emulation clock |
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90 EClkNeon, |
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91 |
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92 EClkL3Domain, |
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93 EClkL4Domain, |
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94 |
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95 EClkMpuPll_Bypass, ///< DPLL1 bypass frequency |
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96 EClkIva2Pll_Bypass, ///< DPLL2 bypass frequency |
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97 EClkRM_F, ///< Reset manager functional clock |
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98 EClk96M, ///< 96MHz clock |
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99 EClk120M, ///< 120MHz clock |
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100 EClkSysOut, |
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101 |
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102 // Functional clocks |
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103 EClkTv_F, ///< TV functional clock, same as 54MHz FCLK |
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104 EClkDss1_F, |
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105 EClkDss2_F, |
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106 EClkCsi2_F, |
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107 EClkCam_F, |
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108 EClkIva2_F, |
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109 EClkMmc1_F, |
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110 EClkMmc2_F, |
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111 EClkMmc3_F, |
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112 EClkMsPro_F, |
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113 EClkHdq_F, |
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114 EClkMcBsp1_F, |
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115 EClkMcBsp2_F, |
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116 EClkMcBsp3_F, |
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117 EClkMcBsp4_F, |
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118 EClkMcBsp5_F, |
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119 EClkMcSpi1_F, |
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120 EClkMcSpi2_F, |
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121 EClkMcSpi3_F, |
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122 EClkMcSpi4_F, |
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123 EClkI2c1_F, |
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124 EClkI2c2_F, |
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125 EClkI2c3_F, |
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126 EClkUart1_F, |
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127 EClkUart2_F, |
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128 EClkUart3_F, |
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129 EClkGpt1_F, |
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130 EClkGpt2_F, |
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131 EClkGpt3_F, |
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132 EClkGpt4_F, |
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133 EClkGpt5_F, |
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134 EClkGpt6_F, |
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135 EClkGpt7_F, |
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136 EClkGpt8_F, |
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137 EClkGpt9_F, |
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138 EClkGpt10_F, |
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139 EClkGpt11_F, |
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140 EClkUsbTll_F, |
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141 EClkTs_F, |
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142 EClkCpeFuse_F, |
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143 |
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144 EClkSgx_F, |
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145 |
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146 EClkUsim_F, |
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147 EClkSmartReflex2_F, |
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148 EClkSmartReflex1_F, |
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149 EClkWdt2_F, |
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150 EClkWdt3_F, |
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151 EClkGpio1_F, |
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152 EClkGpio2_F, |
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153 EClkGpio3_F, |
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154 EClkGpio4_F, |
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155 EClkGpio5_F, |
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156 EClkGpio6_F, |
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157 |
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158 EClkUsb120_F, ///< USB host 120MHz functional clock |
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159 EClkUsb48_F, ///< USB host 48MHz functional clock |
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160 |
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161 |
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162 // Interface clocks |
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163 EClkDss_I, |
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164 EClkCam_I, |
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165 EClkIcr_I, |
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166 EClkMmc1_I, |
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167 EClkMmc2_I, |
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168 EClkMmc3_I, |
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169 EClkMsPro_I, |
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170 EClkHdq_I, |
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171 EClkAes1_I, |
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172 EClkAes2_I, |
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173 EClkSha11_I, |
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174 EClkSha12_I, |
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175 EClkDes1_I, |
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176 EClkDes2_I, |
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177 EClkMcBsp1_I, |
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178 EClkMcBsp2_I, |
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179 EClkMcBsp3_I, |
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180 EClkMcBsp4_I, |
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181 EClkMcBsp5_I, |
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182 EClkI2c1_I, |
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183 EClkI2c2_I, |
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184 EClkI2c3_I, |
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185 EClkUart1_I, |
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186 EClkUart2_I, |
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187 EClkUart3_I, |
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188 EClkMcSpi1_I, |
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189 EClkMcSpi2_I, |
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190 EClkMcSpi3_I, |
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191 EClkMcSpi4_I, |
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192 EClkGpt1_I, |
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193 EClkGpt2_I, |
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194 EClkGpt3_I, |
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195 EClkGpt4_I, |
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196 EClkGpt5_I, |
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197 EClkGpt6_I, |
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198 EClkGpt7_I, |
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199 EClkGpt8_I, |
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200 EClkGpt9_I, |
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201 EClkGpt10_I, |
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202 EClkGpt11_I, |
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203 EClkGpt12_I, |
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204 EClkMailboxes_I, |
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205 EClkOmapSCM_I, |
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206 EClkHsUsbOtg_I, |
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207 EClkSdrc_I, |
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208 EClkPka_I, |
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209 EClkRng_I, |
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210 EClkUsbTll_I, |
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211 |
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212 EClkSgx_I, |
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213 |
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214 EClkUsim_I, |
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215 EClkWdt1_I, |
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216 EClkWdt2_I, |
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217 EClkWdt3_I, |
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218 EClkGpio1_I, |
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219 EClkGpio2_I, |
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220 EClkGpio3_I, |
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221 EClkGpio4_I, |
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222 EClkGpio5_I, |
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223 EClkGpio6_I, |
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224 EClk32Sync_I, |
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225 |
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226 EClkUsb_I, ///< USB host interface clock |
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227 |
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228 EClk48M, ///< 48MHz clock |
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229 EClk12M, ///< 12MHz clock |
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230 |
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231 // These cannot be modified, they just represent the input clocks |
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232 // They must remain last in the table |
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233 EClkSysClk, ///< SYSCLK input clock |
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234 EClkAltClk, ///< SYSCLK32k input clock |
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235 EClkSysClk32k, ///< ALTCLK input clock |
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236 |
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237 KSupportedClockCount |
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238 }; |
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239 |
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240 enum TInterruptIds |
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241 { |
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242 EIntWkUp = (EIrqRangeBasePrcm << KIrqRangeIndexShift), |
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243 EIntUnused1, |
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244 EIntEvGenOn, |
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245 EIntEvGenOff, |
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246 EIntTransition, |
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247 EIntCoreDpll, |
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248 EIntPeriphDpll, |
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249 EIntMpuDpll, |
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250 EIntIvaDpll, |
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251 EIntIo, |
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252 EIntVp1OpChangeDone, |
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253 EIntVp1MinVdd, |
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254 EIntVp1MaxVdd, |
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255 EIntVp1NoSmpsAck, |
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256 EIntVp1EqValue, |
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257 EIntVp1TranDone, |
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258 EIntVp2OpChangeDone, |
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259 EIntVp2MinVdd, |
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260 EIntVp2MaxVdd, |
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261 EIntVp2NoSmpsAck, |
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262 EIntVp2EqValue, |
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263 EIntVp2TranDone, |
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264 EIntVcSaErr, |
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265 EIntVcRaErr, |
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266 EIntVcTimeoutErr, |
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267 EIntSndPeriphDpll, |
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268 |
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269 KPrcmLastInterruptPlusOne |
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270 }; |
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271 const TInt KInterruptCount = KPrcmLastInterruptPlusOne - EIrqRangeBasePrcm; |
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272 |
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273 |
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274 /** GPT reference enumeration */ |
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275 enum TGpt |
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276 { |
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277 EGpt1, |
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278 EGpt2, |
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279 EGpt3, |
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280 EGpt4, |
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281 EGpt5, |
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282 EGpt6, |
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283 EGpt7, |
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284 EGpt8, |
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285 EGpt9, |
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286 EGpt10, |
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287 EGpt11, |
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288 EGpt12, |
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289 |
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290 KSupportedGptCount |
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291 }; |
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292 |
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293 /** Enumeration of supported PLLs */ |
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294 enum TPll |
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295 { |
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296 EDpll1, |
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297 EDpll2, |
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298 EDpll3, |
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299 EDpll4, |
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300 EDpll5, |
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301 |
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302 KSupportedPllCount |
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303 }; |
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304 |
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305 enum TGptClockSource |
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306 { |
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307 EGptClockSysClk, |
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308 EGptClock32k |
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309 }; |
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310 |
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311 enum TClockState |
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312 { |
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313 EClkOff, ///< clock is disabled |
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314 EClkOn, ///< clock is enabled |
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315 EClkAuto ///< clock is in auto mode (enabled when required) |
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316 }; |
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317 |
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318 enum TWakeupMode |
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319 { |
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320 EWakeupDisabled, |
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321 EWakeupEnabled, |
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322 }; |
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323 |
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324 enum TLpMode |
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325 { |
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326 ENormalMode, |
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327 ELpMode |
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328 }; |
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329 |
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330 enum TPowerSaveMode |
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331 { |
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332 EPowerSaveOff, |
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333 EPowerSaveIdle, |
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334 EPowerSaveStandby |
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335 }; |
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336 |
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337 enum TPllMode |
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338 { |
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339 EPllStop, |
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340 EPllBypass, |
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341 EPllRun, |
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342 EPllFastRelock, |
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343 EPllAuto |
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344 }; |
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345 |
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346 enum TBypassDivider |
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347 { |
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348 EBypassDiv1, |
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349 EBypassDiv2, |
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350 EBypassDiv4 |
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351 }; |
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352 |
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353 enum TPowerDomainMode |
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354 { |
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355 EPowerOff, |
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356 EPowerRetention, |
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357 EPowerReserved, |
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358 EPowerOn, |
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359 }; |
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360 |
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361 enum TPowerDomain |
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362 { |
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363 EPowerDomainMpu, |
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364 EPowerDomainIva2, |
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365 EPowerDomainNeon, |
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366 EPowerDomainCore, |
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367 EPowerDomainSgx, |
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368 EPowerDomainDss, |
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369 EPowerDomainCamera, |
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370 EPowerDomainUsb, |
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371 EPowerDomainPer, |
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372 |
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373 KSupportedPowerDomainCount |
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374 }; |
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375 |
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376 enum TWakeupDomain |
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377 { |
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378 EWakeDomainMpu, |
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379 EWakeDomainCore, |
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380 EWakeDomainIva2, |
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381 EWakeDomainPeripheral, |
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382 EWakeDomainDss, |
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383 EWakeDomainWakeup, |
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384 |
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385 KSupportedWakeupDomainCount |
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386 }; |
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387 |
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388 enum TWakeupGroup |
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389 { |
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390 EWakeGroupMpu, |
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391 EWakeGroupIva2, |
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392 |
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393 KSupportedWakeupGroupCount |
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394 }; |
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395 |
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396 /** Indicates how to handle a request to set a clock frequency */ |
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397 enum TClockRoundMode |
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398 { |
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399 EExactOnly, ///< only set clock if requested frequency can be set exactly |
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400 ENearest, ///< always set clock to nearest possible frequency higher or lower than requested |
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401 ENearestLower, ///< set to nearest frequency <=requested, fail if no frequency <= requested is possible |
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402 ENearestHigher, ///< set to nearest frequency >=requested, fail if no frequency >= requested is possible |
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403 }; |
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404 |
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405 /** Enumeration of valid Pll frequency ranges */ |
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406 enum TPllFrequencyRange |
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407 { |
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408 EPllRange_075_100 = 0x3, ///< 0.75 - 1.0 MHz |
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409 EPllRange_100_125 = 0x4, ///< <1.0 MHz - 1.25 MHz |
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410 EPllRange_125_150 = 0x5, ///< <1.25 MHz - 1.5 MHz |
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411 EPllRange_150_175 = 0x6, ///< <1.5 MHz - 1.75 MHz |
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412 EPllRange_175_210 = 0x7, ///< <1.75 MHz - 2.1 MHz |
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413 EPllRange_750_1000 = 0xB, ///< <7.5 MHz - 10 MHz |
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414 EPllRange_1000_1250 = 0xC, ///< <10 MHz - 12.5 MHz |
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415 EPllRange_1250_1500 = 0xD, ///< <12.5 MHz - 15 MHz |
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416 EPllRange_1500_1750 = 0xE, ///< <15 MHz - 17.5 MHz |
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417 EPllRange_1750_2100 = 0xF ///< <17.5 MHz - 21 MHz |
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418 }; |
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419 |
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420 /** Enumeration of valid PLL ramp settings */ |
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421 enum TPllRamp |
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422 { |
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423 EPllRampDisabled = 0x0, |
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424 EPllRamp4us = 0x1, |
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425 EPllRam20us = 0x2, |
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426 EPllRamp40us = 0x3 |
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427 }; |
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428 |
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429 /** Enumeration of vali PLL driftguard settings */ |
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430 enum TPllDrift |
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431 { |
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432 EPllDriftGuardDisabled, |
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433 EPllDriftGuardEnabled |
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434 }; |
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435 |
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436 /** Structure containing configuration for a PLL */ |
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437 struct TPllConfiguration |
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438 { |
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439 TUint iMultiplier; ///< Multiple value |
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440 TUint iDivider; ///< Divider value (this is actual divider, hardware is programmed with iDivider-1) |
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441 TPllFrequencyRange iFreqRange : 8; |
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442 TPllRamp iRamp : 8; |
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443 TPllDrift iDrift : 8; |
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444 TUint8 __spare; |
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445 }; |
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446 |
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447 /** Enumeration of supported SysClk frequency configurations */ |
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448 enum TSysClkFrequency |
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449 { |
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450 ESysClk12MHz, |
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451 ESysClk13MHz, |
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452 ESysClk16_8MHz, |
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453 ESysClk19_2MHz, |
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454 ESysClk26MHz, |
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455 ESysClk38_4MHz |
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456 }; |
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457 |
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458 // called during start-up |
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459 IMPORT_C void Init3(); // PRCM (disable every peripheral leaving DSS (and UART3 in debug) running) |
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460 |
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461 IMPORT_C void SetPllConfig( TPll aPll, const TPllConfiguration& aConfig ); |
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462 IMPORT_C void PllConfig( TPll aPll, TPllConfiguration& aConfigResult ); |
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463 |
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464 |
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465 /** Configure PLL frequency */ |
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466 IMPORT_C void SetPllMode( TPll aPll, TPllMode aPllMode ); |
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467 |
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468 /** Return PLL frequency configuration */ |
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469 IMPORT_C TPllMode PllMode( TPll aPll ); |
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470 |
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471 /** Test whether a PLL is locked */ |
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472 IMPORT_C TBool PllIsLocked( TPll aPll ); |
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473 |
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474 /** Wait for a PLL to lock */ |
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475 IMPORT_C void WaitForPllLock( TPll aPll ); |
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476 |
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477 /** Calculate the correct FreqRange setting for the given pll |
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478 * Updates the iFreqRange parameter of the given TPllConfiguration |
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479 */ |
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480 IMPORT_C void CalcPllFrequencyRange( TPll aPll, TPllConfiguration& aConfig ); |
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481 |
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482 /** Enable LP mode on a DLL if it is within LP frequency range */ |
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483 IMPORT_C void AutoSetPllLpMode( TPll aPll ); |
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484 |
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485 /** Enable or disable PLL LP mode */ |
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486 IMPORT_C void SetPllLp( TPll aPll, TLpMode aLpMode ); |
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487 |
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488 /** Get LP mode setting for a PLL */ |
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489 IMPORT_C TLpMode PllLp( TPll aPll ); |
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490 |
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491 /** Set the bypass divider for a PLL */ |
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492 IMPORT_C void SetPllBypassDivider( TPll aPll, TBypassDivider aDivider ); |
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493 |
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494 /** Get the current bypass divider for a PLL */ |
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495 IMPORT_C TBypassDivider PllBypassDivider( TPll aPll ); |
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496 |
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497 /** Set the divider value for the given clock |
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498 * aDivider is the required divide value - e.g. to divide by 4 |
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499 * aDivider=4. |
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500 * |
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501 * Note that not all clocks support division by any number, and |
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502 * only some clocks have a divider. Attempting to set a divider |
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503 * on a clock without a divider will have no effect in UREL and |
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504 * will panic in UDEB with ESetDividerUnsupportedClock. |
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505 * Attempting to set a divider value not supported by the clock |
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506 * will have no effect in UREL and will panic in UDEB with |
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507 * ESetDividerBadDivider. |
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508 * |
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509 * Note 1: for EClkSgx_F the value valued of aDivide are 0, 3, 4, 6. |
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510 * 0 sets the clock to be the 96MHz clock |
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511 * 3, 4, 6 set it to be CORE_CLK divided by 3, 4, or 6 |
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512 * |
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513 * Note 2: you cannot use this function to set EClkUsim_F, use |
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514 * SetUsimClockDivider(). |
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515 */ |
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516 IMPORT_C void SetDivider( TClock aClock, TUint aDivide ); |
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517 |
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518 /** Get the current divider value of the given clock */ |
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519 IMPORT_C TUint Divider( TClock aClock ); |
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520 |
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521 //IMPORT_C void SetUsimClockDivider( TUint TUsimDivideMode aMode ); |
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522 //IMPORT_C TUsimDivideMode UsimClockDivider(); |
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523 |
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524 /** Controls power to a power domain */ |
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525 IMPORT_C void SetPowerDomainMode( TPowerDomain aDomain, TPowerDomainMode aMode ); |
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526 |
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527 /** Gets the current mode of a power domain power control */ |
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528 IMPORT_C TPowerDomainMode PowerDomainMode( TPowerDomain aDomain ); |
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529 |
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530 //IMPORT_C void SetPowerSaveMode( TClock aClock, TPowerSaveMode aMode ); |
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531 //IMPORT_C TPowerSaveMode PowerSaveMode( TClock aClock ); |
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532 |
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533 //IMPORT_C TBool DomainClockActive( TClock aClock ); |
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534 |
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535 // Set clock enable/disable |
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536 /** Set the clock state of a given clock */ |
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537 IMPORT_C void SetClockState( TClock aClock, TClockState aState ); |
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538 |
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539 /** Get the configured clock state of a given clock */ |
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540 IMPORT_C TClockState ClockState( TClock aClock ); |
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541 |
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542 // Configure wakeup mode for clocks |
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543 /** Configure wakeup mode for a clock |
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544 * Note - for peripheral blocks with an interface and functional clock, it is |
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545 * the interface clock which is configured for wakeup. Attempting to configure |
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546 * wakeup on the functional clock has no effect |
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547 */ |
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548 IMPORT_C void SetWakeupMode( TClock aClock, TWakeupMode aMode ); |
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549 |
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550 /** Get configured wakeup mode for a clock */ |
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551 IMPORT_C TWakeupMode WakeupMode( TClock aClock ); |
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552 |
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553 /** Add a peripheral interface clock to the specified wakeup group */ |
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554 IMPORT_C void AddToWakeupGroup( TClock aClock, TWakeupGroup aGroup ); |
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555 |
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556 /** Remove a peripheral interface clock from the specified wakeup group */ |
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557 IMPORT_C void RemoveFromWakeupGroup( TClock aClock, TWakeupGroup aGroup ); |
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558 |
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559 /** Test whether a peripheral interface clock is in the specified wakeup group */ |
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560 IMPORT_C TBool IsInWakeupGroup( TClock aClock, TWakeupGroup aGroup ); |
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561 |
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562 /** Add a clock to the given wakeup domain */ |
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563 IMPORT_C void AddToWakeupDomain( TClock aClock, TWakeupDomain aDomain ); |
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564 |
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565 /** Remove a clock from the given wakeup domain */ |
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566 IMPORT_C void RemoveFromWakeupDomain( TClock aClock, TWakeupDomain aDomain ); |
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567 |
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568 /** Test whether a clock is in the specified wakeup domain */ |
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569 IMPORT_C TBool IsInWakeupDomain( TClock aClock, TWakeupDomain aDomain ); |
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570 |
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571 |
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572 // Functions for configuring clock sources |
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573 |
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574 /** Set the clock source for a GPT timer */ |
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575 IMPORT_C void SetGptClockSource( TGpt aGpt, TGptClockSource aSource ); |
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576 |
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577 /** Get the current clock source of a GPT */ |
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578 IMPORT_C TGptClockSource GptClockSource( TGpt aGpt ); |
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579 |
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580 /** Get the USIM divider factor */ |
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581 IMPORT_C TUint UsimDivider(); |
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582 |
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583 /** Get the USIM source clock */ |
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584 IMPORT_C TClock UsimClockSource(); |
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585 |
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586 /** Sets the current input clock into the clock mux for the specified clock |
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587 * aClock must refer to a clock that has a mux for selecting input clock |
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588 * and aSource must be a possible input clock for aClock |
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589 */ |
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590 IMPORT_C void SetClockMux( TClock aClock, TClock aSource ); |
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591 |
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592 |
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593 /** Gets the current input clock into the clock mux for the specified clock |
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594 * aClock must refer to a clock that has a mux for selecting input clock |
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595 */ |
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596 IMPORT_C TClock ClockMux( TClock aClock ); |
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597 |
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598 /** Get the currently configured frequency of the specified clock |
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599 * Note that this is regardless of whether the clock is currently running. |
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600 * That is, if a clock is configured to run at 8MHz, then this function |
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601 * will return 8000000 whether the clock is currently enabled or disabled. |
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602 * |
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603 * @param aClock clock required |
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604 * @return Frequency in Hz |
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605 */ |
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606 IMPORT_C TUint ClockFrequency( TClock aClock ); |
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607 |
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608 /** Set the correct SysClock frequency */ |
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609 IMPORT_C void SetSysClkFrequency( TSysClkFrequency aFrequency ); |
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610 |
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611 /** Get the currently configured SysClk frequency */ |
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612 IMPORT_C TSysClkFrequency SysClkFrequency(); |
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613 |
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614 /** Function to get the name to be passed to the Power Resource Manager |
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615 * to refer to the given clock source |
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616 */ |
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617 IMPORT_C const TDesC& PrmName( TClock aClock ); |
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618 |
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619 } |
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620 |
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621 #endif // !defined PRCM_H__ |