/*

 * Texas Instruments OMAP processors.

 *

 * Copyright (C) 2006-2008 Andrzej Zaborowski  <balrog@zabor.org>

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License as

 * published by the Free Software Foundation; either version 2 or

 * (at your option) version 3 of the License.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,

 * MA 02111-1307 USA

 */

#ifndef hw_omap_h

# define hw_omap_h		"omap.h"

# define OMAP_EMIFS_BASE	0x00000000

# define OMAP2_Q0_BASE		0x00000000

# define OMAP_CS0_BASE		0x00000000

# define OMAP_CS1_BASE		0x04000000

# define OMAP_CS2_BASE		0x08000000

# define OMAP_CS3_BASE		0x0c000000

# define OMAP_EMIFF_BASE	0x10000000

# define OMAP_IMIF_BASE		0x20000000

# define OMAP_LOCALBUS_BASE	0x30000000

# define OMAP2_Q1_BASE		0x40000000

# define OMAP2_L4_BASE		0x48000000

# define OMAP2_SRAM_BASE	0x40200000

# define OMAP2_L3_BASE		0x68000000

# define OMAP2_Q2_BASE		0x80000000

# define OMAP2_Q3_BASE		0xc0000000

# define OMAP_MPUI_BASE		0xe1000000

# define OMAP730_SRAM_SIZE	0x00032000

# define OMAP15XX_SRAM_SIZE	0x00030000

# define OMAP16XX_SRAM_SIZE	0x00004000

# define OMAP1611_SRAM_SIZE	0x0003e800

# define OMAP242X_SRAM_SIZE	0x000a0000

# define OMAP243X_SRAM_SIZE	0x00010000

# define OMAP_CS0_SIZE		0x04000000

# define OMAP_CS1_SIZE		0x04000000

# define OMAP_CS2_SIZE		0x04000000

# define OMAP_CS3_SIZE		0x04000000

/* omap_clk.c */

struct omap_mpu_state_s;

typedef struct clk *omap_clk;

omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name);

void omap_clk_init(struct omap_mpu_state_s *mpu);

void omap_clk_adduser(struct clk *clk, qemu_irq user);

void omap_clk_get(omap_clk clk);

void omap_clk_put(omap_clk clk);

void omap_clk_onoff(omap_clk clk, int on);

void omap_clk_canidle(omap_clk clk, int can);

void omap_clk_setrate(omap_clk clk, int divide, int multiply);

int64_t omap_clk_getrate(omap_clk clk);

void omap_clk_reparent(omap_clk clk, omap_clk parent);

/* omap[123].c */

struct omap_l4_s;

struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num);

struct omap_target_agent_s;

struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs);

target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,

                int iotype);

# define l4_register_io_memory	cpu_register_io_memory

struct omap_intr_handler_s;

struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,

                unsigned long size, unsigned char nbanks, qemu_irq **pins,

                qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk);

struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,

                int size, int nbanks, qemu_irq **pins,

                qemu_irq parent_irq, qemu_irq parent_fiq,

                omap_clk fclk, omap_clk iclk);

void omap_inth_reset(struct omap_intr_handler_s *s);

struct omap_prcm_s;

struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,

                qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,

                struct omap_mpu_state_s *mpu);

struct omap_sysctl_s;

struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,

                omap_clk iclk, struct omap_mpu_state_s *mpu);

struct omap_sdrc_s;

struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base);

struct omap_gpmc_s;

struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq);

void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,

                void (*base_upd)(void *opaque, target_phys_addr_t new),

                void (*unmap)(void *opaque), void *opaque);

/*

 * Common IRQ numbers for level 1 interrupt handler

 * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.

 */

# define OMAP_INT_CAMERA		1

# define OMAP_INT_FIQ			3

# define OMAP_INT_RTDX			6

# define OMAP_INT_DSP_MMU_ABORT		7

# define OMAP_INT_HOST			8

# define OMAP_INT_ABORT			9

# define OMAP_INT_BRIDGE_PRIV		13

# define OMAP_INT_GPIO_BANK1		14

# define OMAP_INT_UART3			15

# define OMAP_INT_TIMER3		16

# define OMAP_INT_DMA_CH0_6		19

# define OMAP_INT_DMA_CH1_7		20

# define OMAP_INT_DMA_CH2_8		21

# define OMAP_INT_DMA_CH3		22

# define OMAP_INT_DMA_CH4		23

# define OMAP_INT_DMA_CH5		24

# define OMAP_INT_DMA_LCD		25

# define OMAP_INT_TIMER1		26

# define OMAP_INT_WD_TIMER		27

# define OMAP_INT_BRIDGE_PUB		28

# define OMAP_INT_TIMER2		30

# define OMAP_INT_LCD_CTRL		31

/*

 * Common OMAP-15xx IRQ numbers for level 1 interrupt handler

 */

# define OMAP_INT_15XX_IH2_IRQ		0

# define OMAP_INT_15XX_LB_MMU		17

# define OMAP_INT_15XX_LOCAL_BUS	29

/*

 * OMAP-1510 specific IRQ numbers for level 1 interrupt handler

 */

# define OMAP_INT_1510_SPI_TX		4

# define OMAP_INT_1510_SPI_RX		5

# define OMAP_INT_1510_DSP_MAILBOX1	10

# define OMAP_INT_1510_DSP_MAILBOX2	11

/*

 * OMAP-310 specific IRQ numbers for level 1 interrupt handler

 */

# define OMAP_INT_310_McBSP2_TX		4

# define OMAP_INT_310_McBSP2_RX		5

# define OMAP_INT_310_HSB_MAILBOX1	12

# define OMAP_INT_310_HSAB_MMU		18

/*

 * OMAP-1610 specific IRQ numbers for level 1 interrupt handler

 */

# define OMAP_INT_1610_IH2_IRQ		0

# define OMAP_INT_1610_IH2_FIQ		2

# define OMAP_INT_1610_McBSP2_TX	4

# define OMAP_INT_1610_McBSP2_RX	5

# define OMAP_INT_1610_DSP_MAILBOX1	10

# define OMAP_INT_1610_DSP_MAILBOX2	11

# define OMAP_INT_1610_LCD_LINE		12

# define OMAP_INT_1610_GPTIMER1		17

# define OMAP_INT_1610_GPTIMER2		18

# define OMAP_INT_1610_SSR_FIFO_0	29

/*

 * OMAP-730 specific IRQ numbers for level 1 interrupt handler

 */

# define OMAP_INT_730_IH2_FIQ		0

# define OMAP_INT_730_IH2_IRQ		1

# define OMAP_INT_730_USB_NON_ISO	2

# define OMAP_INT_730_USB_ISO		3

# define OMAP_INT_730_ICR		4

# define OMAP_INT_730_EAC		5

# define OMAP_INT_730_GPIO_BANK1	6

# define OMAP_INT_730_GPIO_BANK2	7

# define OMAP_INT_730_GPIO_BANK3	8

# define OMAP_INT_730_McBSP2TX		10

# define OMAP_INT_730_McBSP2RX		11

# define OMAP_INT_730_McBSP2RX_OVF	12

# define OMAP_INT_730_LCD_LINE		14

# define OMAP_INT_730_GSM_PROTECT	15

# define OMAP_INT_730_TIMER3		16

# define OMAP_INT_730_GPIO_BANK5	17

# define OMAP_INT_730_GPIO_BANK6	18

# define OMAP_INT_730_SPGIO_WR		29

/*

 * Common IRQ numbers for level 2 interrupt handler

 */

# define OMAP_INT_KEYBOARD		1

# define OMAP_INT_uWireTX		2

# define OMAP_INT_uWireRX		3

# define OMAP_INT_I2C			4

# define OMAP_INT_MPUIO			5

# define OMAP_INT_USB_HHC_1		6

# define OMAP_INT_McBSP3TX		10

# define OMAP_INT_McBSP3RX		11

# define OMAP_INT_McBSP1TX		12

# define OMAP_INT_McBSP1RX		13

# define OMAP_INT_UART1			14

# define OMAP_INT_UART2			15

# define OMAP_INT_USB_W2FC		20

# define OMAP_INT_1WIRE			21

# define OMAP_INT_OS_TIMER		22

# define OMAP_INT_OQN			23

# define OMAP_INT_GAUGE_32K		24

# define OMAP_INT_RTC_TIMER		25

# define OMAP_INT_RTC_ALARM		26

# define OMAP_INT_DSP_MMU		28

/*

 * OMAP-1510 specific IRQ numbers for level 2 interrupt handler

 */

# define OMAP_INT_1510_BT_MCSI1TX	16

# define OMAP_INT_1510_BT_MCSI1RX	17

# define OMAP_INT_1510_SoSSI_MATCH	19

# define OMAP_INT_1510_MEM_STICK	27

# define OMAP_INT_1510_COM_SPI_RO	31

/*

 * OMAP-310 specific IRQ numbers for level 2 interrupt handler

 */

# define OMAP_INT_310_FAC		0

# define OMAP_INT_310_USB_HHC_2		7

# define OMAP_INT_310_MCSI1_FE		16

# define OMAP_INT_310_MCSI2_FE		17

# define OMAP_INT_310_USB_W2FC_ISO	29

# define OMAP_INT_310_USB_W2FC_NON_ISO	30

# define OMAP_INT_310_McBSP2RX_OF	31

/*

 * OMAP-1610 specific IRQ numbers for level 2 interrupt handler

 */

# define OMAP_INT_1610_FAC		0

# define OMAP_INT_1610_USB_HHC_2	7

# define OMAP_INT_1610_USB_OTG		8

# define OMAP_INT_1610_SoSSI		9

# define OMAP_INT_1610_BT_MCSI1TX	16

# define OMAP_INT_1610_BT_MCSI1RX	17

# define OMAP_INT_1610_SoSSI_MATCH	19

# define OMAP_INT_1610_MEM_STICK	27

# define OMAP_INT_1610_McBSP2RX_OF	31

# define OMAP_INT_1610_STI		32

# define OMAP_INT_1610_STI_WAKEUP	33

# define OMAP_INT_1610_GPTIMER3		34

# define OMAP_INT_1610_GPTIMER4		35

# define OMAP_INT_1610_GPTIMER5		36

# define OMAP_INT_1610_GPTIMER6		37

# define OMAP_INT_1610_GPTIMER7		38

# define OMAP_INT_1610_GPTIMER8		39

# define OMAP_INT_1610_GPIO_BANK2	40

# define OMAP_INT_1610_GPIO_BANK3	41

# define OMAP_INT_1610_MMC2		42

# define OMAP_INT_1610_CF		43

# define OMAP_INT_1610_WAKE_UP_REQ	46

# define OMAP_INT_1610_GPIO_BANK4	48

# define OMAP_INT_1610_SPI		49

# define OMAP_INT_1610_DMA_CH6		53

# define OMAP_INT_1610_DMA_CH7		54

# define OMAP_INT_1610_DMA_CH8		55

# define OMAP_INT_1610_DMA_CH9		56

# define OMAP_INT_1610_DMA_CH10		57

# define OMAP_INT_1610_DMA_CH11		58

# define OMAP_INT_1610_DMA_CH12		59

# define OMAP_INT_1610_DMA_CH13		60

# define OMAP_INT_1610_DMA_CH14		61

# define OMAP_INT_1610_DMA_CH15		62

# define OMAP_INT_1610_NAND		63

/*

 * OMAP-730 specific IRQ numbers for level 2 interrupt handler

 */

# define OMAP_INT_730_HW_ERRORS		0

# define OMAP_INT_730_NFIQ_PWR_FAIL	1

# define OMAP_INT_730_CFCD		2

# define OMAP_INT_730_CFIREQ		3

# define OMAP_INT_730_I2C		4

# define OMAP_INT_730_PCC		5

# define OMAP_INT_730_MPU_EXT_NIRQ	6

# define OMAP_INT_730_SPI_100K_1	7

# define OMAP_INT_730_SYREN_SPI		8

# define OMAP_INT_730_VLYNQ		9

# define OMAP_INT_730_GPIO_BANK4	10

# define OMAP_INT_730_McBSP1TX		11

# define OMAP_INT_730_McBSP1RX		12

# define OMAP_INT_730_McBSP1RX_OF	13

# define OMAP_INT_730_UART_MODEM_IRDA_2	14

# define OMAP_INT_730_UART_MODEM_1	15

# define OMAP_INT_730_MCSI		16

# define OMAP_INT_730_uWireTX		17

# define OMAP_INT_730_uWireRX		18

# define OMAP_INT_730_SMC_CD		19

# define OMAP_INT_730_SMC_IREQ		20

# define OMAP_INT_730_HDQ_1WIRE		21

# define OMAP_INT_730_TIMER32K		22

# define OMAP_INT_730_MMC_SDIO		23

# define OMAP_INT_730_UPLD		24

# define OMAP_INT_730_USB_HHC_1		27

# define OMAP_INT_730_USB_HHC_2		28

# define OMAP_INT_730_USB_GENI		29

# define OMAP_INT_730_USB_OTG		30

# define OMAP_INT_730_CAMERA_IF		31

# define OMAP_INT_730_RNG		32

# define OMAP_INT_730_DUAL_MODE_TIMER	33

# define OMAP_INT_730_DBB_RF_EN		34

# define OMAP_INT_730_MPUIO_KEYPAD	35

# define OMAP_INT_730_SHA1_MD5		36

# define OMAP_INT_730_SPI_100K_2	37

# define OMAP_INT_730_RNG_IDLE		38

# define OMAP_INT_730_MPUIO		39

# define OMAP_INT_730_LLPC_LCD_CTRL_OFF	40

# define OMAP_INT_730_LLPC_OE_FALLING	41

# define OMAP_INT_730_LLPC_OE_RISING	42

# define OMAP_INT_730_LLPC_VSYNC	43

# define OMAP_INT_730_WAKE_UP_REQ	46

# define OMAP_INT_730_DMA_CH6		53

# define OMAP_INT_730_DMA_CH7		54

# define OMAP_INT_730_DMA_CH8		55

# define OMAP_INT_730_DMA_CH9		56

# define OMAP_INT_730_DMA_CH10		57

# define OMAP_INT_730_DMA_CH11		58

# define OMAP_INT_730_DMA_CH12		59

# define OMAP_INT_730_DMA_CH13		60

# define OMAP_INT_730_DMA_CH14		61

# define OMAP_INT_730_DMA_CH15		62

# define OMAP_INT_730_NAND		63

/*

 * OMAP-24xx common IRQ numbers

 */

# define OMAP_INT_24XX_STI		4

# define OMAP_INT_24XX_SYS_NIRQ		7

# define OMAP_INT_24XX_L3_IRQ		10

# define OMAP_INT_24XX_PRCM_MPU_IRQ	11

# define OMAP_INT_24XX_SDMA_IRQ0	12

# define OMAP_INT_24XX_SDMA_IRQ1	13

# define OMAP_INT_24XX_SDMA_IRQ2	14

# define OMAP_INT_24XX_SDMA_IRQ3	15

# define OMAP_INT_243X_MCBSP2_IRQ	16

# define OMAP_INT_243X_MCBSP3_IRQ	17

# define OMAP_INT_243X_MCBSP4_IRQ	18

# define OMAP_INT_243X_MCBSP5_IRQ	19

# define OMAP_INT_24XX_GPMC_IRQ		20

# define OMAP_INT_24XX_GUFFAW_IRQ	21

# define OMAP_INT_24XX_IVA_IRQ		22

# define OMAP_INT_24XX_EAC_IRQ		23

# define OMAP_INT_24XX_CAM_IRQ		24

# define OMAP_INT_24XX_DSS_IRQ		25

# define OMAP_INT_24XX_MAIL_U0_MPU	26

# define OMAP_INT_24XX_DSP_UMA		27

# define OMAP_INT_24XX_DSP_MMU		28

# define OMAP_INT_24XX_GPIO_BANK1	29

# define OMAP_INT_24XX_GPIO_BANK2	30

# define OMAP_INT_24XX_GPIO_BANK3	31

# define OMAP_INT_24XX_GPIO_BANK4	32

# define OMAP_INT_243X_GPIO_BANK5	33

# define OMAP_INT_24XX_MAIL_U3_MPU	34

# define OMAP_INT_24XX_WDT3		35

# define OMAP_INT_24XX_WDT4		36

# define OMAP_INT_24XX_GPTIMER1		37

# define OMAP_INT_24XX_GPTIMER2		38

# define OMAP_INT_24XX_GPTIMER3		39

# define OMAP_INT_24XX_GPTIMER4		40

# define OMAP_INT_24XX_GPTIMER5		41

# define OMAP_INT_24XX_GPTIMER6		42

# define OMAP_INT_24XX_GPTIMER7		43

# define OMAP_INT_24XX_GPTIMER8		44

# define OMAP_INT_24XX_GPTIMER9		45

# define OMAP_INT_24XX_GPTIMER10	46

# define OMAP_INT_24XX_GPTIMER11	47

# define OMAP_INT_24XX_GPTIMER12	48

# define OMAP_INT_24XX_PKA_IRQ		50

# define OMAP_INT_24XX_SHA1MD5_IRQ	51

# define OMAP_INT_24XX_RNG_IRQ		52

# define OMAP_INT_24XX_MG_IRQ		53

# define OMAP_INT_24XX_I2C1_IRQ		56

# define OMAP_INT_24XX_I2C2_IRQ		57

# define OMAP_INT_24XX_MCBSP1_IRQ_TX	59

# define OMAP_INT_24XX_MCBSP1_IRQ_RX	60

# define OMAP_INT_24XX_MCBSP2_IRQ_TX	62

# define OMAP_INT_24XX_MCBSP2_IRQ_RX	63

# define OMAP_INT_243X_MCBSP1_IRQ	64

# define OMAP_INT_24XX_MCSPI1_IRQ	65

# define OMAP_INT_24XX_MCSPI2_IRQ	66

# define OMAP_INT_24XX_SSI1_IRQ0	67

# define OMAP_INT_24XX_SSI1_IRQ1	68

# define OMAP_INT_24XX_SSI2_IRQ0	69

# define OMAP_INT_24XX_SSI2_IRQ1	70

# define OMAP_INT_24XX_SSI_GDD_IRQ	71

# define OMAP_INT_24XX_UART1_IRQ	72

# define OMAP_INT_24XX_UART2_IRQ	73

# define OMAP_INT_24XX_UART3_IRQ	74

# define OMAP_INT_24XX_USB_IRQ_GEN	75

# define OMAP_INT_24XX_USB_IRQ_NISO	76

# define OMAP_INT_24XX_USB_IRQ_ISO	77

# define OMAP_INT_24XX_USB_IRQ_HGEN	78

# define OMAP_INT_24XX_USB_IRQ_HSOF	79

# define OMAP_INT_24XX_USB_IRQ_OTG	80

# define OMAP_INT_24XX_VLYNQ_IRQ	81

# define OMAP_INT_24XX_MMC_IRQ		83

# define OMAP_INT_24XX_MS_IRQ		84

# define OMAP_INT_24XX_FAC_IRQ		85

# define OMAP_INT_24XX_MCSPI3_IRQ	91

# define OMAP_INT_243X_HS_USB_MC	92

# define OMAP_INT_243X_HS_USB_DMA	93

# define OMAP_INT_243X_CARKIT		94

# define OMAP_INT_34XX_GPTIMER12	95

/* omap_dma.c */

enum omap_dma_model {

    omap_dma_3_0,

    omap_dma_3_1,

    omap_dma_3_2,

    omap_dma_4,

};

struct soc_dma_s;

struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,

                qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,

                enum omap_dma_model model);

struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,

                struct omap_mpu_state_s *mpu, int fifo,

                int chans, omap_clk iclk, omap_clk fclk);

void omap_dma_reset(struct soc_dma_s *s);

struct dma_irq_map {

    int ih;

    int intr;

};

/* Only used in OMAP DMA 3.x gigacells */

enum omap_dma_port {

    emiff = 0,

    emifs,

    imif,	/* omap16xx: ocp_t1 */

    tipb,

    local,	/* omap16xx: ocp_t2 */

    tipb_mpui,

    __omap_dma_port_last,

};

typedef enum {

    constant = 0,

    post_incremented,

    single_index,

    double_index,

} omap_dma_addressing_t;

/* Only used in OMAP DMA 3.x gigacells */

struct omap_dma_lcd_channel_s {

    enum omap_dma_port src;

    target_phys_addr_t src_f1_top;

    target_phys_addr_t src_f1_bottom;

    target_phys_addr_t src_f2_top;

    target_phys_addr_t src_f2_bottom;

    /* Used in OMAP DMA 3.2 gigacell */

    unsigned char brust_f1;

    unsigned char pack_f1;

    unsigned char data_type_f1;

    unsigned char brust_f2;

    unsigned char pack_f2;

    unsigned char data_type_f2;

    unsigned char end_prog;

    unsigned char repeat;

    unsigned char auto_init;

    unsigned char priority;

    unsigned char fs;

    unsigned char running;

    unsigned char bs;

    unsigned char omap_3_1_compatible_disable;

    unsigned char dst;

    unsigned char lch_type;

    int16_t element_index_f1;

    int16_t element_index_f2;

    int32_t frame_index_f1;

    int32_t frame_index_f2;

    uint16_t elements_f1;

    uint16_t frames_f1;

    uint16_t elements_f2;

    uint16_t frames_f2;

    omap_dma_addressing_t mode_f1;

    omap_dma_addressing_t mode_f2;

    /* Destination port is fixed.  */

    int interrupts;

    int condition;

    int dual;

    int current_frame;

    ram_addr_t phys_framebuffer[2];

    qemu_irq irq;

    struct omap_mpu_state_s *mpu;

} *omap_dma_get_lcdch(struct soc_dma_s *s);

/*

 * DMA request numbers for OMAP1

 * See /usr/include/asm-arm/arch-omap/dma.h in Linux.

 */

# define OMAP_DMA_NO_DEVICE		0

# define OMAP_DMA_MCSI1_TX		1

# define OMAP_DMA_MCSI1_RX		2

# define OMAP_DMA_I2C_RX		3

# define OMAP_DMA_I2C_TX		4

# define OMAP_DMA_EXT_NDMA_REQ0		5

# define OMAP_DMA_EXT_NDMA_REQ1		6

# define OMAP_DMA_UWIRE_TX		7

# define OMAP_DMA_MCBSP1_TX		8

# define OMAP_DMA_MCBSP1_RX		9

# define OMAP_DMA_MCBSP3_TX		10

# define OMAP_DMA_MCBSP3_RX		11

# define OMAP_DMA_UART1_TX		12

# define OMAP_DMA_UART1_RX		13

# define OMAP_DMA_UART2_TX		14

# define OMAP_DMA_UART2_RX		15

# define OMAP_DMA_MCBSP2_TX		16

# define OMAP_DMA_MCBSP2_RX		17

# define OMAP_DMA_UART3_TX		18

# define OMAP_DMA_UART3_RX		19

# define OMAP_DMA_CAMERA_IF_RX		20

# define OMAP_DMA_MMC_TX		21

# define OMAP_DMA_MMC_RX		22

# define OMAP_DMA_NAND			23	/* Not in OMAP310 */

# define OMAP_DMA_IRQ_LCD_LINE		24	/* Not in OMAP310 */

# define OMAP_DMA_MEMORY_STICK		25	/* Not in OMAP310 */