/*

 * QEMU Sun4m & Sun4d & Sun4c System Emulator

 *

 * Copyright (c) 2003-2005 Fabrice Bellard

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */

#include "hw.h"

#include "qemu-timer.h"

#include "sun4m.h"

#include "nvram.h"

#include "sparc32_dma.h"

#include "fdc.h"

#include "sysemu.h"

#include "net.h"

#include "boards.h"

#include "firmware_abi.h"

#include "scsi.h"

#include "pc.h"

#include "isa.h"

#include "fw_cfg.h"

//#define DEBUG_IRQ

/*

 * Sun4m architecture was used in the following machines:

 *

 * SPARCserver 6xxMP/xx

 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),

 * SPARCclassic X (4/10)

 * SPARCstation LX/ZX (4/30)

 * SPARCstation Voyager

 * SPARCstation 10/xx, SPARCserver 10/xx

 * SPARCstation 5, SPARCserver 5

 * SPARCstation 20/xx, SPARCserver 20

 * SPARCstation 4

 *

 * Sun4d architecture was used in the following machines:

 *

 * SPARCcenter 2000

 * SPARCserver 1000

 *

 * Sun4c architecture was used in the following machines:

 * SPARCstation 1/1+, SPARCserver 1/1+

 * SPARCstation SLC

 * SPARCstation IPC

 * SPARCstation ELC

 * SPARCstation IPX

 *

 * See for example: http://www.sunhelp.org/faq/sunref1.html

 */

#ifdef DEBUG_IRQ

#define DPRINTF(fmt, args...)                           \

    do { printf("CPUIRQ: " fmt , ##args); } while (0)

#else

#define DPRINTF(fmt, args...)

#endif

#define KERNEL_LOAD_ADDR     0x00004000

#define CMDLINE_ADDR         0x007ff000

#define INITRD_LOAD_ADDR     0x00800000

#define PROM_SIZE_MAX        (1024 * 1024)

#define PROM_VADDR           0xffd00000

#define PROM_FILENAME        "openbios-sparc32"

#define CFG_ADDR             0xd00000510ULL

#define FW_CFG_SUN4M_DEPTH   (FW_CFG_ARCH_LOCAL + 0x00)

// Control plane, 8-bit and 24-bit planes

#define TCX_SIZE             (9 * 1024 * 1024)

#define MAX_CPUS 16

#define MAX_PILS 16

struct sun4m_hwdef {

    target_phys_addr_t iommu_base, slavio_base;

    target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;

    target_phys_addr_t serial_base, fd_base;

    target_phys_addr_t idreg_base, dma_base, esp_base, le_base;

    target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;

    target_phys_addr_t ecc_base;

    uint32_t ecc_version;

    long vram_size, nvram_size;

    // IRQ numbers are not PIL ones, but master interrupt controller

    // register bit numbers

    int esp_irq, le_irq, clock_irq, clock1_irq;

    int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;

    uint8_t nvram_machine_id;

    uint16_t machine_id;

    uint32_t iommu_version;

    uint32_t intbit_to_level[32];

    uint64_t max_mem;

    const char * const default_cpu_model;

};

#define MAX_IOUNITS 5

struct sun4d_hwdef {

    target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;

    target_phys_addr_t counter_base, nvram_base, ms_kb_base;

    target_phys_addr_t serial_base;

    target_phys_addr_t espdma_base, esp_base;

    target_phys_addr_t ledma_base, le_base;

    target_phys_addr_t tcx_base;

    target_phys_addr_t sbi_base;

    unsigned long vram_size, nvram_size;

    // IRQ numbers are not PIL ones, but SBI register bit numbers

    int esp_irq, le_irq, clock_irq, clock1_irq;

    int ser_irq, ms_kb_irq, me_irq;

    uint8_t nvram_machine_id;

    uint16_t machine_id;

    uint32_t iounit_version;

    uint64_t max_mem;

    const char * const default_cpu_model;

};

struct sun4c_hwdef {

    target_phys_addr_t iommu_base, slavio_base;

    target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;

    target_phys_addr_t serial_base, fd_base;

    target_phys_addr_t idreg_base, dma_base, esp_base, le_base;

    target_phys_addr_t tcx_base, aux1_base;

    long vram_size, nvram_size;

    // IRQ numbers are not PIL ones, but master interrupt controller

    // register bit numbers

    int esp_irq, le_irq, clock_irq, clock1_irq;

    int ser_irq, ms_kb_irq, fd_irq, me_irq;

    uint8_t nvram_machine_id;

    uint16_t machine_id;

    uint32_t iommu_version;

    uint32_t intbit_to_level[32];

    uint64_t max_mem;

    const char * const default_cpu_model;

};

int DMA_get_channel_mode (int nchan)

{

    return 0;

}

int DMA_read_memory (int nchan, void *buf, int pos, int size)

{

    return 0;

}

int DMA_write_memory (int nchan, void *buf, int pos, int size)

{

    return 0;

}

void DMA_hold_DREQ (int nchan) {}

void DMA_release_DREQ (int nchan) {}

void DMA_schedule(int nchan) {}

void DMA_init (int high_page_enable) {}

void DMA_register_channel (int nchan,

                           DMA_transfer_handler transfer_handler,

                           void *opaque)

{

}

static int nvram_boot_set(void *opaque, const char *boot_device)

{

    unsigned int i;

    uint8_t image[sizeof(ohwcfg_v3_t)];

    ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ

    m48t59_t *nvram = (m48t59_t *)opaque;

    for (i = 0; i < sizeof(image); i++)

        image[i] = m48t59_read(nvram, i) & 0xff;

    pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),

            boot_device);

    header->nboot_devices = strlen(boot_device) & 0xff;

    header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));

    for (i = 0; i < sizeof(image); i++)

        m48t59_write(nvram, i, image[i]);

    return 0;

}

static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,

                       const char *boot_devices, ram_addr_t RAM_size,

                       uint32_t kernel_size,

                       int width, int height, int depth,

                       int nvram_machine_id, const char *arch)

{

    unsigned int i;

    uint32_t start, end;

    uint8_t image[0x1ff0];

    ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ

    struct sparc_arch_cfg *sparc_header;

    struct OpenBIOS_nvpart_v1 *part_header;

    memset(image, '\0', sizeof(image));

    // Try to match PPC NVRAM

    pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident),

            "QEMU_BIOS");

    header->struct_version = cpu_to_be32(3); /* structure v3 */

    header->nvram_size = cpu_to_be16(0x2000);

    header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));

    header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));

    pstrcpy((char *)header->arch, sizeof(header->arch), arch);

    header->nb_cpus = smp_cpus & 0xff;

    header->RAM0_base = 0;

    header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);

    pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),

            boot_devices);

    header->nboot_devices = strlen(boot_devices) & 0xff;

    header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR);

    header->kernel_size = cpu_to_be64((uint64_t)kernel_size);

    if (cmdline) {

        pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);

        header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);

        header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));

    }

    // XXX add initrd_image, initrd_size

    header->width = cpu_to_be16(width);

    header->height = cpu_to_be16(height);

    header->depth = cpu_to_be16(depth);

    if (nographic)

        header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);

    header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));

    // Architecture specific header

    start = sizeof(ohwcfg_v3_t);

    sparc_header = (struct sparc_arch_cfg *)&image[start];

    sparc_header->valid = 0;

    start += sizeof(struct sparc_arch_cfg);

    // OpenBIOS nvram variables

    // Variable partition

    part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];

    part_header->signature = OPENBIOS_PART_SYSTEM;

    pstrcpy(part_header->name, sizeof(part_header->name), "system");

    end = start + sizeof(struct OpenBIOS_nvpart_v1);

    for (i = 0; i < nb_prom_envs; i++)

        end = OpenBIOS_set_var(image, end, prom_envs[i]);

    // End marker

    image[end++] = '\0';

    end = start + ((end - start + 15) & ~15);

    OpenBIOS_finish_partition(part_header, end - start);

    // free partition

    start = end;

    part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];

    part_header->signature = OPENBIOS_PART_FREE;

    pstrcpy(part_header->name, sizeof(part_header->name), "free");

    end = 0x1fd0;

    OpenBIOS_finish_partition(part_header, end - start);

    Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,

                    nvram_machine_id);

    for (i = 0; i < sizeof(image); i++)

        m48t59_write(nvram, i, image[i]);

    qemu_register_boot_set(nvram_boot_set, nvram);

}

static void *slavio_intctl;

void pic_info(void)

{

    if (slavio_intctl)

        slavio_pic_info(slavio_intctl);

}

void irq_info(void)

{

    if (slavio_intctl)

        slavio_irq_info(slavio_intctl);

}

void cpu_check_irqs(CPUState *env)

{

    if (env->pil_in && (env->interrupt_index == 0 ||

                        (env->interrupt_index & ~15) == TT_EXTINT)) {

        unsigned int i;

        for (i = 15; i > 0; i--) {

            if (env->pil_in & (1 << i)) {

                int old_interrupt = env->interrupt_index;

                env->interrupt_index = TT_EXTINT | i;

                if (old_interrupt != env->interrupt_index) {

                    DPRINTF("Set CPU IRQ %d\n", i);

                    cpu_interrupt(env, CPU_INTERRUPT_HARD);

                }

                break;

            }

        }

    } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {

        DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);

        env->interrupt_index = 0;

        cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);

    }

}

static void cpu_set_irq(void *opaque, int irq, int level)

{

    CPUState *env = opaque;

    if (level) {

        DPRINTF("Raise CPU IRQ %d\n", irq);

        env->halted = 0;

        env->pil_in |= 1 << irq;

        cpu_check_irqs(env);

    } else {

        DPRINTF("Lower CPU IRQ %d\n", irq);

        env->pil_in &= ~(1 << irq);

        cpu_check_irqs(env);

    }

}

static void dummy_cpu_set_irq(void *opaque, int irq, int level)

{

}

static void *slavio_misc;

void qemu_system_powerdown(void)

{

    slavio_set_power_fail(slavio_misc, 1);

}

static void main_cpu_reset(void *opaque)

{

    CPUState *env = opaque;

    cpu_reset(env);

    env->halted = 0;

}

static void secondary_cpu_reset(void *opaque)

{

    CPUState *env = opaque;

    cpu_reset(env);

    env->halted = 1;

}

static void cpu_halt_signal(void *opaque, int irq, int level)

{

    if (level && cpu_single_env)

        cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);

}

static unsigned long sun4m_load_kernel(const char *kernel_filename,

                                       const char *initrd_filename,

                                       ram_addr_t RAM_size)

{

    int linux_boot;

    unsigned int i;

    long initrd_size, kernel_size;

    linux_boot = (kernel_filename != NULL);

    kernel_size = 0;

    if (linux_boot) {

        kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,

                               NULL);

        if (kernel_size < 0)

            kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,

                                    RAM_size - KERNEL_LOAD_ADDR);

        if (kernel_size < 0)

            kernel_size = load_image_targphys(kernel_filename,

                                              KERNEL_LOAD_ADDR,

                                              RAM_size - KERNEL_LOAD_ADDR);

        if (kernel_size < 0) {

            fprintf(stderr, "qemu: could not load kernel '%s'\n",

                    kernel_filename);

            exit(1);

        }

        /* load initrd */

        initrd_size = 0;

        if (initrd_filename) {

            initrd_size = load_image_targphys(initrd_filename,

                                              INITRD_LOAD_ADDR,

                                              RAM_size - INITRD_LOAD_ADDR);

            if (initrd_size < 0) {

                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",

                        initrd_filename);

                exit(1);

            }

        }

        if (initrd_size > 0) {

            for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {

                if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS

                    stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);

                    stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);

                    break;

                }

            }

        }

    }

    return kernel_size;

}

static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,

                          const char *boot_device,

                          DisplayState *ds, const char *kernel_filename,

                          const char *kernel_cmdline,

                          const char *initrd_filename, const char *cpu_model)

{

    CPUState *env, *envs[MAX_CPUS];

    unsigned int i;

    void *iommu, *espdma, *ledma, *main_esp, *nvram;

    qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,

        *espdma_irq, *ledma_irq;

    qemu_irq *esp_reset, *le_reset;

    qemu_irq *fdc_tc;

    qemu_irq *cpu_halt;

    ram_addr_t ram_offset, prom_offset, tcx_offset, idreg_offset;

    unsigned long kernel_size;

    int ret;

    char buf[1024];

    BlockDriverState *fd[MAX_FD];

    int drive_index;

    void *fw_cfg;

    /* init CPUs */

    if (!cpu_model)

        cpu_model = hwdef->default_cpu_model;

    for(i = 0; i < smp_cpus; i++) {

        env = cpu_init(cpu_model);

        if (!env) {

            fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");

            exit(1);

        }

        cpu_sparc_set_id(env, i);

        envs[i] = env;

        if (i == 0) {

            qemu_register_reset(main_cpu_reset, env);

        } else {

            qemu_register_reset(secondary_cpu_reset, env);

            env->halted = 1;

        }

        cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);

        env->prom_addr = hwdef->slavio_base;

    }

    for (i = smp_cpus; i < MAX_CPUS; i++)

        cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);

    /* allocate RAM */

    if ((uint64_t)RAM_size > hwdef->max_mem) {

        fprintf(stderr,

                "qemu: Too much memory for this machine: %d, maximum %d\n",

                (unsigned int)(RAM_size / (1024 * 1024)),

                (unsigned int)(hwdef->max_mem / (1024 * 1024)));

        exit(1);

    }

    ram_offset = qemu_ram_alloc(RAM_size);

    cpu_register_physical_memory(0, RAM_size, ram_offset);

    /* load boot prom */

    prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);

    cpu_register_physical_memory(hwdef->slavio_base,

                                 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &

                                 TARGET_PAGE_MASK,

                                 prom_offset | IO_MEM_ROM);

    if (bios_name == NULL)

        bios_name = PROM_FILENAME;

    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);

    ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);

    if (ret < 0 || ret > PROM_SIZE_MAX)

        ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);

    if (ret < 0 || ret > PROM_SIZE_MAX) {

        fprintf(stderr, "qemu: could not load prom '%s'\n",

                buf);

        exit(1);

    }

    /* set up devices */

    slavio_intctl = slavio_intctl_init(hwdef->intctl_base,

                                       hwdef->intctl_base + 0x10000ULL,

                                       &hwdef->intbit_to_level[0],

                                       &slavio_irq, &slavio_cpu_irq,

                                       cpu_irqs,

                                       hwdef->clock_irq);

    if (hwdef->idreg_base != (target_phys_addr_t)-1) {

        static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };

        idreg_offset = qemu_ram_alloc(sizeof(idreg_data));

        cpu_register_physical_memory(hwdef->idreg_base, sizeof(idreg_data),

                                     idreg_offset | IO_MEM_ROM);

        cpu_physical_memory_write_rom(hwdef->idreg_base, idreg_data,

                                      sizeof(idreg_data));

    }

    iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,

                       slavio_irq[hwdef->me_irq]);

    espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],

                              iommu, &espdma_irq, &esp_reset);

    ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,

                             slavio_irq[hwdef->le_irq], iommu, &ledma_irq,

                             &le_reset);

    if (graphic_depth != 8 && graphic_depth != 24) {