symbian-qemu-0.9.1-12/qemu-symbian-svp/plugins/syborg_serial.py
author Masaki Hosaka <hosaka@isb.co.jp>
Wed, 24 Mar 2010 13:46:59 +0900
changeset 52 0dfaca43d90e
parent 36 a587897e3bb2
permissions -rw-r--r--
Added web camera drivers and QEMU plug-in for obtaining and transferring dummy data.
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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parents:
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import qemu
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a587897e3bb2 start phonesim-integ
cdavies@GUAR
parents: 1
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import os
a587897e3bb2 start phonesim-integ
cdavies@GUAR
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import sys
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class syborg_serial(qemu.devclass):
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  REG_ID           = 0
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  REG_DATA         = 1
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  REG_FIFO_COUNT   = 2
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  REG_INT_ENABLE   = 3
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  REG_DMA_TX_ADDR  = 4
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  REG_DMA_TX_COUNT = 5 # triggers dma
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  REG_DMA_RX_ADDR  = 6
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  REG_DMA_RX_COUNT = 7 # triggers dma
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  def update_irq(self):
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    level = 2 # TX DMA complete
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    if len(self.fifo) > 0:
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      level |= 1 # FIFO not empty
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    if self.dma_rx_count == 0:
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      level |= 4 # RX DMA complete
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    self.set_irq_level(0, (level & self.int_enable) != 0)
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  def can_receive(self):
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    return self.fifo_size - len(self.fifo)
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  def receive(self, buf):
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    for x in buf:
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      ch = ord(x)
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      if self.dma_rx_count > 0:
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        self.dma_writeb(self.dma_rx_addr, ch)
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        self.dma_rx_addr += 1
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        self.dma_rx_count -= 1
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      else:
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        self.fifo.append(ch)
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    self.update_irq()
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  def do_dma_tx(self, count):
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    # TODO: Optimize block transmits.
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    while count > 0:
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      ch = self.dma_readb(self.dma_tx_addr)
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      self.chardev.write(ch)
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      self.dma_tx_addr += 1
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      count -= 1
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    self.update_irq()
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  def dma_rx_start(self, count):
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    while (count > 0) and (len(self.fifo) > 0):
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      ch = self.fifo.pop(0)
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      self.dma_writeb(self.dma_rx_addr, ch)
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      self.dma_rx_addr += 1
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      count -= 1
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    self.dma_rx_count = count
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    self.update_irq()
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  def create(self):
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    self.fifo_size = self.properties["fifo-size"]
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    self.chardev = self.properties["chardev"]
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    self.fifo=[]
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    self.int_enable = 0
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    self.chardev.set_handlers(self.can_receive, self.receive)
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    self.dma_tx_addr = 0
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    self.dma_rx_addr = 0
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    self.dma_rx_count = 0
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  def read_reg(self, offset):
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    offset >>= 2
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    if offset == self.REG_ID:
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      return 0xc51d0001
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    elif offset == self.REG_DATA:
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      if len(self.fifo) == 0:
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        return 0xffffffff
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      val = self.fifo.pop(0)
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      self.update_irq();
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      return val
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    elif offset == self.REG_FIFO_COUNT:
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      return len(self.fifo)
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    elif offset == self.REG_INT_ENABLE:
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      return self.int_enable
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    elif offset == self.REG_DMA_TX_ADDR:
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      return self.dma_tx_addr
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    elif offset == self.REG_DMA_TX_COUNT:
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      return 0
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    elif offset == self.REG_DMA_RX_ADDR:
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      return self.dma_rx_addr
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    elif offset == self.REG_DMA_RX_COUNT:
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    86
      return self.dma_rx_count
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    return 0
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  def write_reg(self, offset, value):
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    offset >>= 2
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    if offset == self.REG_DATA:
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      self.chardev.write(value)
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    93
    elif offset == self.REG_INT_ENABLE:
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      self.int_enable = value & 7
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    95
      self.update_irq()
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    96
    elif offset == self.REG_DMA_TX_ADDR:
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    97
      self.dma_tx_addr = value
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    98
    elif offset == self.REG_DMA_TX_COUNT:
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      self.do_dma_tx(value)
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   100
    elif offset == self.REG_DMA_RX_ADDR:
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   101
      self.dma_rx_addr = value
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   102
    elif offset == self.REG_DMA_RX_COUNT:
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   103
      self.dma_rx_start(value)
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   104
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  def save(self, f):
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   106
    f.put_u32(self.fifo_size)
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   107
    f.put_u32(self.int_enable)
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   108
    f.put_u32(self.dma_tx_addr)
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   109
    f.put_u32(self.dma_rx_addr)
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   110
    f.put_u32(self.dma_rx_count)
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   111
    f.put_u32(len(self.fifo))
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   112
    for x in self.fifo:
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   113
      f.put_u32(x)
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   114
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  def load(self, f):
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   116
    if self.fifo_size != f.get_u32():
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   117
      raise ValueError, "fifo size mismatch"
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parents:
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   118
    self.int_enable = f.get_u32()
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    self.dma_tx_addr = f.get_u32()
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    self.dma_rx_addr = f.get_u32()
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    self.dma_rx_count = f.get_u32()
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    n = f.get_u32()
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    self.fifo = []
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    while n > 0:
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      self.fifo.append(f.get_u32())
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      n -= 1;
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  # Device class properties
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  regions = [qemu.ioregion(0x1000, readl=read_reg, writel=write_reg)]
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  irqs = 1
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  name = "syborg,serial"
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  properties = {"fifo-size":16, "chardev":None, "target": ""}
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qemu.register_device(syborg_serial)
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class syborg_modem(syborg_serial):
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  def create(self):
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    syborg_serial.create(self)
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    # Find the path of the emulator executable
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    path = os.path.dirname(sys.executable)
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    executable = os.getenv("SVP_MODEM_EXECUTABLE")
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    if None == executable:
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      executable = self.modem_executable
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    executable_name = executable
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    fq_executable = os.path.join(path, executable_name)
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    print(fq_executable)
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    if not os.path.exists(fq_executable):
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      executable_name = executable + ".exe"
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      fq_executable = os.path.join(path, executable_name)
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      if not os.path.exists(fq_executable):
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        sys.exit("Could not locate modem executable '" + executable + "' in '" + path + "'!\n")
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    # Attempt to find the correct port from the target spec
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    target = self.properties["target"]
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    if not(target.startswith("tcp:") or target.startswith("udp:")):
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      sys.exit("Modem device is not accessed via an acceptable socket.")
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    target = target[4:]
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    port_start_idx = target.find(":");
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    port_end_idx = target.find(",")
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    if -1 == port_start_idx:
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      sys.exit("Could not extract port number from modem target spec!")
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    port = ""
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    if -1 == port_end_idx:
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      port = target[port_start_idx + 1:]
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    else:
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      port = target[port_start_idx + 1:port_end_idx]
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    os.spawnl(os.P_NOWAIT, fq_executable, executable_name, "-p", port)
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    self.chardev.handle_connect()
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  # Name property override.
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  name = "syborg,serial,modem"
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  # Default modem executable
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  modem_executable = "phonesim"
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qemu.register_device(syborg_modem)