/*

 * Tiny Code Generator for QEMU

 *

 * Copyright (c) 2008 Andrzej Zaborowski

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */

#ifndef NDEBUG

static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {

    "%r0",

    "%r1",

    "%r2",

    "%r3",

    "%r4",

    "%r5",

    "%r6",

    "%r7",

    "%r8",

    "%r9",

    "%r10",

    "%r11",

    "%r12",

    "%r13",

    "%r14",

};

#endif

static const int tcg_target_reg_alloc_order[] = {

    TCG_REG_R0,

    TCG_REG_R1,

    TCG_REG_R2,

    TCG_REG_R3,

    TCG_REG_R4,

    TCG_REG_R5,

    TCG_REG_R6,

    TCG_REG_R7,

    TCG_REG_R8,

    TCG_REG_R9,

    TCG_REG_R10,

    TCG_REG_R11,

    TCG_REG_R12,

    TCG_REG_R13,

    TCG_REG_R14,

};

static const int tcg_target_call_iarg_regs[4] = {

    TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3

};

static const int tcg_target_call_oarg_regs[2] = {

    TCG_REG_R0, TCG_REG_R1

};

static void patch_reloc(uint8_t *code_ptr, int type,

                tcg_target_long value, tcg_target_long addend)

{

    switch (type) {

    case R_ARM_ABS32:

        *(uint32_t *) code_ptr = value;

        break;

    case R_ARM_CALL:

    case R_ARM_JUMP24:

    default:

        tcg_abort();

    case R_ARM_PC24:

        *(uint32_t *) code_ptr = ((*(uint32_t *) code_ptr) & 0xff000000) |

                (((value - ((tcg_target_long) code_ptr + 8)) >> 2) & 0xffffff);

        break;

    }

}

/* maximum number of register used for input function arguments */

static inline int tcg_target_get_call_iarg_regs_count(int flags)

{

    return 4;

}

/* parse target specific constraints */

static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)

{

    const char *ct_str;

    ct_str = *pct_str;

    switch (ct_str[0]) {

    case 'r':

#ifndef CONFIG_SOFTMMU

    case 'd':

    case 'D':

    case 'x':

    case 'X':

#endif

        ct->ct |= TCG_CT_REG;

        tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);

        break;

#ifdef CONFIG_SOFTMMU

    /* qemu_ld/st inputs (unless 'X', 'd' or 'D') */

    case 'x':

        ct->ct |= TCG_CT_REG;

        tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);

        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);

        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);

        break;

    /* qemu_ld64 data_reg */

    case 'd':

        ct->ct |= TCG_CT_REG;

        tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);

        /* r1 is still needed to load data_reg2, so don't use it.  */

        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);

        break;

    /* qemu_ld/st64 data_reg2 */

    case 'D':

        ct->ct |= TCG_CT_REG;

        tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);

        /* r0, r1 and optionally r2 will be overwritten by the address

         * and the low word of data, so don't use these.  */

        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);

        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);

# if TARGET_LONG_BITS == 64

        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);

# endif

        break;

# if TARGET_LONG_BITS == 64

    /* qemu_ld/st addr_reg2 */

    case 'X':

        ct->ct |= TCG_CT_REG;

        tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);

        /* r0 will be overwritten by the low word of base, so don't use it.  */

        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);

        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);

        break;

# endif

#endif

    case '1':

        ct->ct |= TCG_CT_REG;

        tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);

        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);

        break;

    case '2':

        ct->ct |= TCG_CT_REG;

        tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);

        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);

        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);

        break;

    default:

        return -1;

    }

    ct_str++;

    *pct_str = ct_str;

    return 0;

}

/* Test if a constant matches the constraint.

 * TODO: define constraints for:

 *

 * ldr/str offset:   between -0xfff and 0xfff

 * ldrh/strh offset: between -0xff and 0xff

 * mov operand2:     values represented with x << (2 * y), x < 0x100

 * add, sub, eor...: ditto

 */

static inline int tcg_target_const_match(tcg_target_long val,

                const TCGArgConstraint *arg_ct)

{

    int ct;

    ct = arg_ct->ct;

    if (ct & TCG_CT_CONST)

        return 1;

    else

        return 0;

}

enum arm_data_opc_e {

    ARITH_AND = 0x0,

    ARITH_EOR = 0x1,

    ARITH_SUB = 0x2,

    ARITH_RSB = 0x3,

    ARITH_ADD = 0x4,

    ARITH_ADC = 0x5,

    ARITH_SBC = 0x6,

    ARITH_RSC = 0x7,

    ARITH_TST = 0x8,

    ARITH_CMP = 0xa,

    ARITH_CMN = 0xb,

    ARITH_ORR = 0xc,

    ARITH_MOV = 0xd,

    ARITH_BIC = 0xe,

    ARITH_MVN = 0xf,

};

#define TO_CPSR(opc) \

  ((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20)

#define SHIFT_IMM_LSL(im)	(((im) << 7) | 0x00)

#define SHIFT_IMM_LSR(im)	(((im) << 7) | 0x20)

#define SHIFT_IMM_ASR(im)	(((im) << 7) | 0x40)

#define SHIFT_IMM_ROR(im)	(((im) << 7) | 0x60)

#define SHIFT_REG_LSL(rs)	(((rs) << 8) | 0x10)

#define SHIFT_REG_LSR(rs)	(((rs) << 8) | 0x30)

#define SHIFT_REG_ASR(rs)	(((rs) << 8) | 0x50)

#define SHIFT_REG_ROR(rs)	(((rs) << 8) | 0x70)

enum arm_cond_code_e {

    COND_EQ = 0x0,

    COND_NE = 0x1,

    COND_CS = 0x2,	/* Unsigned greater or equal */

    COND_CC = 0x3,	/* Unsigned less than */

    COND_MI = 0x4,	/* Negative */

    COND_PL = 0x5,	/* Zero or greater */

    COND_VS = 0x6,	/* Overflow */

    COND_VC = 0x7,	/* No overflow */

    COND_HI = 0x8,	/* Unsigned greater than */

    COND_LS = 0x9,	/* Unsigned less or equal */

    COND_GE = 0xa,

    COND_LT = 0xb,

    COND_GT = 0xc,

    COND_LE = 0xd,

    COND_AL = 0xe,

};

static const uint8_t tcg_cond_to_arm_cond[10] = {

    [TCG_COND_EQ] = COND_EQ,

    [TCG_COND_NE] = COND_NE,

    [TCG_COND_LT] = COND_LT,

    [TCG_COND_GE] = COND_GE,

    [TCG_COND_LE] = COND_LE,

    [TCG_COND_GT] = COND_GT,

    /* unsigned */

    [TCG_COND_LTU] = COND_CC,

    [TCG_COND_GEU] = COND_CS,

    [TCG_COND_LEU] = COND_LS,

    [TCG_COND_GTU] = COND_HI,

};

static inline void tcg_out_bx(TCGContext *s, int cond, int rn)

{

    tcg_out32(s, (cond << 28) | 0x012fff10 | rn);

}

static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)

{

    tcg_out32(s, (cond << 28) | 0x0a000000 |

                    (((offset - 8) >> 2) & 0x00ffffff));

}

static inline void tcg_out_b_noaddr(TCGContext *s, int cond)

{

#ifdef WORDS_BIGENDIAN

    tcg_out8(s, (cond << 4) | 0x0a);

    s->code_ptr += 3;

#else

    s->code_ptr += 3;

    tcg_out8(s, (cond << 4) | 0x0a);

#endif

}

static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset)

{

    tcg_out32(s, (cond << 28) | 0x0b000000 |

                    (((offset - 8) >> 2) & 0x00ffffff));

}

static inline void tcg_out_dat_reg(TCGContext *s,

                int cond, int opc, int rd, int rn, int rm, int shift)

{

    tcg_out32(s, (cond << 28) | (0 << 25) | (opc << 21) | TO_CPSR(opc) |

                    (rn << 16) | (rd << 12) | shift | rm);

}

static inline void tcg_out_dat_reg2(TCGContext *s,

                int cond, int opc0, int opc1, int rd0, int rd1,

                int rn0, int rn1, int rm0, int rm1, int shift)

{

    if (rd0 == rn1 || rd0 == rm1) {

        tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |

                        (rn0 << 16) | (8 << 12) | shift | rm0);

        tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |

                        (rn1 << 16) | (rd1 << 12) | shift | rm1);

        tcg_out_dat_reg(s, cond, ARITH_MOV,

                        rd0, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));

    } else {

        tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |

                        (rn0 << 16) | (rd0 << 12) | shift | rm0);

        tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |

                        (rn1 << 16) | (rd1 << 12) | shift | rm1);

    }

}

static inline void tcg_out_dat_imm(TCGContext *s,

                int cond, int opc, int rd, int rn, int im)

{

    tcg_out32(s, (cond << 28) | (1 << 25) | (opc << 21) | TO_CPSR(opc) |

                    (rn << 16) | (rd << 12) | im);

}

static inline void tcg_out_movi32(TCGContext *s,

                int cond, int rd, int32_t arg)

{

    int offset = (uint32_t) arg - ((uint32_t) s->code_ptr + 8);

    /* TODO: This is very suboptimal, we can easily have a constant

     * pool somewhere after all the instructions.  */

    if (arg < 0 && arg > -0x100)

        return tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, (~arg) & 0xff);

    if (offset < 0x100 && offset > -0x100)

        return offset >= 0 ?

                tcg_out_dat_imm(s, cond, ARITH_ADD, rd, 15, offset) :

                tcg_out_dat_imm(s, cond, ARITH_SUB, rd, 15, -offset);

    tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, arg & 0xff);

    if (arg & 0x0000ff00)

        tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,

                        ((arg >>  8) & 0xff) | 0xc00);

    if (arg & 0x00ff0000)

        tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,

                        ((arg >> 16) & 0xff) | 0x800);

    if (arg & 0xff000000)

        tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,

                        ((arg >> 24) & 0xff) | 0x400);

}

static inline void tcg_out_mul32(TCGContext *s,

                int cond, int rd, int rs, int rm)

{

    if (rd != rm)

        tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |

                        (rs << 8) | 0x90 | rm);

    else if (rd != rs)

        tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |

                        (rm << 8) | 0x90 | rs);

    else {

        tcg_out32(s, (cond << 28) | ( 8 << 16) | (0 << 12) |

                        (rs << 8) | 0x90 | rm);

        tcg_out_dat_reg(s, cond, ARITH_MOV,

                        rd, 0, 8, SHIFT_IMM_LSL(0));

    }

}

static inline void tcg_out_umull32(TCGContext *s,

                int cond, int rd0, int rd1, int rs, int rm)

{

    if (rd0 != rm && rd1 != rm)

        tcg_out32(s, (cond << 28) | 0x800090 |

                        (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);

    else if (rd0 != rs && rd1 != rs)

        tcg_out32(s, (cond << 28) | 0x800090 |

                        (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);

    else {

        tcg_out_dat_reg(s, cond, ARITH_MOV,

                        TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));

        tcg_out32(s, (cond << 28) | 0x800098 |

                        (rd1 << 16) | (rd0 << 12) | (rs << 8));

    }

}

static inline void tcg_out_smull32(TCGContext *s,

                int cond, int rd0, int rd1, int rs, int rm)

{

    if (rd0 != rm && rd1 != rm)

        tcg_out32(s, (cond << 28) | 0xc00090 |

                        (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);

    else if (rd0 != rs && rd1 != rs)

        tcg_out32(s, (cond << 28) | 0xc00090 |

                        (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);

    else {

        tcg_out_dat_reg(s, cond, ARITH_MOV,

                        TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));

        tcg_out32(s, (cond << 28) | 0xc00098 |

                        (rd1 << 16) | (rd0 << 12) | (rs << 8));

    }

}

static inline void tcg_out_ld32_12(TCGContext *s, int cond,

                int rd, int rn, tcg_target_long im)

{

    if (im >= 0)

        tcg_out32(s, (cond << 28) | 0x05900000 |

                        (rn << 16) | (rd << 12) | (im & 0xfff));

    else

        tcg_out32(s, (cond << 28) | 0x05100000 |

                        (rn << 16) | (rd << 12) | ((-im) & 0xfff));

}

static inline void tcg_out_st32_12(TCGContext *s, int cond,

                int rd, int rn, tcg_target_long im)

{

    if (im >= 0)

        tcg_out32(s, (cond << 28) | 0x05800000 |

                        (rn << 16) | (rd << 12) | (im & 0xfff));

    else

        tcg_out32(s, (cond << 28) | 0x05000000 |

                        (rn << 16) | (rd << 12) | ((-im) & 0xfff));

}

static inline void tcg_out_ld32_r(TCGContext *s, int cond,

                int rd, int rn, int rm)

{

    tcg_out32(s, (cond << 28) | 0x07900000 |

                    (rn << 16) | (rd << 12) | rm);

}

static inline void tcg_out_st32_r(TCGContext *s, int cond,

                int rd, int rn, int rm)

{

    tcg_out32(s, (cond << 28) | 0x07800000 |

                    (rn << 16) | (rd << 12) | rm);

}

/* Register pre-increment with base writeback.  */

static inline void tcg_out_ld32_rwb(TCGContext *s, int cond,

                int rd, int rn, int rm)

{

    tcg_out32(s, (cond << 28) | 0x07b00000 |

                    (rn << 16) | (rd << 12) | rm);

}

static inline void tcg_out_st32_rwb(TCGContext *s, int cond,

                int rd, int rn, int rm)

{

    tcg_out32(s, (cond << 28) | 0x07a00000 |

                    (rn << 16) | (rd << 12) | rm);

}

static inline void tcg_out_ld16u_8(TCGContext *s, int cond,

                int rd, int rn, tcg_target_long im)

{

    if (im >= 0)

        tcg_out32(s, (cond << 28) | 0x01d000b0 |

                        (rn << 16) | (rd << 12) |

                        ((im & 0xf0) << 4) | (im & 0xf));

    else

        tcg_out32(s, (cond << 28) | 0x015000b0 |

                        (rn << 16) | (rd << 12) |

                        (((-im) & 0xf0) << 4) | ((-im) & 0xf));

}

static inline void tcg_out_st16u_8(TCGContext *s, int cond,

                int rd, int rn, tcg_target_long im)

{

    if (im >= 0)

        tcg_out32(s, (cond << 28) | 0x01c000b0 |

                        (rn << 16) | (rd << 12) |

                        ((im & 0xf0) << 4) | (im & 0xf));

    else

        tcg_out32(s, (cond << 28) | 0x014000b0 |

                        (rn << 16) | (rd << 12) |

                        (((-im) & 0xf0) << 4) | ((-im) & 0xf));

}

static inline void tcg_out_ld16u_r(TCGContext *s, int cond,

                int rd, int rn, int rm)

{

    tcg_out32(s, (cond << 28) | 0x019000b0 |

                    (rn << 16) | (rd << 12) | rm);

}

static inline void tcg_out_st16u_r(TCGContext *s, int cond,

                int rd, int rn, int rm)

{

    tcg_out32(s, (cond << 28) | 0x018000b0 |

                    (rn << 16) | (rd << 12) | rm);

}

static inline void tcg_out_ld16s_8(TCGContext *s, int cond,

                int rd, int rn, tcg_target_long im)

{

    if (im >= 0)

        tcg_out32(s, (cond << 28) | 0x01d000f0 |

                        (rn << 16) | (rd << 12) |

                        ((im & 0xf0) << 4) | (im & 0xf));

    else

        tcg_out32(s, (cond << 28) | 0x015000f0 |

                        (rn << 16) | (rd << 12) |

                        (((-im) & 0xf0) << 4) | ((-im) & 0xf));

}

static inline void tcg_out_st16s_8(TCGContext *s, int cond,

                int rd, int rn, tcg_target_long im)

{

    if (im >= 0)

        tcg_out32(s, (cond << 28) | 0x01c000f0 |

                        (rn << 16) | (rd << 12) |

                        ((im & 0xf0) << 4) | (im & 0xf));

    else

        tcg_out32(s, (cond << 28) | 0x014000f0 |

                        (rn << 16) | (rd << 12) |

                        (((-im) & 0xf0) << 4) | ((-im) & 0xf));

}

static inline void tcg_out_ld16s_r(TCGContext *s, int cond,

                int rd, int rn, int rm)

{

    tcg_out32(s, (cond << 28) | 0x019000f0 |

                    (rn << 16) | (rd << 12) | rm);

}

static inline void tcg_out_st16s_r(TCGContext *s, int cond,

                int rd, int rn, int rm)

{

    tcg_out32(s, (cond << 28) | 0x018000f0 |

                    (rn << 16) | (rd << 12) | rm);

}