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1 /* |
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2 * common defines for all CPUs |
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3 * |
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4 * Copyright (c) 2003 Fabrice Bellard |
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5 * |
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6 * This library is free software; you can redistribute it and/or |
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7 * modify it under the terms of the GNU Lesser General Public |
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8 * License as published by the Free Software Foundation; either |
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9 * version 2 of the License, or (at your option) any later version. |
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10 * |
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11 * This library is distributed in the hope that it will be useful, |
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 * Lesser General Public License for more details. |
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15 * |
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16 * You should have received a copy of the GNU Lesser General Public |
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17 * License along with this library; if not, write to the Free Software |
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18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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19 */ |
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20 #ifndef CPU_DEFS_H |
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21 #define CPU_DEFS_H |
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22 |
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23 #ifndef NEED_CPU_H |
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24 #error cpu.h included from common code |
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25 #endif |
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26 |
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27 #include "config.h" |
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28 #include <setjmp.h> |
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29 #include <inttypes.h> |
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30 #include "osdep.h" |
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31 #include "sys-queue.h" |
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32 |
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33 #ifndef TARGET_LONG_BITS |
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34 #error TARGET_LONG_BITS must be defined before including this header |
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35 #endif |
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36 |
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37 #ifndef TARGET_PHYS_ADDR_BITS |
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38 #if TARGET_LONG_BITS >= HOST_LONG_BITS |
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39 #define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS |
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40 #else |
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41 #define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS |
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42 #endif |
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43 #endif |
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44 |
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45 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) |
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46 |
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47 /* target_ulong is the type of a virtual address */ |
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48 #if TARGET_LONG_SIZE == 4 |
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49 typedef int32_t target_long; |
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50 typedef uint32_t target_ulong; |
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51 #define TARGET_FMT_lx "%08x" |
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52 #define TARGET_FMT_ld "%d" |
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53 #define TARGET_FMT_lu "%u" |
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54 #elif TARGET_LONG_SIZE == 8 |
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55 typedef int64_t target_long; |
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56 typedef uint64_t target_ulong; |
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57 #define TARGET_FMT_lx "%016" PRIx64 |
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58 #define TARGET_FMT_ld "%" PRId64 |
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59 #define TARGET_FMT_lu "%" PRIu64 |
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60 #else |
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61 #error TARGET_LONG_SIZE undefined |
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62 #endif |
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63 |
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64 /* target_phys_addr_t is the type of a physical address (its size can |
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65 be different from 'target_ulong'). We have sizeof(target_phys_addr) |
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66 = max(sizeof(unsigned long), |
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67 sizeof(size_of_target_physical_address)) because we must pass a |
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68 host pointer to memory operations in some cases */ |
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69 |
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70 #if TARGET_PHYS_ADDR_BITS == 32 |
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71 typedef uint32_t target_phys_addr_t; |
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72 #define TARGET_FMT_plx "%08x" |
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73 #elif TARGET_PHYS_ADDR_BITS == 64 |
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74 typedef uint64_t target_phys_addr_t; |
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75 #define TARGET_FMT_plx "%016" PRIx64 |
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76 #else |
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77 #error TARGET_PHYS_ADDR_BITS undefined |
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78 #endif |
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79 |
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80 #define HOST_LONG_SIZE (HOST_LONG_BITS / 8) |
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81 |
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82 #define EXCP_INTERRUPT 0x10000 /* async interruption */ |
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83 #define EXCP_HLT 0x10001 /* hlt instruction reached */ |
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84 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ |
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85 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ |
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86 |
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87 #define TB_JMP_CACHE_BITS 12 |
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88 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) |
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89 |
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90 /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for |
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91 addresses on the same page. The top bits are the same. This allows |
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92 TLB invalidation to quickly clear a subset of the hash table. */ |
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93 #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2) |
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94 #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS) |
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95 #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1) |
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96 #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE) |
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97 |
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98 #define CPU_TLB_BITS 8 |
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99 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS) |
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100 |
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101 #if TARGET_PHYS_ADDR_BITS == 32 && TARGET_LONG_BITS == 32 |
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102 #define CPU_TLB_ENTRY_BITS 4 |
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103 #else |
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104 #define CPU_TLB_ENTRY_BITS 5 |
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105 #endif |
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106 |
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107 typedef struct CPUTLBEntry { |
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108 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address |
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109 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not |
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110 go directly to ram. |
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111 bit 3 : indicates that the entry is invalid |
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112 bit 2..0 : zero |
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113 */ |
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114 target_ulong addr_read; |
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115 target_ulong addr_write; |
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116 target_ulong addr_code; |
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117 /* Addend to virtual address to get physical address. IO accesses |
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118 use the corresponding iotlb value. */ |
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119 #if TARGET_PHYS_ADDR_BITS == 64 |
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120 /* on i386 Linux make sure it is aligned */ |
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121 target_phys_addr_t addend __attribute__((aligned(8))); |
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122 #else |
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123 target_phys_addr_t addend; |
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124 #endif |
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125 /* padding to get a power of two size */ |
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126 uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) - |
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127 (sizeof(target_ulong) * 3 + |
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128 ((-sizeof(target_ulong) * 3) & (sizeof(target_phys_addr_t) - 1)) + |
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129 sizeof(target_phys_addr_t))]; |
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130 } CPUTLBEntry; |
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131 |
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132 #ifdef WORDS_BIGENDIAN |
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133 typedef struct icount_decr_u16 { |
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134 uint16_t high; |
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135 uint16_t low; |
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136 } icount_decr_u16; |
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137 #else |
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138 typedef struct icount_decr_u16 { |
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139 uint16_t low; |
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140 uint16_t high; |
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141 } icount_decr_u16; |
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142 #endif |
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143 |
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144 struct kvm_run; |
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145 struct KVMState; |
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146 |
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147 typedef struct CPUBreakpoint { |
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148 target_ulong pc; |
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149 int flags; /* BP_* */ |
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150 TAILQ_ENTRY(CPUBreakpoint) entry; |
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151 } CPUBreakpoint; |
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152 |
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153 typedef struct CPUWatchpoint { |
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154 target_ulong vaddr; |
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155 target_ulong len_mask; |
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156 int flags; /* BP_* */ |
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157 TAILQ_ENTRY(CPUWatchpoint) entry; |
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158 } CPUWatchpoint; |
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159 |
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160 #define CPU_TEMP_BUF_NLONGS 128 |
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161 #define CPU_COMMON \ |
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162 struct TranslationBlock *current_tb; /* currently executing TB */ \ |
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163 /* soft mmu support */ \ |
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164 /* in order to avoid passing too many arguments to the MMIO \ |
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165 helpers, we store some rarely used information in the CPU \ |
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166 context) */ \ |
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167 unsigned long mem_io_pc; /* host pc at which the memory was \ |
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168 accessed */ \ |
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169 target_ulong mem_io_vaddr; /* target virtual addr at which the \ |
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170 memory was accessed */ \ |
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171 uint32_t halted; /* Nonzero if the CPU is in suspend state */ \ |
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172 uint32_t interrupt_request; \ |
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173 /* The meaning of the MMU modes is defined in the target code. */ \ |
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174 CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ |
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175 target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ |
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176 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ |
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177 /* buffer for temporaries in the code generator */ \ |
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178 long temp_buf[CPU_TEMP_BUF_NLONGS]; \ |
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179 \ |
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180 int64_t icount_extra; /* Instructions until next timer event. */ \ |
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181 /* Number of cycles left, with interrupt flag in high bit. \ |
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182 This allows a single read-compare-cbranch-write sequence to test \ |
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183 for both decrementer underflow and exceptions. */ \ |
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184 union { \ |
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185 uint32_t u32; \ |
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186 icount_decr_u16 u16; \ |
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187 } icount_decr; \ |
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188 uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \ |
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189 \ |
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190 /* from this point: preserved by CPU reset */ \ |
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191 /* ice debug support */ \ |
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192 TAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \ |
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193 int singlestep_enabled; \ |
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194 \ |
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195 TAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \ |
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196 CPUWatchpoint *watchpoint_hit; \ |
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197 \ |
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198 struct GDBRegisterState *gdb_regs; \ |
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199 \ |
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200 /* Core interrupt code */ \ |
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201 jmp_buf jmp_env; \ |
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202 int exception_index; \ |
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203 \ |
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204 int user_mode_only; \ |
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205 \ |
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206 void *next_cpu; /* next CPU sharing TB cache */ \ |
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207 int cpu_index; /* CPU index (informative) */ \ |
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208 int running; /* Nonzero if cpu is currently running(usermode). */ \ |
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209 /* user data */ \ |
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210 void *opaque; \ |
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211 void *qdev; \ |
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212 \ |
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213 const char *cpu_model_str; \ |
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214 struct KVMState *kvm_state; \ |
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215 struct kvm_run *kvm_run; \ |
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216 int kvm_fd; |
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217 |
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218 #endif |