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1 /* |
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2 * QEMU ETRAX DMA Controller. |
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3 * |
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4 * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB. |
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5 * |
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6 * Permission is hereby granted, free of charge, to any person obtaining a copy |
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7 * of this software and associated documentation files (the "Software"), to deal |
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8 * in the Software without restriction, including without limitation the rights |
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9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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10 * copies of the Software, and to permit persons to whom the Software is |
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11 * furnished to do so, subject to the following conditions: |
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12 * |
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13 * The above copyright notice and this permission notice shall be included in |
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14 * all copies or substantial portions of the Software. |
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15 * |
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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22 * THE SOFTWARE. |
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23 */ |
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24 #include <stdio.h> |
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25 #include <sys/time.h> |
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26 #include "hw.h" |
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27 #include "qemu-common.h" |
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28 #include "sysemu.h" |
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29 |
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30 #include "etraxfs_dma.h" |
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31 |
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32 #define D(x) |
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33 |
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34 #define RW_DATA 0x0 |
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35 #define RW_SAVED_DATA 0x58 |
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36 #define RW_SAVED_DATA_BUF 0x5c |
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37 #define RW_GROUP 0x60 |
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38 #define RW_GROUP_DOWN 0x7c |
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39 #define RW_CMD 0x80 |
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40 #define RW_CFG 0x84 |
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41 #define RW_STAT 0x88 |
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42 #define RW_INTR_MASK 0x8c |
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43 #define RW_ACK_INTR 0x90 |
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44 #define R_INTR 0x94 |
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45 #define R_MASKED_INTR 0x98 |
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46 #define RW_STREAM_CMD 0x9c |
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47 |
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48 #define DMA_REG_MAX 0x100 |
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49 |
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50 /* descriptors */ |
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51 |
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52 // ------------------------------------------------------------ dma_descr_group |
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53 typedef struct dma_descr_group { |
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54 struct dma_descr_group *next; |
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55 unsigned eol : 1; |
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56 unsigned tol : 1; |
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57 unsigned bol : 1; |
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58 unsigned : 1; |
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59 unsigned intr : 1; |
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60 unsigned : 2; |
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61 unsigned en : 1; |
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62 unsigned : 7; |
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63 unsigned dis : 1; |
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64 unsigned md : 16; |
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65 struct dma_descr_group *up; |
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66 union { |
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67 struct dma_descr_context *context; |
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68 struct dma_descr_group *group; |
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69 } down; |
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70 } dma_descr_group; |
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71 |
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72 // ---------------------------------------------------------- dma_descr_context |
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73 typedef struct dma_descr_context { |
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74 struct dma_descr_context *next; |
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75 unsigned eol : 1; |
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76 unsigned : 3; |
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77 unsigned intr : 1; |
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78 unsigned : 1; |
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79 unsigned store_mode : 1; |
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80 unsigned en : 1; |
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81 unsigned : 7; |
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82 unsigned dis : 1; |
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83 unsigned md0 : 16; |
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84 unsigned md1; |
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85 unsigned md2; |
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86 unsigned md3; |
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87 unsigned md4; |
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88 struct dma_descr_data *saved_data; |
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89 char *saved_data_buf; |
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90 } dma_descr_context; |
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91 |
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92 // ------------------------------------------------------------- dma_descr_data |
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93 typedef struct dma_descr_data { |
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94 struct dma_descr_data *next; |
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95 char *buf; |
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96 unsigned eol : 1; |
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97 unsigned : 2; |
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98 unsigned out_eop : 1; |
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99 unsigned intr : 1; |
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100 unsigned wait : 1; |
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101 unsigned : 2; |
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102 unsigned : 3; |
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103 unsigned in_eop : 1; |
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104 unsigned : 4; |
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105 unsigned md : 16; |
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106 char *after; |
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107 } dma_descr_data; |
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108 |
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109 /* Constants */ |
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110 enum { |
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111 regk_dma_ack_pkt = 0x00000100, |
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112 regk_dma_anytime = 0x00000001, |
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113 regk_dma_array = 0x00000008, |
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114 regk_dma_burst = 0x00000020, |
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115 regk_dma_client = 0x00000002, |
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116 regk_dma_copy_next = 0x00000010, |
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117 regk_dma_copy_up = 0x00000020, |
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118 regk_dma_data_at_eol = 0x00000001, |
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119 regk_dma_dis_c = 0x00000010, |
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120 regk_dma_dis_g = 0x00000020, |
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121 regk_dma_idle = 0x00000001, |
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122 regk_dma_intern = 0x00000004, |
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123 regk_dma_load_c = 0x00000200, |
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124 regk_dma_load_c_n = 0x00000280, |
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125 regk_dma_load_c_next = 0x00000240, |
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126 regk_dma_load_d = 0x00000140, |
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127 regk_dma_load_g = 0x00000300, |
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128 regk_dma_load_g_down = 0x000003c0, |
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129 regk_dma_load_g_next = 0x00000340, |
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130 regk_dma_load_g_up = 0x00000380, |
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131 regk_dma_next_en = 0x00000010, |
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132 regk_dma_next_pkt = 0x00000010, |
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133 regk_dma_no = 0x00000000, |
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134 regk_dma_only_at_wait = 0x00000000, |
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135 regk_dma_restore = 0x00000020, |
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136 regk_dma_rst = 0x00000001, |
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137 regk_dma_running = 0x00000004, |
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138 regk_dma_rw_cfg_default = 0x00000000, |
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139 regk_dma_rw_cmd_default = 0x00000000, |
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140 regk_dma_rw_intr_mask_default = 0x00000000, |
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141 regk_dma_rw_stat_default = 0x00000101, |
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142 regk_dma_rw_stream_cmd_default = 0x00000000, |
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143 regk_dma_save_down = 0x00000020, |
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144 regk_dma_save_up = 0x00000020, |
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145 regk_dma_set_reg = 0x00000050, |
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146 regk_dma_set_w_size1 = 0x00000190, |
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147 regk_dma_set_w_size2 = 0x000001a0, |
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148 regk_dma_set_w_size4 = 0x000001c0, |
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149 regk_dma_stopped = 0x00000002, |
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150 regk_dma_store_c = 0x00000002, |
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151 regk_dma_store_descr = 0x00000000, |
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152 regk_dma_store_g = 0x00000004, |
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153 regk_dma_store_md = 0x00000001, |
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154 regk_dma_sw = 0x00000008, |
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155 regk_dma_update_down = 0x00000020, |
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156 regk_dma_yes = 0x00000001 |
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157 }; |
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158 |
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159 enum dma_ch_state |
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160 { |
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161 RST = 1, |
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162 STOPPED = 2, |
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163 RUNNING = 4 |
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164 }; |
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165 |
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166 struct fs_dma_channel |
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167 { |
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168 qemu_irq *irq; |
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169 struct etraxfs_dma_client *client; |
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170 |
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171 /* Internal status. */ |
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172 int stream_cmd_src; |
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173 enum dma_ch_state state; |
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174 |
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175 unsigned int input : 1; |
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176 unsigned int eol : 1; |
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177 |
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178 struct dma_descr_group current_g; |
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179 struct dma_descr_context current_c; |
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180 struct dma_descr_data current_d; |
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181 |
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182 /* Controll registers. */ |
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183 uint32_t regs[DMA_REG_MAX]; |
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184 }; |
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185 |
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186 struct fs_dma_ctrl |
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187 { |
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188 int map; |
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189 CPUState *env; |
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190 |
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191 int nr_channels; |
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192 struct fs_dma_channel *channels; |
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193 |
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194 QEMUBH *bh; |
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195 }; |
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196 |
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197 static inline uint32_t channel_reg(struct fs_dma_ctrl *ctrl, int c, int reg) |
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198 { |
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199 return ctrl->channels[c].regs[reg]; |
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200 } |
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201 |
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202 static inline int channel_stopped(struct fs_dma_ctrl *ctrl, int c) |
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203 { |
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204 return channel_reg(ctrl, c, RW_CFG) & 2; |
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205 } |
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206 |
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207 static inline int channel_en(struct fs_dma_ctrl *ctrl, int c) |
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208 { |
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209 return (channel_reg(ctrl, c, RW_CFG) & 1) |
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210 && ctrl->channels[c].client; |
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211 } |
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212 |
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213 static inline int fs_channel(target_phys_addr_t addr) |
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214 { |
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215 /* Every channel has a 0x2000 ctrl register map. */ |
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216 return addr >> 13; |
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217 } |
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218 |
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219 #ifdef USE_THIS_DEAD_CODE |
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220 static void channel_load_g(struct fs_dma_ctrl *ctrl, int c) |
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221 { |
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222 target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP); |
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223 |
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224 /* Load and decode. FIXME: handle endianness. */ |
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225 cpu_physical_memory_read (addr, |
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226 (void *) &ctrl->channels[c].current_g, |
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227 sizeof ctrl->channels[c].current_g); |
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228 } |
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229 |
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230 static void dump_c(int ch, struct dma_descr_context *c) |
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231 { |
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232 printf("%s ch=%d\n", __func__, ch); |
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233 printf("next=%p\n", c->next); |
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234 printf("saved_data=%p\n", c->saved_data); |
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235 printf("saved_data_buf=%p\n", c->saved_data_buf); |
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236 printf("eol=%x\n", (uint32_t) c->eol); |
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237 } |
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238 |
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239 static void dump_d(int ch, struct dma_descr_data *d) |
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240 { |
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241 printf("%s ch=%d\n", __func__, ch); |
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242 printf("next=%p\n", d->next); |
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243 printf("buf=%p\n", d->buf); |
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244 printf("after=%p\n", d->after); |
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245 printf("intr=%x\n", (uint32_t) d->intr); |
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246 printf("out_eop=%x\n", (uint32_t) d->out_eop); |
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247 printf("in_eop=%x\n", (uint32_t) d->in_eop); |
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248 printf("eol=%x\n", (uint32_t) d->eol); |
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249 } |
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250 #endif |
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251 |
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252 static void channel_load_c(struct fs_dma_ctrl *ctrl, int c) |
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253 { |
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254 target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN); |
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255 |
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256 /* Load and decode. FIXME: handle endianness. */ |
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257 cpu_physical_memory_read (addr, |
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258 (void *) &ctrl->channels[c].current_c, |
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259 sizeof ctrl->channels[c].current_c); |
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260 |
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261 D(dump_c(c, &ctrl->channels[c].current_c)); |
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262 /* I guess this should update the current pos. */ |
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263 ctrl->channels[c].regs[RW_SAVED_DATA] = |
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264 (uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data; |
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265 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
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266 (uint32_t)(unsigned long)ctrl->channels[c].current_c.saved_data_buf; |
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267 } |
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268 |
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269 static void channel_load_d(struct fs_dma_ctrl *ctrl, int c) |
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270 { |
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271 target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA); |
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272 |
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273 /* Load and decode. FIXME: handle endianness. */ |
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274 D(printf("%s ch=%d addr=%x\n", __func__, c, addr)); |
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275 cpu_physical_memory_read (addr, |
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276 (void *) &ctrl->channels[c].current_d, |
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277 sizeof ctrl->channels[c].current_d); |
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278 |
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279 D(dump_d(c, &ctrl->channels[c].current_d)); |
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280 ctrl->channels[c].regs[RW_DATA] = addr; |
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281 } |
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282 |
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283 static void channel_store_c(struct fs_dma_ctrl *ctrl, int c) |
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284 { |
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285 target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN); |
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286 |
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287 /* Encode and store. FIXME: handle endianness. */ |
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288 D(printf("%s ch=%d addr=%x\n", __func__, c, addr)); |
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289 D(dump_d(c, &ctrl->channels[c].current_d)); |
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290 cpu_physical_memory_write (addr, |
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291 (void *) &ctrl->channels[c].current_c, |
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292 sizeof ctrl->channels[c].current_c); |
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293 } |
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294 |
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295 static void channel_store_d(struct fs_dma_ctrl *ctrl, int c) |
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296 { |
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297 target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA); |
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298 |
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299 /* Encode and store. FIXME: handle endianness. */ |
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300 D(printf("%s ch=%d addr=%x\n", __func__, c, addr)); |
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301 cpu_physical_memory_write (addr, |
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302 (void *) &ctrl->channels[c].current_d, |
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303 sizeof ctrl->channels[c].current_d); |
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304 } |
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305 |
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306 static inline void channel_stop(struct fs_dma_ctrl *ctrl, int c) |
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307 { |
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308 /* FIXME: */ |
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309 } |
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310 |
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311 static inline void channel_start(struct fs_dma_ctrl *ctrl, int c) |
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312 { |
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313 if (ctrl->channels[c].client) |
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314 { |
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315 ctrl->channels[c].eol = 0; |
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316 ctrl->channels[c].state = RUNNING; |
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317 } else |
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318 printf("WARNING: starting DMA ch %d with no client\n", c); |
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319 |
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320 qemu_bh_schedule_idle(ctrl->bh); |
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321 } |
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322 |
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323 static void channel_continue(struct fs_dma_ctrl *ctrl, int c) |
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324 { |
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325 if (!channel_en(ctrl, c) |
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326 || channel_stopped(ctrl, c) |
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327 || ctrl->channels[c].state != RUNNING |
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328 /* Only reload the current data descriptor if it has eol set. */ |
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329 || !ctrl->channels[c].current_d.eol) { |
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330 D(printf("continue failed ch=%d state=%d stopped=%d en=%d eol=%d\n", |
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331 c, ctrl->channels[c].state, |
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332 channel_stopped(ctrl, c), |
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333 channel_en(ctrl,c), |
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334 ctrl->channels[c].eol)); |
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335 D(dump_d(c, &ctrl->channels[c].current_d)); |
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336 return; |
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337 } |
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338 |
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339 /* Reload the current descriptor. */ |
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340 channel_load_d(ctrl, c); |
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341 |
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342 /* If the current descriptor cleared the eol flag and we had already |
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343 reached eol state, do the continue. */ |
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344 if (!ctrl->channels[c].current_d.eol && ctrl->channels[c].eol) { |
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345 D(printf("continue %d ok %p\n", c, |
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346 ctrl->channels[c].current_d.next)); |
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347 ctrl->channels[c].regs[RW_SAVED_DATA] = |
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348 (uint32_t)(unsigned long)ctrl->channels[c].current_d.next; |
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349 channel_load_d(ctrl, c); |
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350 channel_start(ctrl, c); |
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351 } |
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352 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
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353 (uint32_t)(unsigned long)ctrl->channels[c].current_d.buf; |
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354 } |
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355 |
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356 static void channel_stream_cmd(struct fs_dma_ctrl *ctrl, int c, uint32_t v) |
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357 { |
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358 unsigned int cmd = v & ((1 << 10) - 1); |
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359 |
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360 D(printf("%s ch=%d cmd=%x\n", |
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361 __func__, c, cmd)); |
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362 if (cmd & regk_dma_load_d) { |
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363 channel_load_d(ctrl, c); |
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364 if (cmd & regk_dma_burst) |
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365 channel_start(ctrl, c); |
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366 } |
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367 |
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368 if (cmd & regk_dma_load_c) { |
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369 channel_load_c(ctrl, c); |
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370 channel_start(ctrl, c); |
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371 } |
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372 } |
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373 |
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374 static void channel_update_irq(struct fs_dma_ctrl *ctrl, int c) |
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375 { |
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376 D(printf("%s %d\n", __func__, c)); |
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377 ctrl->channels[c].regs[R_INTR] &= |
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378 ~(ctrl->channels[c].regs[RW_ACK_INTR]); |
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379 |
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380 ctrl->channels[c].regs[R_MASKED_INTR] = |
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381 ctrl->channels[c].regs[R_INTR] |
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382 & ctrl->channels[c].regs[RW_INTR_MASK]; |
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383 |
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384 D(printf("%s: chan=%d masked_intr=%x\n", __func__, |
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385 c, |
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386 ctrl->channels[c].regs[R_MASKED_INTR])); |
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387 |
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388 if (ctrl->channels[c].regs[R_MASKED_INTR]) |
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389 qemu_irq_raise(ctrl->channels[c].irq[0]); |
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390 else |
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391 qemu_irq_lower(ctrl->channels[c].irq[0]); |
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392 } |
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393 |
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394 static int channel_out_run(struct fs_dma_ctrl *ctrl, int c) |
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395 { |
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396 uint32_t len; |
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397 uint32_t saved_data_buf; |
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398 unsigned char buf[2 * 1024]; |
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399 |
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400 if (ctrl->channels[c].eol) |
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401 return 0; |
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402 |
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403 do { |
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404 saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF); |
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405 |
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406 D(printf("ch=%d buf=%x after=%x saved_data_buf=%x\n", |
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407 c, |
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408 (uint32_t)ctrl->channels[c].current_d.buf, |
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409 (uint32_t)ctrl->channels[c].current_d.after, |
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410 saved_data_buf)); |
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411 |
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412 len = (uint32_t)(unsigned long) |
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413 ctrl->channels[c].current_d.after; |
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414 len -= saved_data_buf; |
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415 |
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416 if (len > sizeof buf) |
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417 len = sizeof buf; |
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418 cpu_physical_memory_read (saved_data_buf, buf, len); |
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419 |
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420 D(printf("channel %d pushes %x %u bytes\n", c, |
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421 saved_data_buf, len)); |
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422 |
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423 if (ctrl->channels[c].client->client.push) |
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424 ctrl->channels[c].client->client.push( |
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425 ctrl->channels[c].client->client.opaque, |
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426 buf, len); |
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427 else |
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428 printf("WARNING: DMA ch%d dataloss," |
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429 " no attached client.\n", c); |
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430 |
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431 saved_data_buf += len; |
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432 |
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433 if (saved_data_buf == (uint32_t)(unsigned long) |
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434 ctrl->channels[c].current_d.after) { |
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435 /* Done. Step to next. */ |
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436 if (ctrl->channels[c].current_d.out_eop) { |
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437 /* TODO: signal eop to the client. */ |
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438 D(printf("signal eop\n")); |
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439 } |
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440 if (ctrl->channels[c].current_d.intr) { |
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441 /* TODO: signal eop to the client. */ |
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442 /* data intr. */ |
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443 D(printf("signal intr\n")); |
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444 ctrl->channels[c].regs[R_INTR] |= (1 << 2); |
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445 channel_update_irq(ctrl, c); |
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446 } |
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447 if (ctrl->channels[c].current_d.eol) { |
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448 D(printf("channel %d EOL\n", c)); |
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449 ctrl->channels[c].eol = 1; |
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450 |
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451 /* Mark the context as disabled. */ |
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452 ctrl->channels[c].current_c.dis = 1; |
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453 channel_store_c(ctrl, c); |
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454 |
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455 channel_stop(ctrl, c); |
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456 } else { |
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457 ctrl->channels[c].regs[RW_SAVED_DATA] = |
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458 (uint32_t)(unsigned long)ctrl-> |
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459 channels[c].current_d.next; |
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460 /* Load new descriptor. */ |
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461 channel_load_d(ctrl, c); |
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462 saved_data_buf = (uint32_t)(unsigned long) |
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463 ctrl->channels[c].current_d.buf; |
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464 } |
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465 |
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466 channel_store_d(ctrl, c); |
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467 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = |
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468 saved_data_buf; |
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469 D(dump_d(c, &ctrl->channels[c].current_d)); |
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470 } |
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471 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf; |
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472 } while (!ctrl->channels[c].eol); |
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473 return 1; |
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474 } |
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475 |
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476 static int channel_in_process(struct fs_dma_ctrl *ctrl, int c, |
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477 unsigned char *buf, int buflen, int eop) |
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478 { |
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479 uint32_t len; |
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480 uint32_t saved_data_buf; |
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481 |
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482 if (ctrl->channels[c].eol == 1) |
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483 return 0; |
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484 |
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485 saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF); |
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486 len = (uint32_t)(unsigned long)ctrl->channels[c].current_d.after; |
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487 len -= saved_data_buf; |
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488 |
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489 if (len > buflen) |
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490 len = buflen; |
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491 |
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492 cpu_physical_memory_write (saved_data_buf, buf, len); |
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493 saved_data_buf += len; |
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494 |
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495 if (saved_data_buf == |
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496 (uint32_t)(unsigned long)ctrl->channels[c].current_d.after |
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497 || eop) { |
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498 uint32_t r_intr = ctrl->channels[c].regs[R_INTR]; |
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499 |
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500 D(printf("in dscr end len=%d\n", |
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501 ctrl->channels[c].current_d.after |
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502 - ctrl->channels[c].current_d.buf)); |
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503 ctrl->channels[c].current_d.after = |
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504 (void *)(unsigned long) saved_data_buf; |
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505 |
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506 /* Done. Step to next. */ |
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507 if (ctrl->channels[c].current_d.intr) { |
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508 /* TODO: signal eop to the client. */ |
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509 /* data intr. */ |
|
510 ctrl->channels[c].regs[R_INTR] |= 3; |
|
511 } |
|
512 if (eop) { |
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513 ctrl->channels[c].current_d.in_eop = 1; |
|
514 ctrl->channels[c].regs[R_INTR] |= 8; |
|
515 } |
|
516 if (r_intr != ctrl->channels[c].regs[R_INTR]) |
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517 channel_update_irq(ctrl, c); |
|
518 |
|
519 channel_store_d(ctrl, c); |
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520 D(dump_d(c, &ctrl->channels[c].current_d)); |
|
521 |
|
522 if (ctrl->channels[c].current_d.eol) { |
|
523 D(printf("channel %d EOL\n", c)); |
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524 ctrl->channels[c].eol = 1; |
|
525 |
|
526 /* Mark the context as disabled. */ |
|
527 ctrl->channels[c].current_c.dis = 1; |
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528 channel_store_c(ctrl, c); |
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529 |
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530 channel_stop(ctrl, c); |
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531 } else { |
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532 ctrl->channels[c].regs[RW_SAVED_DATA] = |
|
533 (uint32_t)(unsigned long)ctrl-> |
|
534 channels[c].current_d.next; |
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535 /* Load new descriptor. */ |
|
536 channel_load_d(ctrl, c); |
|
537 saved_data_buf = (uint32_t)(unsigned long) |
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538 ctrl->channels[c].current_d.buf; |
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539 } |
|
540 } |
|
541 |
|
542 ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf; |
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543 return len; |
|
544 } |
|
545 |
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546 static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c) |
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547 { |
|
548 if (ctrl->channels[c].client->client.pull) { |
|
549 ctrl->channels[c].client->client.pull( |
|
550 ctrl->channels[c].client->client.opaque); |
|
551 return 1; |
|
552 } else |
|
553 return 0; |
|
554 } |
|
555 |
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556 static uint32_t dma_rinvalid (void *opaque, target_phys_addr_t addr) |
|
557 { |
|
558 struct fs_dma_ctrl *ctrl = opaque; |
|
559 CPUState *env = ctrl->env; |
|
560 cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n", |
|
561 addr); |
|
562 return 0; |
|
563 } |
|
564 |
|
565 static uint32_t |
|
566 dma_readl (void *opaque, target_phys_addr_t addr) |
|
567 { |
|
568 struct fs_dma_ctrl *ctrl = opaque; |
|
569 int c; |
|
570 uint32_t r = 0; |
|
571 |
|
572 /* Make addr relative to this channel and bounded to nr regs. */ |
|
573 c = fs_channel(addr); |
|
574 addr &= 0xff; |
|
575 switch (addr) |
|
576 { |
|
577 case RW_STAT: |
|
578 r = ctrl->channels[c].state & 7; |
|
579 r |= ctrl->channels[c].eol << 5; |
|
580 r |= ctrl->channels[c].stream_cmd_src << 8; |
|
581 break; |
|
582 |
|
583 default: |
|
584 r = ctrl->channels[c].regs[addr]; |
|
585 D(printf ("%s c=%d addr=%x\n", |
|
586 __func__, c, addr)); |
|
587 break; |
|
588 } |
|
589 return r; |
|
590 } |
|
591 |
|
592 static void |
|
593 dma_winvalid (void *opaque, target_phys_addr_t addr, uint32_t value) |
|
594 { |
|
595 struct fs_dma_ctrl *ctrl = opaque; |
|
596 CPUState *env = ctrl->env; |
|
597 cpu_abort(env, "Unsupported short access. reg=" TARGET_FMT_plx "\n", |
|
598 addr); |
|
599 } |
|
600 |
|
601 static void |
|
602 dma_update_state(struct fs_dma_ctrl *ctrl, int c) |
|
603 { |
|
604 if ((ctrl->channels[c].regs[RW_CFG] & 1) != 3) { |
|
605 if (ctrl->channels[c].regs[RW_CFG] & 2) |
|
606 ctrl->channels[c].state = STOPPED; |
|
607 if (!(ctrl->channels[c].regs[RW_CFG] & 1)) |
|
608 ctrl->channels[c].state = RST; |
|
609 } |
|
610 } |
|
611 |
|
612 static void |
|
613 dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
|
614 { |
|
615 struct fs_dma_ctrl *ctrl = opaque; |
|
616 int c; |
|
617 |
|
618 /* Make addr relative to this channel and bounded to nr regs. */ |
|
619 c = fs_channel(addr); |
|
620 addr &= 0xff; |
|
621 switch (addr) |
|
622 { |
|
623 case RW_DATA: |
|
624 ctrl->channels[c].regs[addr] = value; |
|
625 break; |
|
626 |
|
627 case RW_CFG: |
|
628 ctrl->channels[c].regs[addr] = value; |
|
629 dma_update_state(ctrl, c); |
|
630 break; |
|
631 case RW_CMD: |
|
632 /* continue. */ |
|
633 if (value & ~1) |
|
634 printf("Invalid store to ch=%d RW_CMD %x\n", |
|
635 c, value); |
|
636 ctrl->channels[c].regs[addr] = value; |
|
637 channel_continue(ctrl, c); |
|
638 break; |
|
639 |
|
640 case RW_SAVED_DATA: |
|
641 case RW_SAVED_DATA_BUF: |
|
642 case RW_GROUP: |
|
643 case RW_GROUP_DOWN: |
|
644 ctrl->channels[c].regs[addr] = value; |
|
645 break; |
|
646 |
|
647 case RW_ACK_INTR: |
|
648 case RW_INTR_MASK: |
|
649 ctrl->channels[c].regs[addr] = value; |
|
650 channel_update_irq(ctrl, c); |
|
651 if (addr == RW_ACK_INTR) |
|
652 ctrl->channels[c].regs[RW_ACK_INTR] = 0; |
|
653 break; |
|
654 |
|
655 case RW_STREAM_CMD: |
|
656 if (value & ~1023) |
|
657 printf("Invalid store to ch=%d " |
|
658 "RW_STREAMCMD %x\n", |
|
659 c, value); |
|
660 ctrl->channels[c].regs[addr] = value; |
|
661 D(printf("stream_cmd ch=%d\n", c)); |
|
662 channel_stream_cmd(ctrl, c, value); |
|
663 break; |
|
664 |
|
665 default: |
|
666 D(printf ("%s c=%d %x %x\n", __func__, c, addr)); |
|
667 break; |
|
668 } |
|
669 } |
|
670 |
|
671 static CPUReadMemoryFunc *dma_read[] = { |
|
672 &dma_rinvalid, |
|
673 &dma_rinvalid, |
|
674 &dma_readl, |
|
675 }; |
|
676 |
|
677 static CPUWriteMemoryFunc *dma_write[] = { |
|
678 &dma_winvalid, |
|
679 &dma_winvalid, |
|
680 &dma_writel, |
|
681 }; |
|
682 |
|
683 static int etraxfs_dmac_run(void *opaque) |
|
684 { |
|
685 struct fs_dma_ctrl *ctrl = opaque; |
|
686 int i; |
|
687 int p = 0; |
|
688 |
|
689 for (i = 0; |
|
690 i < ctrl->nr_channels; |
|
691 i++) |
|
692 { |
|
693 if (ctrl->channels[i].state == RUNNING) |
|
694 { |
|
695 if (ctrl->channels[i].input) { |
|
696 p += channel_in_run(ctrl, i); |
|
697 } else { |
|
698 p += channel_out_run(ctrl, i); |
|
699 } |
|
700 } |
|
701 } |
|
702 return p; |
|
703 } |
|
704 |
|
705 int etraxfs_dmac_input(struct etraxfs_dma_client *client, |
|
706 void *buf, int len, int eop) |
|
707 { |
|
708 return channel_in_process(client->ctrl, client->channel, |
|
709 buf, len, eop); |
|
710 } |
|
711 |
|
712 /* Connect an IRQ line with a channel. */ |
|
713 void etraxfs_dmac_connect(void *opaque, int c, qemu_irq *line, int input) |
|
714 { |
|
715 struct fs_dma_ctrl *ctrl = opaque; |
|
716 ctrl->channels[c].irq = line; |
|
717 ctrl->channels[c].input = input; |
|
718 } |
|
719 |
|
720 void etraxfs_dmac_connect_client(void *opaque, int c, |
|
721 struct etraxfs_dma_client *cl) |
|
722 { |
|
723 struct fs_dma_ctrl *ctrl = opaque; |
|
724 cl->ctrl = ctrl; |
|
725 cl->channel = c; |
|
726 ctrl->channels[c].client = cl; |
|
727 } |
|
728 |
|
729 |
|
730 static void DMA_run(void *opaque) |
|
731 { |
|
732 struct fs_dma_ctrl *etraxfs_dmac = opaque; |
|
733 int p = 1; |
|
734 |
|
735 if (vm_running) |
|
736 p = etraxfs_dmac_run(etraxfs_dmac); |
|
737 |
|
738 if (p) |
|
739 qemu_bh_schedule_idle(etraxfs_dmac->bh); |
|
740 } |
|
741 |
|
742 void *etraxfs_dmac_init(CPUState *env, |
|
743 target_phys_addr_t base, int nr_channels) |
|
744 { |
|
745 struct fs_dma_ctrl *ctrl = NULL; |
|
746 |
|
747 ctrl = qemu_mallocz(sizeof *ctrl); |
|
748 if (!ctrl) |
|
749 return NULL; |
|
750 |
|
751 ctrl->bh = qemu_bh_new(DMA_run, ctrl); |
|
752 |
|
753 ctrl->env = env; |
|
754 ctrl->nr_channels = nr_channels; |
|
755 ctrl->channels = qemu_mallocz(sizeof ctrl->channels[0] * nr_channels); |
|
756 if (!ctrl->channels) |
|
757 goto err; |
|
758 |
|
759 ctrl->map = cpu_register_io_memory(0, dma_read, dma_write, ctrl); |
|
760 cpu_register_physical_memory(base, nr_channels * 0x2000, ctrl->map); |
|
761 return ctrl; |
|
762 err: |
|
763 qemu_free(ctrl->channels); |
|
764 qemu_free(ctrl); |
|
765 return NULL; |
|
766 } |