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1 /* |
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2 * QEMU ETRAX System Emulator |
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3 * |
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4 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB. |
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5 * |
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6 * Permission is hereby granted, free of charge, to any person obtaining a copy |
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7 * of this software and associated documentation files (the "Software"), to deal |
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8 * in the Software without restriction, including without limitation the rights |
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9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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10 * copies of the Software, and to permit persons to whom the Software is |
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11 * furnished to do so, subject to the following conditions: |
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12 * |
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13 * The above copyright notice and this permission notice shall be included in |
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14 * all copies or substantial portions of the Software. |
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15 * |
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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22 * THE SOFTWARE. |
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23 */ |
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24 |
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25 #include <stdio.h> |
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26 #include <ctype.h> |
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27 #include "hw.h" |
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28 #include "qemu-char.h" |
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29 |
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30 #define D(x) |
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31 |
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32 #define RW_TR_CTRL 0x00 |
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33 #define RW_TR_DMA_EN 0x04 |
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34 #define RW_REC_CTRL 0x08 |
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35 #define RW_DOUT 0x1c |
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36 #define RS_STAT_DIN 0x20 |
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37 #define R_STAT_DIN 0x24 |
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38 #define RW_INTR_MASK 0x2c |
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39 #define RW_ACK_INTR 0x30 |
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40 #define R_INTR 0x34 |
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41 #define R_MASKED_INTR 0x38 |
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42 |
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43 #define STAT_DAV 16 |
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44 #define STAT_TR_IDLE 22 |
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45 #define STAT_TR_RDY 24 |
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46 |
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47 struct etrax_serial_t |
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48 { |
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49 CPUState *env; |
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50 CharDriverState *chr; |
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51 qemu_irq *irq; |
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52 |
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53 int pending_tx; |
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54 |
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55 /* Control registers. */ |
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56 uint32_t rw_tr_ctrl; |
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57 uint32_t rw_tr_dma_en; |
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58 uint32_t rw_rec_ctrl; |
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59 uint32_t rs_stat_din; |
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60 uint32_t r_stat_din; |
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61 uint32_t rw_intr_mask; |
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62 uint32_t rw_ack_intr; |
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63 uint32_t r_intr; |
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64 uint32_t r_masked_intr; |
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65 }; |
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66 |
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67 static void ser_update_irq(struct etrax_serial_t *s) |
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68 { |
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69 uint32_t o_irq = s->r_masked_intr; |
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70 |
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71 s->r_intr &= ~(s->rw_ack_intr); |
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72 s->r_masked_intr = s->r_intr & s->rw_intr_mask; |
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73 |
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74 if (o_irq != s->r_masked_intr) { |
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75 D(printf("irq_mask=%x r_intr=%x rmi=%x airq=%x \n", |
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76 s->rw_intr_mask, s->r_intr, |
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77 s->r_masked_intr, s->rw_ack_intr)); |
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78 if (s->r_masked_intr) |
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79 qemu_irq_raise(s->irq[0]); |
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80 else |
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81 qemu_irq_lower(s->irq[0]); |
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82 } |
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83 s->rw_ack_intr = 0; |
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84 } |
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85 |
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86 |
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87 static uint32_t ser_readb (void *opaque, target_phys_addr_t addr) |
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88 { |
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89 D(CPUState *env = opaque); |
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90 D(printf ("%s %x\n", __func__, addr)); |
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91 return 0; |
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92 } |
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93 |
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94 static uint32_t ser_readl (void *opaque, target_phys_addr_t addr) |
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95 { |
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96 struct etrax_serial_t *s = opaque; |
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97 D(CPUState *env = s->env); |
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98 uint32_t r = 0; |
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99 |
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100 switch (addr) |
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101 { |
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102 case RW_TR_CTRL: |
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103 r = s->rw_tr_ctrl; |
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104 break; |
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105 case RW_TR_DMA_EN: |
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106 r = s->rw_tr_dma_en; |
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107 break; |
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108 case RS_STAT_DIN: |
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109 r = s->rs_stat_din; |
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110 /* clear dav. */ |
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111 s->rs_stat_din &= ~(1 << STAT_DAV); |
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112 break; |
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113 case R_STAT_DIN: |
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114 r = s->rs_stat_din; |
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115 break; |
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116 case RW_ACK_INTR: |
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117 D(printf("load rw_ack_intr=%x\n", s->rw_ack_intr)); |
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118 r = s->rw_ack_intr; |
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119 break; |
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120 case RW_INTR_MASK: |
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121 r = s->rw_intr_mask; |
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122 break; |
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123 case R_INTR: |
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124 D(printf("load r_intr=%x\n", s->r_intr)); |
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125 r = s->r_intr; |
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126 break; |
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127 case R_MASKED_INTR: |
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128 D(printf("load r_maked_intr=%x\n", s->r_masked_intr)); |
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129 r = s->r_masked_intr; |
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130 break; |
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131 |
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132 default: |
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133 D(printf ("%s %x\n", __func__, addr)); |
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134 break; |
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135 } |
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136 return r; |
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137 } |
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138 |
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139 static void |
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140 ser_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) |
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141 { |
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142 D(struct etrax_serial_t *s = opaque); |
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143 D(CPUState *env = s->env); |
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144 D(printf ("%s %x %x\n", __func__, addr, value)); |
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145 } |
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146 static void |
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147 ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
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148 { |
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149 struct etrax_serial_t *s = opaque; |
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150 unsigned char ch = value; |
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151 D(CPUState *env = s->env); |
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152 |
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153 switch (addr) |
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154 { |
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155 case RW_TR_CTRL: |
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156 D(printf("rw_tr_ctrl=%x\n", value)); |
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157 s->rw_tr_ctrl = value; |
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158 break; |
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159 case RW_TR_DMA_EN: |
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160 D(printf("rw_tr_dma_en=%x\n", value)); |
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161 s->rw_tr_dma_en = value; |
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162 break; |
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163 case RW_DOUT: |
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164 qemu_chr_write(s->chr, &ch, 1); |
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165 s->r_intr |= 1; |
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166 s->pending_tx = 1; |
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167 break; |
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168 case RW_ACK_INTR: |
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169 D(printf("rw_ack_intr=%x\n", value)); |
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170 s->rw_ack_intr = value; |
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171 if (s->pending_tx && (s->rw_ack_intr & 1)) { |
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172 s->r_intr |= 1; |
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173 s->pending_tx = 0; |
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174 s->rw_ack_intr &= ~1; |
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175 } |
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176 break; |
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177 case RW_INTR_MASK: |
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178 D(printf("r_intr_mask=%x\n", value)); |
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179 s->rw_intr_mask = value; |
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180 break; |
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181 default: |
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182 D(printf ("%s %x %x\n", __func__, addr, value)); |
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183 break; |
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184 } |
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185 ser_update_irq(s); |
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186 } |
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187 |
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188 static CPUReadMemoryFunc *ser_read[] = { |
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189 &ser_readb, |
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190 &ser_readb, |
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191 &ser_readl, |
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192 }; |
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193 |
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194 static CPUWriteMemoryFunc *ser_write[] = { |
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195 &ser_writeb, |
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196 &ser_writeb, |
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197 &ser_writel, |
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198 }; |
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199 |
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200 static void serial_receive(void *opaque, const uint8_t *buf, int size) |
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201 { |
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202 struct etrax_serial_t *s = opaque; |
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203 |
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204 s->r_intr |= 8; |
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205 s->rs_stat_din &= ~0xff; |
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206 s->rs_stat_din |= (buf[0] & 0xff); |
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207 s->rs_stat_din |= (1 << STAT_DAV); /* dav. */ |
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208 ser_update_irq(s); |
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209 } |
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210 |
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211 static int serial_can_receive(void *opaque) |
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212 { |
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213 struct etrax_serial_t *s = opaque; |
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214 int r; |
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215 |
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216 /* Is the receiver enabled? */ |
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217 r = s->rw_rec_ctrl & 1; |
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218 |
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219 /* Pending rx data? */ |
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220 r |= !(s->r_intr & 8); |
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221 return r; |
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222 } |
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223 |
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224 static void serial_event(void *opaque, int event) |
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225 { |
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226 |
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227 } |
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228 |
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229 void etraxfs_ser_init(CPUState *env, qemu_irq *irq, CharDriverState *chr, |
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230 target_phys_addr_t base) |
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231 { |
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232 struct etrax_serial_t *s; |
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233 int ser_regs; |
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234 |
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235 s = qemu_mallocz(sizeof *s); |
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236 if (!s) |
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237 return; |
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238 |
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239 s->env = env; |
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240 s->irq = irq; |
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241 s->chr = chr; |
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242 |
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243 /* transmitter begins ready and idle. */ |
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244 s->rs_stat_din |= (1 << STAT_TR_RDY); |
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245 s->rs_stat_din |= (1 << STAT_TR_IDLE); |
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246 |
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247 qemu_chr_add_handlers(chr, serial_can_receive, serial_receive, |
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248 serial_event, s); |
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249 |
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250 ser_regs = cpu_register_io_memory(0, ser_read, ser_write, s); |
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251 cpu_register_physical_memory (base, 0x3c, ser_regs); |
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252 } |