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1 /* |
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2 * QEMU Firmware configuration device emulation |
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3 * |
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4 * Copyright (c) 2008 Gleb Natapov |
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5 * |
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6 * Permission is hereby granted, free of charge, to any person obtaining a copy |
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7 * of this software and associated documentation files (the "Software"), to deal |
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8 * in the Software without restriction, including without limitation the rights |
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9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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10 * copies of the Software, and to permit persons to whom the Software is |
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11 * furnished to do so, subject to the following conditions: |
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12 * |
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13 * The above copyright notice and this permission notice shall be included in |
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14 * all copies or substantial portions of the Software. |
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15 * |
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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22 * THE SOFTWARE. |
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23 */ |
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24 #include "hw.h" |
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25 #include "sysemu.h" |
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26 #include "isa.h" |
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27 #include "fw_cfg.h" |
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28 |
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29 /* debug firmware config */ |
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30 //#define DEBUG_FW_CFG |
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31 |
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32 #ifdef DEBUG_FW_CFG |
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33 #define FW_CFG_DPRINTF(fmt, args...) \ |
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34 do { printf("FW_CFG: " fmt , ##args); } while (0) |
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35 #else |
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36 #define FW_CFG_DPRINTF(fmt, args...) |
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37 #endif |
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38 |
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39 #define FW_CFG_SIZE 2 |
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40 |
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41 typedef struct _FWCfgEntry { |
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42 uint16_t len; |
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43 uint8_t *data; |
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44 void *callback_opaque; |
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45 FWCfgCallback callback; |
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46 } FWCfgEntry; |
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47 |
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48 typedef struct _FWCfgState { |
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49 FWCfgEntry entries[2][FW_CFG_MAX_ENTRY]; |
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50 uint16_t cur_entry; |
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51 uint16_t cur_offset; |
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52 } FWCfgState; |
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53 |
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54 static void fw_cfg_write(FWCfgState *s, uint8_t value) |
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55 { |
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56 int arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL); |
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57 FWCfgEntry *e = &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK]; |
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58 |
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59 FW_CFG_DPRINTF("write %d\n", value); |
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60 |
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61 if (s->cur_entry & FW_CFG_WRITE_CHANNEL && s->cur_offset < e->len) { |
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62 e->data[s->cur_offset++] = value; |
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63 if (s->cur_offset == e->len) { |
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64 e->callback(e->callback_opaque, e->data); |
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65 s->cur_offset = 0; |
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66 } |
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67 } |
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68 } |
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69 |
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70 static int fw_cfg_select(FWCfgState *s, uint16_t key) |
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71 { |
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72 int ret; |
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73 |
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74 s->cur_offset = 0; |
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75 if ((key & FW_CFG_ENTRY_MASK) >= FW_CFG_MAX_ENTRY) { |
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76 s->cur_entry = FW_CFG_INVALID; |
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77 ret = 0; |
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78 } else { |
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79 s->cur_entry = key; |
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80 ret = 1; |
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81 } |
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82 |
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83 FW_CFG_DPRINTF("select key %d (%sfound)\n", key, ret ? "" : "not "); |
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84 |
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85 return ret; |
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86 } |
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87 |
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88 static uint8_t fw_cfg_read(FWCfgState *s) |
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89 { |
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90 int arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL); |
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91 FWCfgEntry *e = &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK]; |
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92 uint8_t ret; |
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93 |
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94 if (s->cur_entry == FW_CFG_INVALID || !e->data || s->cur_offset >= e->len) |
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95 ret = 0; |
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96 else |
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97 ret = e->data[s->cur_offset++]; |
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98 |
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99 FW_CFG_DPRINTF("read %d\n", ret); |
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100 |
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101 return ret; |
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102 } |
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103 |
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104 static uint32_t fw_cfg_io_readb(void *opaque, uint32_t addr) |
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105 { |
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106 return fw_cfg_read(opaque); |
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107 } |
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108 |
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109 static void fw_cfg_io_writeb(void *opaque, uint32_t addr, uint32_t value) |
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110 { |
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111 return fw_cfg_write(opaque, (uint8_t)value); |
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112 } |
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113 |
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114 static void fw_cfg_io_writew(void *opaque, uint32_t addr, uint32_t value) |
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115 { |
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116 fw_cfg_select(opaque, (uint16_t)value); |
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117 } |
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118 |
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119 static uint32_t fw_cfg_mem_readb(void *opaque, target_phys_addr_t addr) |
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120 { |
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121 return fw_cfg_read(opaque); |
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122 } |
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123 |
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124 static void fw_cfg_mem_writeb(void *opaque, target_phys_addr_t addr, |
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125 uint32_t value) |
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126 { |
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127 return fw_cfg_write(opaque, (uint8_t)value); |
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128 } |
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129 |
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130 static void fw_cfg_mem_writew(void *opaque, target_phys_addr_t addr, |
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131 uint32_t value) |
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132 { |
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133 fw_cfg_select(opaque, (uint16_t)value); |
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134 } |
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135 |
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136 static CPUReadMemoryFunc *fw_cfg_ctl_mem_read[3] = { |
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137 NULL, |
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138 NULL, |
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139 NULL, |
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140 }; |
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141 |
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142 static CPUWriteMemoryFunc *fw_cfg_ctl_mem_write[3] = { |
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143 NULL, |
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144 fw_cfg_mem_writew, |
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145 NULL, |
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146 }; |
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147 |
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148 static CPUReadMemoryFunc *fw_cfg_data_mem_read[3] = { |
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149 fw_cfg_mem_readb, |
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150 NULL, |
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151 NULL, |
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152 }; |
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153 |
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154 static CPUWriteMemoryFunc *fw_cfg_data_mem_write[3] = { |
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155 fw_cfg_mem_writeb, |
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156 NULL, |
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157 NULL, |
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158 }; |
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159 |
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160 static void fw_cfg_reset(void *opaque) |
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161 { |
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162 FWCfgState *s = opaque; |
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163 |
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164 fw_cfg_select(s, 0); |
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165 } |
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166 |
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167 static void fw_cfg_save(QEMUFile *f, void *opaque) |
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168 { |
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169 FWCfgState *s = opaque; |
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170 |
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171 qemu_put_be16s(f, &s->cur_entry); |
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172 qemu_put_be16s(f, &s->cur_offset); |
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173 } |
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174 |
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175 static int fw_cfg_load(QEMUFile *f, void *opaque, int version_id) |
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176 { |
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177 FWCfgState *s = opaque; |
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178 |
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179 if (version_id > 1) |
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180 return -EINVAL; |
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181 |
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182 qemu_get_be16s(f, &s->cur_entry); |
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183 qemu_get_be16s(f, &s->cur_offset); |
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184 |
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185 return 0; |
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186 } |
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187 |
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188 int fw_cfg_add_bytes(void *opaque, uint16_t key, uint8_t *data, uint16_t len) |
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189 { |
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190 FWCfgState *s = opaque; |
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191 int arch = !!(key & FW_CFG_ARCH_LOCAL); |
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192 |
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193 key &= FW_CFG_ENTRY_MASK; |
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194 |
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195 if (key >= FW_CFG_MAX_ENTRY) |
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196 return 0; |
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197 |
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198 s->entries[arch][key].data = data; |
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199 s->entries[arch][key].len = len; |
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200 |
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201 return 1; |
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202 } |
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203 |
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204 int fw_cfg_add_i16(void *opaque, uint16_t key, uint16_t value) |
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205 { |
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206 uint16_t *copy; |
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207 |
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208 copy = qemu_malloc(sizeof(value)); |
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209 if (!copy) |
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210 return 0; |
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211 *copy = cpu_to_le16(value); |
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212 return fw_cfg_add_bytes(opaque, key, (uint8_t *)copy, sizeof(value)); |
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213 } |
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214 |
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215 int fw_cfg_add_i32(void *opaque, uint16_t key, uint32_t value) |
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216 { |
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217 uint32_t *copy; |
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218 |
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219 copy = qemu_malloc(sizeof(value)); |
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220 if (!copy) |
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221 return 0; |
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222 *copy = cpu_to_le32(value); |
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223 return fw_cfg_add_bytes(opaque, key, (uint8_t *)copy, sizeof(value)); |
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224 } |
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225 |
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226 int fw_cfg_add_i64(void *opaque, uint16_t key, uint64_t value) |
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227 { |
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228 uint64_t *copy; |
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229 |
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230 copy = qemu_malloc(sizeof(value)); |
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231 if (!copy) |
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232 return 0; |
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233 *copy = cpu_to_le64(value); |
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234 return fw_cfg_add_bytes(opaque, key, (uint8_t *)copy, sizeof(value)); |
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235 } |
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236 |
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237 int fw_cfg_add_callback(void *opaque, uint16_t key, FWCfgCallback callback, |
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238 void *callback_opaque, uint8_t *data, size_t len) |
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239 { |
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240 FWCfgState *s = opaque; |
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241 int arch = !!(key & FW_CFG_ARCH_LOCAL); |
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242 |
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243 if (!(key & FW_CFG_WRITE_CHANNEL)) |
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244 return 0; |
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245 |
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246 key &= FW_CFG_ENTRY_MASK; |
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247 |
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248 if (key >= FW_CFG_MAX_ENTRY || len > 65535) |
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249 return 0; |
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250 |
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251 s->entries[arch][key].data = data; |
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252 s->entries[arch][key].len = len; |
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253 s->entries[arch][key].callback_opaque = callback_opaque; |
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254 s->entries[arch][key].callback = callback; |
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255 |
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256 return 1; |
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257 } |
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258 |
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259 void *fw_cfg_init(uint32_t ctl_port, uint32_t data_port, |
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260 target_phys_addr_t ctl_addr, target_phys_addr_t data_addr) |
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261 { |
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262 FWCfgState *s; |
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263 int io_ctl_memory, io_data_memory; |
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264 |
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265 s = qemu_mallocz(sizeof(FWCfgState)); |
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266 if (!s) |
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267 return NULL; |
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268 |
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269 if (ctl_port) { |
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270 register_ioport_write(ctl_port, 2, 2, fw_cfg_io_writew, s); |
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271 } |
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272 if (data_port) { |
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273 register_ioport_read(data_port, 1, 1, fw_cfg_io_readb, s); |
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274 register_ioport_write(data_port, 1, 1, fw_cfg_io_writeb, s); |
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275 } |
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276 if (ctl_addr) { |
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277 io_ctl_memory = cpu_register_io_memory(0, fw_cfg_ctl_mem_read, |
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278 fw_cfg_ctl_mem_write, s); |
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279 cpu_register_physical_memory(ctl_addr, FW_CFG_SIZE, io_ctl_memory); |
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280 } |
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281 if (data_addr) { |
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282 io_data_memory = cpu_register_io_memory(0, fw_cfg_data_mem_read, |
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283 fw_cfg_data_mem_write, s); |
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284 cpu_register_physical_memory(data_addr, FW_CFG_SIZE, io_data_memory); |
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285 } |
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286 fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (uint8_t *)"QEMU", 4); |
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287 fw_cfg_add_bytes(s, FW_CFG_UUID, qemu_uuid, 16); |
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288 fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)nographic); |
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289 fw_cfg_add_i16(s, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); |
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290 |
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291 register_savevm("fw_cfg", -1, 1, fw_cfg_save, fw_cfg_load, s); |
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292 qemu_register_reset(fw_cfg_reset, s); |
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293 fw_cfg_reset(s); |
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294 |
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295 return s; |
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296 } |