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1 /* |
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2 * QEMU GT64120 PCI host |
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3 * |
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4 * Copyright (c) 2006,2007 Aurelien Jarno |
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5 * |
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6 * Permission is hereby granted, free of charge, to any person obtaining a copy |
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7 * of this software and associated documentation files (the "Software"), to deal |
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8 * in the Software without restriction, including without limitation the rights |
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9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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10 * copies of the Software, and to permit persons to whom the Software is |
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11 * furnished to do so, subject to the following conditions: |
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12 * |
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13 * The above copyright notice and this permission notice shall be included in |
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14 * all copies or substantial portions of the Software. |
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15 * |
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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22 * THE SOFTWARE. |
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23 */ |
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24 |
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25 #include "hw.h" |
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26 #include "mips.h" |
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27 #include "pci.h" |
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28 #include "pc.h" |
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29 |
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30 typedef target_phys_addr_t pci_addr_t; |
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31 #include "pci_host.h" |
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32 |
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33 //#define DEBUG |
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34 |
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35 #ifdef DEBUG |
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36 #define dprintf(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__) |
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37 #else |
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38 #define dprintf(fmt, ...) |
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39 #endif |
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40 |
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41 #define GT_REGS (0x1000 >> 2) |
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42 |
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43 /* CPU Configuration */ |
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44 #define GT_CPU (0x000 >> 2) |
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45 #define GT_MULTI (0x120 >> 2) |
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46 |
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47 /* CPU Address Decode */ |
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48 #define GT_SCS10LD (0x008 >> 2) |
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49 #define GT_SCS10HD (0x010 >> 2) |
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50 #define GT_SCS32LD (0x018 >> 2) |
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51 #define GT_SCS32HD (0x020 >> 2) |
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52 #define GT_CS20LD (0x028 >> 2) |
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53 #define GT_CS20HD (0x030 >> 2) |
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54 #define GT_CS3BOOTLD (0x038 >> 2) |
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55 #define GT_CS3BOOTHD (0x040 >> 2) |
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56 #define GT_PCI0IOLD (0x048 >> 2) |
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57 #define GT_PCI0IOHD (0x050 >> 2) |
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58 #define GT_PCI0M0LD (0x058 >> 2) |
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59 #define GT_PCI0M0HD (0x060 >> 2) |
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60 #define GT_PCI0M1LD (0x080 >> 2) |
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61 #define GT_PCI0M1HD (0x088 >> 2) |
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62 #define GT_PCI1IOLD (0x090 >> 2) |
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63 #define GT_PCI1IOHD (0x098 >> 2) |
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64 #define GT_PCI1M0LD (0x0a0 >> 2) |
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65 #define GT_PCI1M0HD (0x0a8 >> 2) |
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66 #define GT_PCI1M1LD (0x0b0 >> 2) |
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67 #define GT_PCI1M1HD (0x0b8 >> 2) |
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68 #define GT_ISD (0x068 >> 2) |
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69 |
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70 #define GT_SCS10AR (0x0d0 >> 2) |
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71 #define GT_SCS32AR (0x0d8 >> 2) |
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72 #define GT_CS20R (0x0e0 >> 2) |
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73 #define GT_CS3BOOTR (0x0e8 >> 2) |
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74 |
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75 #define GT_PCI0IOREMAP (0x0f0 >> 2) |
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76 #define GT_PCI0M0REMAP (0x0f8 >> 2) |
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77 #define GT_PCI0M1REMAP (0x100 >> 2) |
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78 #define GT_PCI1IOREMAP (0x108 >> 2) |
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79 #define GT_PCI1M0REMAP (0x110 >> 2) |
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80 #define GT_PCI1M1REMAP (0x118 >> 2) |
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81 |
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82 /* CPU Error Report */ |
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83 #define GT_CPUERR_ADDRLO (0x070 >> 2) |
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84 #define GT_CPUERR_ADDRHI (0x078 >> 2) |
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85 #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */ |
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86 #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */ |
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87 #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */ |
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88 |
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89 /* CPU Sync Barrier */ |
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90 #define GT_PCI0SYNC (0x0c0 >> 2) |
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91 #define GT_PCI1SYNC (0x0c8 >> 2) |
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92 |
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93 /* SDRAM and Device Address Decode */ |
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94 #define GT_SCS0LD (0x400 >> 2) |
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95 #define GT_SCS0HD (0x404 >> 2) |
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96 #define GT_SCS1LD (0x408 >> 2) |
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97 #define GT_SCS1HD (0x40c >> 2) |
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98 #define GT_SCS2LD (0x410 >> 2) |
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99 #define GT_SCS2HD (0x414 >> 2) |
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100 #define GT_SCS3LD (0x418 >> 2) |
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101 #define GT_SCS3HD (0x41c >> 2) |
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102 #define GT_CS0LD (0x420 >> 2) |
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103 #define GT_CS0HD (0x424 >> 2) |
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104 #define GT_CS1LD (0x428 >> 2) |
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105 #define GT_CS1HD (0x42c >> 2) |
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106 #define GT_CS2LD (0x430 >> 2) |
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107 #define GT_CS2HD (0x434 >> 2) |
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108 #define GT_CS3LD (0x438 >> 2) |
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109 #define GT_CS3HD (0x43c >> 2) |
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110 #define GT_BOOTLD (0x440 >> 2) |
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111 #define GT_BOOTHD (0x444 >> 2) |
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112 #define GT_ADERR (0x470 >> 2) |
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113 |
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114 /* SDRAM Configuration */ |
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115 #define GT_SDRAM_CFG (0x448 >> 2) |
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116 #define GT_SDRAM_OPMODE (0x474 >> 2) |
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117 #define GT_SDRAM_BM (0x478 >> 2) |
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118 #define GT_SDRAM_ADDRDECODE (0x47c >> 2) |
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119 |
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120 /* SDRAM Parameters */ |
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121 #define GT_SDRAM_B0 (0x44c >> 2) |
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122 #define GT_SDRAM_B1 (0x450 >> 2) |
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123 #define GT_SDRAM_B2 (0x454 >> 2) |
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124 #define GT_SDRAM_B3 (0x458 >> 2) |
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125 |
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126 /* Device Parameters */ |
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127 #define GT_DEV_B0 (0x45c >> 2) |
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128 #define GT_DEV_B1 (0x460 >> 2) |
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129 #define GT_DEV_B2 (0x464 >> 2) |
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130 #define GT_DEV_B3 (0x468 >> 2) |
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131 #define GT_DEV_BOOT (0x46c >> 2) |
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132 |
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133 /* ECC */ |
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134 #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */ |
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135 #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */ |
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136 #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */ |
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137 #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */ |
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138 #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */ |
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139 |
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140 /* DMA Record */ |
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141 #define GT_DMA0_CNT (0x800 >> 2) |
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142 #define GT_DMA1_CNT (0x804 >> 2) |
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143 #define GT_DMA2_CNT (0x808 >> 2) |
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144 #define GT_DMA3_CNT (0x80c >> 2) |
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145 #define GT_DMA0_SA (0x810 >> 2) |
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146 #define GT_DMA1_SA (0x814 >> 2) |
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147 #define GT_DMA2_SA (0x818 >> 2) |
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148 #define GT_DMA3_SA (0x81c >> 2) |
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149 #define GT_DMA0_DA (0x820 >> 2) |
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150 #define GT_DMA1_DA (0x824 >> 2) |
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151 #define GT_DMA2_DA (0x828 >> 2) |
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152 #define GT_DMA3_DA (0x82c >> 2) |
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153 #define GT_DMA0_NEXT (0x830 >> 2) |
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154 #define GT_DMA1_NEXT (0x834 >> 2) |
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155 #define GT_DMA2_NEXT (0x838 >> 2) |
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156 #define GT_DMA3_NEXT (0x83c >> 2) |
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157 #define GT_DMA0_CUR (0x870 >> 2) |
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158 #define GT_DMA1_CUR (0x874 >> 2) |
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159 #define GT_DMA2_CUR (0x878 >> 2) |
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160 #define GT_DMA3_CUR (0x87c >> 2) |
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161 |
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162 /* DMA Channel Control */ |
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163 #define GT_DMA0_CTRL (0x840 >> 2) |
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164 #define GT_DMA1_CTRL (0x844 >> 2) |
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165 #define GT_DMA2_CTRL (0x848 >> 2) |
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166 #define GT_DMA3_CTRL (0x84c >> 2) |
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167 |
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168 /* DMA Arbiter */ |
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169 #define GT_DMA_ARB (0x860 >> 2) |
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170 |
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171 /* Timer/Counter */ |
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172 #define GT_TC0 (0x850 >> 2) |
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173 #define GT_TC1 (0x854 >> 2) |
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174 #define GT_TC2 (0x858 >> 2) |
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175 #define GT_TC3 (0x85c >> 2) |
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176 #define GT_TC_CONTROL (0x864 >> 2) |
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177 |
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178 /* PCI Internal */ |
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179 #define GT_PCI0_CMD (0xc00 >> 2) |
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180 #define GT_PCI0_TOR (0xc04 >> 2) |
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181 #define GT_PCI0_BS_SCS10 (0xc08 >> 2) |
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182 #define GT_PCI0_BS_SCS32 (0xc0c >> 2) |
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183 #define GT_PCI0_BS_CS20 (0xc10 >> 2) |
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184 #define GT_PCI0_BS_CS3BT (0xc14 >> 2) |
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185 #define GT_PCI1_IACK (0xc30 >> 2) |
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186 #define GT_PCI0_IACK (0xc34 >> 2) |
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187 #define GT_PCI0_BARE (0xc3c >> 2) |
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188 #define GT_PCI0_PREFMBR (0xc40 >> 2) |
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189 #define GT_PCI0_SCS10_BAR (0xc48 >> 2) |
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190 #define GT_PCI0_SCS32_BAR (0xc4c >> 2) |
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191 #define GT_PCI0_CS20_BAR (0xc50 >> 2) |
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192 #define GT_PCI0_CS3BT_BAR (0xc54 >> 2) |
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193 #define GT_PCI0_SSCS10_BAR (0xc58 >> 2) |
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194 #define GT_PCI0_SSCS32_BAR (0xc5c >> 2) |
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195 #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2) |
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196 #define GT_PCI1_CMD (0xc80 >> 2) |
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197 #define GT_PCI1_TOR (0xc84 >> 2) |
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198 #define GT_PCI1_BS_SCS10 (0xc88 >> 2) |
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199 #define GT_PCI1_BS_SCS32 (0xc8c >> 2) |
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200 #define GT_PCI1_BS_CS20 (0xc90 >> 2) |
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201 #define GT_PCI1_BS_CS3BT (0xc94 >> 2) |
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202 #define GT_PCI1_BARE (0xcbc >> 2) |
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203 #define GT_PCI1_PREFMBR (0xcc0 >> 2) |
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204 #define GT_PCI1_SCS10_BAR (0xcc8 >> 2) |
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205 #define GT_PCI1_SCS32_BAR (0xccc >> 2) |
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206 #define GT_PCI1_CS20_BAR (0xcd0 >> 2) |
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207 #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2) |
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208 #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2) |
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209 #define GT_PCI1_SSCS32_BAR (0xcdc >> 2) |
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210 #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2) |
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211 #define GT_PCI1_CFGADDR (0xcf0 >> 2) |
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212 #define GT_PCI1_CFGDATA (0xcf4 >> 2) |
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213 #define GT_PCI0_CFGADDR (0xcf8 >> 2) |
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214 #define GT_PCI0_CFGDATA (0xcfc >> 2) |
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215 |
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216 /* Interrupts */ |
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217 #define GT_INTRCAUSE (0xc18 >> 2) |
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218 #define GT_INTRMASK (0xc1c >> 2) |
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219 #define GT_PCI0_ICMASK (0xc24 >> 2) |
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220 #define GT_PCI0_SERR0MASK (0xc28 >> 2) |
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221 #define GT_CPU_INTSEL (0xc70 >> 2) |
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222 #define GT_PCI0_INTSEL (0xc74 >> 2) |
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223 #define GT_HINTRCAUSE (0xc98 >> 2) |
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224 #define GT_HINTRMASK (0xc9c >> 2) |
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225 #define GT_PCI0_HICMASK (0xca4 >> 2) |
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226 #define GT_PCI1_SERR1MASK (0xca8 >> 2) |
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227 |
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228 |
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229 typedef PCIHostState GT64120PCIState; |
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230 |
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231 #define PCI_MAPPING_ENTRY(regname) \ |
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232 target_phys_addr_t regname ##_start; \ |
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233 target_phys_addr_t regname ##_length; \ |
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234 int regname ##_handle |
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235 |
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236 typedef struct GT64120State { |
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237 GT64120PCIState *pci; |
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238 uint32_t regs[GT_REGS]; |
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239 PCI_MAPPING_ENTRY(PCI0IO); |
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240 PCI_MAPPING_ENTRY(ISD); |
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241 } GT64120State; |
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242 |
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243 /* Adjust range to avoid touching space which isn't mappable via PCI */ |
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244 /* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000 |
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245 0x1fc00000 - 0x1fd00000 */ |
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246 static void check_reserved_space (target_phys_addr_t *start, |
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247 target_phys_addr_t *length) |
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248 { |
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249 target_phys_addr_t begin = *start; |
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250 target_phys_addr_t end = *start + *length; |
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251 |
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252 if (end >= 0x1e000000LL && end < 0x1f100000LL) |
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253 end = 0x1e000000LL; |
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254 if (begin >= 0x1e000000LL && begin < 0x1f100000LL) |
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255 begin = 0x1f100000LL; |
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256 if (end >= 0x1fc00000LL && end < 0x1fd00000LL) |
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257 end = 0x1fc00000LL; |
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258 if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL) |
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259 begin = 0x1fd00000LL; |
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260 /* XXX: This is broken when a reserved range splits the requested range */ |
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261 if (end >= 0x1f100000LL && begin < 0x1e000000LL) |
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262 end = 0x1e000000LL; |
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263 if (end >= 0x1fd00000LL && begin < 0x1fc00000LL) |
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264 end = 0x1fc00000LL; |
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265 |
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266 *start = begin; |
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267 *length = end - begin; |
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268 } |
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269 |
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270 static void gt64120_isd_mapping(GT64120State *s) |
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271 { |
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272 target_phys_addr_t start = s->regs[GT_ISD] << 21; |
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273 target_phys_addr_t length = 0x1000; |
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274 |
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275 if (s->ISD_length) |
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276 cpu_register_physical_memory(s->ISD_start, s->ISD_length, |
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277 IO_MEM_UNASSIGNED); |
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278 check_reserved_space(&start, &length); |
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279 length = 0x1000; |
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280 /* Map new address */ |
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281 dprintf("ISD: %x@%x -> %x@%x, %x\n", s->ISD_length, s->ISD_start, |
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282 length, start, s->ISD_handle); |
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283 s->ISD_start = start; |
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284 s->ISD_length = length; |
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285 cpu_register_physical_memory(s->ISD_start, s->ISD_length, s->ISD_handle); |
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286 } |
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287 |
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288 static void gt64120_pci_mapping(GT64120State *s) |
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289 { |
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290 /* Update IO mapping */ |
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291 if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) |
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292 { |
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293 /* Unmap old IO address */ |
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294 if (s->PCI0IO_length) |
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295 { |
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296 cpu_register_physical_memory(s->PCI0IO_start, s->PCI0IO_length, IO_MEM_UNASSIGNED); |
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297 } |
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298 /* Map new IO address */ |
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299 s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21; |
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300 s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) - (s->regs[GT_PCI0IOLD] & 0x7f)) << 21; |
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301 isa_mem_base = s->PCI0IO_start; |
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302 isa_mmio_init(s->PCI0IO_start, s->PCI0IO_length); |
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303 } |
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304 } |
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305 |
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306 static void gt64120_writel (void *opaque, target_phys_addr_t addr, |
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307 uint32_t val) |
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308 { |
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309 GT64120State *s = opaque; |
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310 uint32_t saddr; |
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311 |
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312 if (!(s->regs[GT_CPU] & 0x00001000)) |
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313 val = bswap32(val); |
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314 |
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315 saddr = (addr & 0xfff) >> 2; |
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316 switch (saddr) { |
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317 |
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318 /* CPU Configuration */ |
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319 case GT_CPU: |
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320 s->regs[GT_CPU] = val; |
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321 break; |
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322 case GT_MULTI: |
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323 /* Read-only register as only one GT64xxx is present on the CPU bus */ |
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324 break; |
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325 |
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326 /* CPU Address Decode */ |
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327 case GT_PCI0IOLD: |
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328 s->regs[GT_PCI0IOLD] = val & 0x00007fff; |
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329 s->regs[GT_PCI0IOREMAP] = val & 0x000007ff; |
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330 gt64120_pci_mapping(s); |
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331 break; |
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332 case GT_PCI0M0LD: |
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333 s->regs[GT_PCI0M0LD] = val & 0x00007fff; |
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334 s->regs[GT_PCI0M0REMAP] = val & 0x000007ff; |
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335 break; |
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336 case GT_PCI0M1LD: |
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337 s->regs[GT_PCI0M1LD] = val & 0x00007fff; |
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338 s->regs[GT_PCI0M1REMAP] = val & 0x000007ff; |
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339 break; |
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340 case GT_PCI1IOLD: |
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341 s->regs[GT_PCI1IOLD] = val & 0x00007fff; |
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342 s->regs[GT_PCI1IOREMAP] = val & 0x000007ff; |
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343 break; |
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344 case GT_PCI1M0LD: |
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345 s->regs[GT_PCI1M0LD] = val & 0x00007fff; |
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346 s->regs[GT_PCI1M0REMAP] = val & 0x000007ff; |
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347 break; |
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348 case GT_PCI1M1LD: |
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349 s->regs[GT_PCI1M1LD] = val & 0x00007fff; |
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350 s->regs[GT_PCI1M1REMAP] = val & 0x000007ff; |
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351 break; |
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352 case GT_PCI0IOHD: |
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353 s->regs[saddr] = val & 0x0000007f; |
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354 gt64120_pci_mapping(s); |
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355 break; |
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356 case GT_PCI0M0HD: |
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357 case GT_PCI0M1HD: |
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358 case GT_PCI1IOHD: |
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359 case GT_PCI1M0HD: |
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360 case GT_PCI1M1HD: |
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361 s->regs[saddr] = val & 0x0000007f; |
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362 break; |
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363 case GT_ISD: |
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364 s->regs[saddr] = val & 0x00007fff; |
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365 gt64120_isd_mapping(s); |
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366 break; |
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367 |
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368 case GT_PCI0IOREMAP: |
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369 case GT_PCI0M0REMAP: |
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370 case GT_PCI0M1REMAP: |
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371 case GT_PCI1IOREMAP: |
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372 case GT_PCI1M0REMAP: |
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373 case GT_PCI1M1REMAP: |
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374 s->regs[saddr] = val & 0x000007ff; |
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375 break; |
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376 |
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377 /* CPU Error Report */ |
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378 case GT_CPUERR_ADDRLO: |
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379 case GT_CPUERR_ADDRHI: |
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380 case GT_CPUERR_DATALO: |
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381 case GT_CPUERR_DATAHI: |
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382 case GT_CPUERR_PARITY: |
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383 /* Read-only registers, do nothing */ |
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384 break; |
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385 |
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386 /* CPU Sync Barrier */ |
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387 case GT_PCI0SYNC: |
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388 case GT_PCI1SYNC: |
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389 /* Read-only registers, do nothing */ |
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390 break; |
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391 |
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392 /* SDRAM and Device Address Decode */ |
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393 case GT_SCS0LD: |
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394 case GT_SCS0HD: |
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395 case GT_SCS1LD: |
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396 case GT_SCS1HD: |
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397 case GT_SCS2LD: |
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398 case GT_SCS2HD: |
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399 case GT_SCS3LD: |
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400 case GT_SCS3HD: |
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401 case GT_CS0LD: |
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402 case GT_CS0HD: |
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403 case GT_CS1LD: |
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404 case GT_CS1HD: |
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405 case GT_CS2LD: |
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406 case GT_CS2HD: |
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407 case GT_CS3LD: |
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408 case GT_CS3HD: |
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409 case GT_BOOTLD: |
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410 case GT_BOOTHD: |
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411 case GT_ADERR: |
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412 /* SDRAM Configuration */ |
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413 case GT_SDRAM_CFG: |
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414 case GT_SDRAM_OPMODE: |
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415 case GT_SDRAM_BM: |
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416 case GT_SDRAM_ADDRDECODE: |
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417 /* Accept and ignore SDRAM interleave configuration */ |
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418 s->regs[saddr] = val; |
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419 break; |
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420 |
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421 /* Device Parameters */ |
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422 case GT_DEV_B0: |
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423 case GT_DEV_B1: |
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424 case GT_DEV_B2: |
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425 case GT_DEV_B3: |
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426 case GT_DEV_BOOT: |
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427 /* Not implemented */ |
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428 dprintf ("Unimplemented device register offset 0x%x\n", saddr << 2); |
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429 break; |
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430 |
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431 /* ECC */ |
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432 case GT_ECC_ERRDATALO: |
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433 case GT_ECC_ERRDATAHI: |
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434 case GT_ECC_MEM: |
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435 case GT_ECC_CALC: |
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436 case GT_ECC_ERRADDR: |
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437 /* Read-only registers, do nothing */ |
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438 break; |
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439 |
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440 /* DMA Record */ |
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441 case GT_DMA0_CNT: |
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442 case GT_DMA1_CNT: |
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443 case GT_DMA2_CNT: |
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444 case GT_DMA3_CNT: |
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445 case GT_DMA0_SA: |
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446 case GT_DMA1_SA: |
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447 case GT_DMA2_SA: |
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448 case GT_DMA3_SA: |
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449 case GT_DMA0_DA: |
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450 case GT_DMA1_DA: |
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451 case GT_DMA2_DA: |
|
452 case GT_DMA3_DA: |
|
453 case GT_DMA0_NEXT: |
|
454 case GT_DMA1_NEXT: |
|
455 case GT_DMA2_NEXT: |
|
456 case GT_DMA3_NEXT: |
|
457 case GT_DMA0_CUR: |
|
458 case GT_DMA1_CUR: |
|
459 case GT_DMA2_CUR: |
|
460 case GT_DMA3_CUR: |
|
461 /* Not implemented */ |
|
462 dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2); |
|
463 break; |
|
464 |
|
465 /* DMA Channel Control */ |
|
466 case GT_DMA0_CTRL: |
|
467 case GT_DMA1_CTRL: |
|
468 case GT_DMA2_CTRL: |
|
469 case GT_DMA3_CTRL: |
|
470 /* Not implemented */ |
|
471 dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2); |
|
472 break; |
|
473 |
|
474 /* DMA Arbiter */ |
|
475 case GT_DMA_ARB: |
|
476 /* Not implemented */ |
|
477 dprintf ("Unimplemented DMA register offset 0x%x\n", saddr << 2); |
|
478 break; |
|
479 |
|
480 /* Timer/Counter */ |
|
481 case GT_TC0: |
|
482 case GT_TC1: |
|
483 case GT_TC2: |
|
484 case GT_TC3: |
|
485 case GT_TC_CONTROL: |
|
486 /* Not implemented */ |
|
487 dprintf ("Unimplemented timer register offset 0x%x\n", saddr << 2); |
|
488 break; |
|
489 |
|
490 /* PCI Internal */ |
|
491 case GT_PCI0_CMD: |
|
492 case GT_PCI1_CMD: |
|
493 s->regs[saddr] = val & 0x0401fc0f; |
|
494 break; |
|
495 case GT_PCI0_TOR: |
|
496 case GT_PCI0_BS_SCS10: |
|
497 case GT_PCI0_BS_SCS32: |
|
498 case GT_PCI0_BS_CS20: |
|
499 case GT_PCI0_BS_CS3BT: |
|
500 case GT_PCI1_IACK: |
|
501 case GT_PCI0_IACK: |
|
502 case GT_PCI0_BARE: |
|
503 case GT_PCI0_PREFMBR: |
|
504 case GT_PCI0_SCS10_BAR: |
|
505 case GT_PCI0_SCS32_BAR: |
|
506 case GT_PCI0_CS20_BAR: |
|
507 case GT_PCI0_CS3BT_BAR: |
|
508 case GT_PCI0_SSCS10_BAR: |
|
509 case GT_PCI0_SSCS32_BAR: |
|
510 case GT_PCI0_SCS3BT_BAR: |
|
511 case GT_PCI1_TOR: |
|
512 case GT_PCI1_BS_SCS10: |
|
513 case GT_PCI1_BS_SCS32: |
|
514 case GT_PCI1_BS_CS20: |
|
515 case GT_PCI1_BS_CS3BT: |
|
516 case GT_PCI1_BARE: |
|
517 case GT_PCI1_PREFMBR: |
|
518 case GT_PCI1_SCS10_BAR: |
|
519 case GT_PCI1_SCS32_BAR: |
|
520 case GT_PCI1_CS20_BAR: |
|
521 case GT_PCI1_CS3BT_BAR: |
|
522 case GT_PCI1_SSCS10_BAR: |
|
523 case GT_PCI1_SSCS32_BAR: |
|
524 case GT_PCI1_SCS3BT_BAR: |
|
525 case GT_PCI1_CFGADDR: |
|
526 case GT_PCI1_CFGDATA: |
|
527 /* not implemented */ |
|
528 break; |
|
529 case GT_PCI0_CFGADDR: |
|
530 s->pci->config_reg = val & 0x80fffffc; |
|
531 break; |
|
532 case GT_PCI0_CFGDATA: |
|
533 if (!(s->regs[GT_PCI0_CMD] & 1) && (s->pci->config_reg & 0x00fff800)) |
|
534 val = bswap32(val); |
|
535 if (s->pci->config_reg & (1u << 31)) |
|
536 pci_data_write(s->pci->bus, s->pci->config_reg, val, 4); |
|
537 break; |
|
538 |
|
539 /* Interrupts */ |
|
540 case GT_INTRCAUSE: |
|
541 /* not really implemented */ |
|
542 s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe)); |
|
543 s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe); |
|
544 dprintf("INTRCAUSE %x\n", val); |
|
545 break; |
|
546 case GT_INTRMASK: |
|
547 s->regs[saddr] = val & 0x3c3ffffe; |
|
548 dprintf("INTRMASK %x\n", val); |
|
549 break; |
|
550 case GT_PCI0_ICMASK: |
|
551 s->regs[saddr] = val & 0x03fffffe; |
|
552 dprintf("ICMASK %x\n", val); |
|
553 break; |
|
554 case GT_PCI0_SERR0MASK: |
|
555 s->regs[saddr] = val & 0x0000003f; |
|
556 dprintf("SERR0MASK %x\n", val); |
|
557 break; |
|
558 |
|
559 /* Reserved when only PCI_0 is configured. */ |
|
560 case GT_HINTRCAUSE: |
|
561 case GT_CPU_INTSEL: |
|
562 case GT_PCI0_INTSEL: |
|
563 case GT_HINTRMASK: |
|
564 case GT_PCI0_HICMASK: |
|
565 case GT_PCI1_SERR1MASK: |
|
566 /* not implemented */ |
|
567 break; |
|
568 |
|
569 /* SDRAM Parameters */ |
|
570 case GT_SDRAM_B0: |
|
571 case GT_SDRAM_B1: |
|
572 case GT_SDRAM_B2: |
|
573 case GT_SDRAM_B3: |
|
574 /* We don't simulate electrical parameters of the SDRAM. |
|
575 Accept, but ignore the values. */ |
|
576 s->regs[saddr] = val; |
|
577 break; |
|
578 |
|
579 default: |
|
580 dprintf ("Bad register offset 0x%x\n", (int)addr); |
|
581 break; |
|
582 } |
|
583 } |
|
584 |
|
585 static uint32_t gt64120_readl (void *opaque, |
|
586 target_phys_addr_t addr) |
|
587 { |
|
588 GT64120State *s = opaque; |
|
589 uint32_t val; |
|
590 uint32_t saddr; |
|
591 |
|
592 saddr = (addr & 0xfff) >> 2; |
|
593 switch (saddr) { |
|
594 |
|
595 /* CPU Configuration */ |
|
596 case GT_MULTI: |
|
597 /* Only one GT64xxx is present on the CPU bus, return |
|
598 the initial value */ |
|
599 val = s->regs[saddr]; |
|
600 break; |
|
601 |
|
602 /* CPU Error Report */ |
|
603 case GT_CPUERR_ADDRLO: |
|
604 case GT_CPUERR_ADDRHI: |
|
605 case GT_CPUERR_DATALO: |
|
606 case GT_CPUERR_DATAHI: |
|
607 case GT_CPUERR_PARITY: |
|
608 /* Emulated memory has no error, always return the initial |
|
609 values */ |
|
610 val = s->regs[saddr]; |
|
611 break; |
|
612 |
|
613 /* CPU Sync Barrier */ |
|
614 case GT_PCI0SYNC: |
|
615 case GT_PCI1SYNC: |
|
616 /* Reading those register should empty all FIFO on the PCI |
|
617 bus, which are not emulated. The return value should be |
|
618 a random value that should be ignored. */ |
|
619 val = 0xc000ffee; |
|
620 break; |
|
621 |
|
622 /* ECC */ |
|
623 case GT_ECC_ERRDATALO: |
|
624 case GT_ECC_ERRDATAHI: |
|
625 case GT_ECC_MEM: |
|
626 case GT_ECC_CALC: |
|
627 case GT_ECC_ERRADDR: |
|
628 /* Emulated memory has no error, always return the initial |
|
629 values */ |
|
630 val = s->regs[saddr]; |
|
631 break; |
|
632 |
|
633 case GT_CPU: |
|
634 case GT_SCS10LD: |
|
635 case GT_SCS10HD: |
|
636 case GT_SCS32LD: |
|
637 case GT_SCS32HD: |
|
638 case GT_CS20LD: |
|
639 case GT_CS20HD: |
|
640 case GT_CS3BOOTLD: |
|
641 case GT_CS3BOOTHD: |
|
642 case GT_SCS10AR: |
|
643 case GT_SCS32AR: |
|
644 case GT_CS20R: |
|
645 case GT_CS3BOOTR: |
|
646 case GT_PCI0IOLD: |
|
647 case GT_PCI0M0LD: |
|
648 case GT_PCI0M1LD: |
|
649 case GT_PCI1IOLD: |
|
650 case GT_PCI1M0LD: |
|
651 case GT_PCI1M1LD: |
|
652 case GT_PCI0IOHD: |
|
653 case GT_PCI0M0HD: |
|
654 case GT_PCI0M1HD: |
|
655 case GT_PCI1IOHD: |
|
656 case GT_PCI1M0HD: |
|
657 case GT_PCI1M1HD: |
|
658 case GT_PCI0IOREMAP: |
|
659 case GT_PCI0M0REMAP: |
|
660 case GT_PCI0M1REMAP: |
|
661 case GT_PCI1IOREMAP: |
|
662 case GT_PCI1M0REMAP: |
|
663 case GT_PCI1M1REMAP: |
|
664 case GT_ISD: |
|
665 val = s->regs[saddr]; |
|
666 break; |
|
667 case GT_PCI0_IACK: |
|
668 /* Read the IRQ number */ |
|
669 val = pic_read_irq(isa_pic); |
|
670 break; |
|
671 |
|
672 /* SDRAM and Device Address Decode */ |
|
673 case GT_SCS0LD: |
|
674 case GT_SCS0HD: |
|
675 case GT_SCS1LD: |
|
676 case GT_SCS1HD: |
|
677 case GT_SCS2LD: |
|
678 case GT_SCS2HD: |
|
679 case GT_SCS3LD: |
|
680 case GT_SCS3HD: |
|
681 case GT_CS0LD: |
|
682 case GT_CS0HD: |
|
683 case GT_CS1LD: |
|
684 case GT_CS1HD: |
|
685 case GT_CS2LD: |
|
686 case GT_CS2HD: |
|
687 case GT_CS3LD: |
|
688 case GT_CS3HD: |
|
689 case GT_BOOTLD: |
|
690 case GT_BOOTHD: |
|
691 case GT_ADERR: |
|
692 val = s->regs[saddr]; |
|
693 break; |
|
694 |
|
695 /* SDRAM Configuration */ |
|
696 case GT_SDRAM_CFG: |
|
697 case GT_SDRAM_OPMODE: |
|
698 case GT_SDRAM_BM: |
|
699 case GT_SDRAM_ADDRDECODE: |
|
700 val = s->regs[saddr]; |
|
701 break; |
|
702 |
|
703 /* SDRAM Parameters */ |
|
704 case GT_SDRAM_B0: |
|
705 case GT_SDRAM_B1: |
|
706 case GT_SDRAM_B2: |
|
707 case GT_SDRAM_B3: |
|
708 /* We don't simulate electrical parameters of the SDRAM. |
|
709 Just return the last written value. */ |
|
710 val = s->regs[saddr]; |
|
711 break; |
|
712 |
|
713 /* Device Parameters */ |
|
714 case GT_DEV_B0: |
|
715 case GT_DEV_B1: |
|
716 case GT_DEV_B2: |
|
717 case GT_DEV_B3: |
|
718 case GT_DEV_BOOT: |
|
719 val = s->regs[saddr]; |
|
720 break; |
|
721 |
|
722 /* DMA Record */ |
|
723 case GT_DMA0_CNT: |
|
724 case GT_DMA1_CNT: |
|
725 case GT_DMA2_CNT: |
|
726 case GT_DMA3_CNT: |
|
727 case GT_DMA0_SA: |
|
728 case GT_DMA1_SA: |
|
729 case GT_DMA2_SA: |
|
730 case GT_DMA3_SA: |
|
731 case GT_DMA0_DA: |
|
732 case GT_DMA1_DA: |
|
733 case GT_DMA2_DA: |
|
734 case GT_DMA3_DA: |
|
735 case GT_DMA0_NEXT: |
|
736 case GT_DMA1_NEXT: |
|
737 case GT_DMA2_NEXT: |
|
738 case GT_DMA3_NEXT: |
|
739 case GT_DMA0_CUR: |
|
740 case GT_DMA1_CUR: |
|
741 case GT_DMA2_CUR: |
|
742 case GT_DMA3_CUR: |
|
743 val = s->regs[saddr]; |
|
744 break; |
|
745 |
|
746 /* DMA Channel Control */ |
|
747 case GT_DMA0_CTRL: |
|
748 case GT_DMA1_CTRL: |
|
749 case GT_DMA2_CTRL: |
|
750 case GT_DMA3_CTRL: |
|
751 val = s->regs[saddr]; |
|
752 break; |
|
753 |
|
754 /* DMA Arbiter */ |
|
755 case GT_DMA_ARB: |
|
756 val = s->regs[saddr]; |
|
757 break; |
|
758 |
|
759 /* Timer/Counter */ |
|
760 case GT_TC0: |
|
761 case GT_TC1: |
|
762 case GT_TC2: |
|
763 case GT_TC3: |
|
764 case GT_TC_CONTROL: |
|
765 val = s->regs[saddr]; |
|
766 break; |
|
767 |
|
768 /* PCI Internal */ |
|
769 case GT_PCI0_CFGADDR: |
|
770 val = s->pci->config_reg; |
|
771 break; |
|
772 case GT_PCI0_CFGDATA: |
|
773 if (!(s->pci->config_reg & (1 << 31))) |
|
774 val = 0xffffffff; |
|
775 else |
|
776 val = pci_data_read(s->pci->bus, s->pci->config_reg, 4); |
|
777 if (!(s->regs[GT_PCI0_CMD] & 1) && (s->pci->config_reg & 0x00fff800)) |
|
778 val = bswap32(val); |
|
779 break; |
|
780 |
|
781 case GT_PCI0_CMD: |
|
782 case GT_PCI0_TOR: |
|
783 case GT_PCI0_BS_SCS10: |
|
784 case GT_PCI0_BS_SCS32: |
|
785 case GT_PCI0_BS_CS20: |
|
786 case GT_PCI0_BS_CS3BT: |
|
787 case GT_PCI1_IACK: |
|
788 case GT_PCI0_BARE: |
|
789 case GT_PCI0_PREFMBR: |
|
790 case GT_PCI0_SCS10_BAR: |
|
791 case GT_PCI0_SCS32_BAR: |
|
792 case GT_PCI0_CS20_BAR: |
|
793 case GT_PCI0_CS3BT_BAR: |
|
794 case GT_PCI0_SSCS10_BAR: |
|
795 case GT_PCI0_SSCS32_BAR: |
|
796 case GT_PCI0_SCS3BT_BAR: |
|
797 case GT_PCI1_CMD: |
|
798 case GT_PCI1_TOR: |
|
799 case GT_PCI1_BS_SCS10: |
|
800 case GT_PCI1_BS_SCS32: |
|
801 case GT_PCI1_BS_CS20: |
|
802 case GT_PCI1_BS_CS3BT: |
|
803 case GT_PCI1_BARE: |
|
804 case GT_PCI1_PREFMBR: |
|
805 case GT_PCI1_SCS10_BAR: |
|
806 case GT_PCI1_SCS32_BAR: |
|
807 case GT_PCI1_CS20_BAR: |
|
808 case GT_PCI1_CS3BT_BAR: |
|
809 case GT_PCI1_SSCS10_BAR: |
|
810 case GT_PCI1_SSCS32_BAR: |
|
811 case GT_PCI1_SCS3BT_BAR: |
|
812 case GT_PCI1_CFGADDR: |
|
813 case GT_PCI1_CFGDATA: |
|
814 val = s->regs[saddr]; |
|
815 break; |
|
816 |
|
817 /* Interrupts */ |
|
818 case GT_INTRCAUSE: |
|
819 val = s->regs[saddr]; |
|
820 dprintf("INTRCAUSE %x\n", val); |
|
821 break; |
|
822 case GT_INTRMASK: |
|
823 val = s->regs[saddr]; |
|
824 dprintf("INTRMASK %x\n", val); |
|
825 break; |
|
826 case GT_PCI0_ICMASK: |
|
827 val = s->regs[saddr]; |
|
828 dprintf("ICMASK %x\n", val); |
|
829 break; |
|
830 case GT_PCI0_SERR0MASK: |
|
831 val = s->regs[saddr]; |
|
832 dprintf("SERR0MASK %x\n", val); |
|
833 break; |
|
834 |
|
835 /* Reserved when only PCI_0 is configured. */ |
|
836 case GT_HINTRCAUSE: |
|
837 case GT_CPU_INTSEL: |
|
838 case GT_PCI0_INTSEL: |
|
839 case GT_HINTRMASK: |
|
840 case GT_PCI0_HICMASK: |
|
841 case GT_PCI1_SERR1MASK: |
|
842 val = s->regs[saddr]; |
|
843 break; |
|
844 |
|
845 default: |
|
846 val = s->regs[saddr]; |
|
847 dprintf ("Bad register offset 0x%x\n", (int)addr); |
|
848 break; |
|
849 } |
|
850 |
|
851 if (!(s->regs[GT_CPU] & 0x00001000)) |
|
852 val = bswap32(val); |
|
853 |
|
854 return val; |
|
855 } |
|
856 |
|
857 static CPUWriteMemoryFunc *gt64120_write[] = { |
|
858 >64120_writel, |
|
859 >64120_writel, |
|
860 >64120_writel, |
|
861 }; |
|
862 |
|
863 static CPUReadMemoryFunc *gt64120_read[] = { |
|
864 >64120_readl, |
|
865 >64120_readl, |
|
866 >64120_readl, |
|
867 }; |
|
868 |
|
869 static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num) |
|
870 { |
|
871 int slot; |
|
872 |
|
873 slot = (pci_dev->devfn >> 3); |
|
874 |
|
875 switch (slot) { |
|
876 /* PIIX4 USB */ |
|
877 case 10: |
|
878 return 3; |
|
879 /* AMD 79C973 Ethernet */ |
|
880 case 11: |
|
881 return 1; |
|
882 /* Crystal 4281 Sound */ |
|
883 case 12: |
|
884 return 2; |
|
885 /* PCI slot 1 to 4 */ |
|
886 case 18 ... 21: |
|
887 return ((slot - 18) + irq_num) & 0x03; |
|
888 /* Unknown device, don't do any translation */ |
|
889 default: |
|
890 return irq_num; |
|
891 } |
|
892 } |
|
893 |
|
894 static int pci_irq_levels[4]; |
|
895 |
|
896 static void pci_gt64120_set_irq(qemu_irq *pic, int irq_num, int level) |
|
897 { |
|
898 int i, pic_irq, pic_level; |
|
899 |
|
900 pci_irq_levels[irq_num] = level; |
|
901 |
|
902 /* now we change the pic irq level according to the piix irq mappings */ |
|
903 /* XXX: optimize */ |
|
904 pic_irq = piix4_dev->config[0x60 + irq_num]; |
|
905 if (pic_irq < 16) { |
|
906 /* The pic level is the logical OR of all the PCI irqs mapped |
|
907 to it */ |
|
908 pic_level = 0; |
|
909 for (i = 0; i < 4; i++) { |
|
910 if (pic_irq == piix4_dev->config[0x60 + i]) |
|
911 pic_level |= pci_irq_levels[i]; |
|
912 } |
|
913 qemu_set_irq(pic[pic_irq], pic_level); |
|
914 } |
|
915 } |
|
916 |
|
917 |
|
918 static void gt64120_reset(void *opaque) |
|
919 { |
|
920 GT64120State *s = opaque; |
|
921 |
|
922 /* FIXME: Malta specific hw assumptions ahead */ |
|
923 |
|
924 /* CPU Configuration */ |
|
925 #ifdef TARGET_WORDS_BIGENDIAN |
|
926 s->regs[GT_CPU] = 0x00000000; |
|
927 #else |
|
928 s->regs[GT_CPU] = 0x00001000; |
|
929 #endif |
|
930 s->regs[GT_MULTI] = 0x00000003; |
|
931 |
|
932 /* CPU Address decode */ |
|
933 s->regs[GT_SCS10LD] = 0x00000000; |
|
934 s->regs[GT_SCS10HD] = 0x00000007; |
|
935 s->regs[GT_SCS32LD] = 0x00000008; |
|
936 s->regs[GT_SCS32HD] = 0x0000000f; |
|
937 s->regs[GT_CS20LD] = 0x000000e0; |
|
938 s->regs[GT_CS20HD] = 0x00000070; |
|
939 s->regs[GT_CS3BOOTLD] = 0x000000f8; |
|
940 s->regs[GT_CS3BOOTHD] = 0x0000007f; |
|
941 |
|
942 s->regs[GT_PCI0IOLD] = 0x00000080; |
|
943 s->regs[GT_PCI0IOHD] = 0x0000000f; |
|
944 s->regs[GT_PCI0M0LD] = 0x00000090; |
|
945 s->regs[GT_PCI0M0HD] = 0x0000001f; |
|
946 s->regs[GT_ISD] = 0x000000a0; |
|
947 s->regs[GT_PCI0M1LD] = 0x00000790; |
|
948 s->regs[GT_PCI0M1HD] = 0x0000001f; |
|
949 s->regs[GT_PCI1IOLD] = 0x00000100; |
|
950 s->regs[GT_PCI1IOHD] = 0x0000000f; |
|
951 s->regs[GT_PCI1M0LD] = 0x00000110; |
|
952 s->regs[GT_PCI1M0HD] = 0x0000001f; |
|
953 s->regs[GT_PCI1M1LD] = 0x00000120; |
|
954 s->regs[GT_PCI1M1HD] = 0x0000002f; |
|
955 |
|
956 s->regs[GT_SCS10AR] = 0x00000000; |
|
957 s->regs[GT_SCS32AR] = 0x00000008; |
|
958 s->regs[GT_CS20R] = 0x000000e0; |
|
959 s->regs[GT_CS3BOOTR] = 0x000000f8; |
|
960 |
|
961 s->regs[GT_PCI0IOREMAP] = 0x00000080; |
|
962 s->regs[GT_PCI0M0REMAP] = 0x00000090; |
|
963 s->regs[GT_PCI0M1REMAP] = 0x00000790; |
|
964 s->regs[GT_PCI1IOREMAP] = 0x00000100; |
|
965 s->regs[GT_PCI1M0REMAP] = 0x00000110; |
|
966 s->regs[GT_PCI1M1REMAP] = 0x00000120; |
|
967 |
|
968 /* CPU Error Report */ |
|
969 s->regs[GT_CPUERR_ADDRLO] = 0x00000000; |
|
970 s->regs[GT_CPUERR_ADDRHI] = 0x00000000; |
|
971 s->regs[GT_CPUERR_DATALO] = 0xffffffff; |
|
972 s->regs[GT_CPUERR_DATAHI] = 0xffffffff; |
|
973 s->regs[GT_CPUERR_PARITY] = 0x000000ff; |
|
974 |
|
975 /* CPU Sync Barrier */ |
|
976 s->regs[GT_PCI0SYNC] = 0x00000000; |
|
977 s->regs[GT_PCI1SYNC] = 0x00000000; |
|
978 |
|
979 /* SDRAM and Device Address Decode */ |
|
980 s->regs[GT_SCS0LD] = 0x00000000; |
|
981 s->regs[GT_SCS0HD] = 0x00000007; |
|
982 s->regs[GT_SCS1LD] = 0x00000008; |
|
983 s->regs[GT_SCS1HD] = 0x0000000f; |
|
984 s->regs[GT_SCS2LD] = 0x00000010; |
|
985 s->regs[GT_SCS2HD] = 0x00000017; |
|
986 s->regs[GT_SCS3LD] = 0x00000018; |
|
987 s->regs[GT_SCS3HD] = 0x0000001f; |
|
988 s->regs[GT_CS0LD] = 0x000000c0; |
|
989 s->regs[GT_CS0HD] = 0x000000c7; |
|
990 s->regs[GT_CS1LD] = 0x000000c8; |
|
991 s->regs[GT_CS1HD] = 0x000000cf; |
|
992 s->regs[GT_CS2LD] = 0x000000d0; |
|
993 s->regs[GT_CS2HD] = 0x000000df; |
|
994 s->regs[GT_CS3LD] = 0x000000f0; |
|
995 s->regs[GT_CS3HD] = 0x000000fb; |
|
996 s->regs[GT_BOOTLD] = 0x000000fc; |
|
997 s->regs[GT_BOOTHD] = 0x000000ff; |
|
998 s->regs[GT_ADERR] = 0xffffffff; |
|
999 |
|
1000 /* SDRAM Configuration */ |
|
1001 s->regs[GT_SDRAM_CFG] = 0x00000200; |
|
1002 s->regs[GT_SDRAM_OPMODE] = 0x00000000; |
|
1003 s->regs[GT_SDRAM_BM] = 0x00000007; |
|
1004 s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002; |
|
1005 |
|
1006 /* SDRAM Parameters */ |
|
1007 s->regs[GT_SDRAM_B0] = 0x00000005; |
|
1008 s->regs[GT_SDRAM_B1] = 0x00000005; |
|
1009 s->regs[GT_SDRAM_B2] = 0x00000005; |
|
1010 s->regs[GT_SDRAM_B3] = 0x00000005; |
|
1011 |
|
1012 /* ECC */ |
|
1013 s->regs[GT_ECC_ERRDATALO] = 0x00000000; |
|
1014 s->regs[GT_ECC_ERRDATAHI] = 0x00000000; |
|
1015 s->regs[GT_ECC_MEM] = 0x00000000; |
|
1016 s->regs[GT_ECC_CALC] = 0x00000000; |
|
1017 s->regs[GT_ECC_ERRADDR] = 0x00000000; |
|
1018 |
|
1019 /* Device Parameters */ |
|
1020 s->regs[GT_DEV_B0] = 0x386fffff; |
|
1021 s->regs[GT_DEV_B1] = 0x386fffff; |
|
1022 s->regs[GT_DEV_B2] = 0x386fffff; |
|
1023 s->regs[GT_DEV_B3] = 0x386fffff; |
|
1024 s->regs[GT_DEV_BOOT] = 0x146fffff; |
|
1025 |
|
1026 /* DMA registers are all zeroed at reset */ |
|
1027 |
|
1028 /* Timer/Counter */ |
|
1029 s->regs[GT_TC0] = 0xffffffff; |
|
1030 s->regs[GT_TC1] = 0x00ffffff; |
|
1031 s->regs[GT_TC2] = 0x00ffffff; |
|
1032 s->regs[GT_TC3] = 0x00ffffff; |
|
1033 s->regs[GT_TC_CONTROL] = 0x00000000; |
|
1034 |
|
1035 /* PCI Internal */ |
|
1036 #ifdef TARGET_WORDS_BIGENDIAN |
|
1037 s->regs[GT_PCI0_CMD] = 0x00000000; |
|
1038 #else |
|
1039 s->regs[GT_PCI0_CMD] = 0x00010001; |
|
1040 #endif |
|
1041 s->regs[GT_PCI0_TOR] = 0x0000070f; |
|
1042 s->regs[GT_PCI0_BS_SCS10] = 0x00fff000; |
|
1043 s->regs[GT_PCI0_BS_SCS32] = 0x00fff000; |
|
1044 s->regs[GT_PCI0_BS_CS20] = 0x01fff000; |
|
1045 s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000; |
|
1046 s->regs[GT_PCI1_IACK] = 0x00000000; |
|
1047 s->regs[GT_PCI0_IACK] = 0x00000000; |
|
1048 s->regs[GT_PCI0_BARE] = 0x0000000f; |
|
1049 s->regs[GT_PCI0_PREFMBR] = 0x00000040; |
|
1050 s->regs[GT_PCI0_SCS10_BAR] = 0x00000000; |
|
1051 s->regs[GT_PCI0_SCS32_BAR] = 0x01000000; |
|
1052 s->regs[GT_PCI0_CS20_BAR] = 0x1c000000; |
|
1053 s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000; |
|
1054 s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000; |
|
1055 s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000; |
|
1056 s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000; |
|
1057 #ifdef TARGET_WORDS_BIGENDIAN |
|
1058 s->regs[GT_PCI1_CMD] = 0x00000000; |
|
1059 #else |
|
1060 s->regs[GT_PCI1_CMD] = 0x00010001; |
|
1061 #endif |
|
1062 s->regs[GT_PCI1_TOR] = 0x0000070f; |
|
1063 s->regs[GT_PCI1_BS_SCS10] = 0x00fff000; |
|
1064 s->regs[GT_PCI1_BS_SCS32] = 0x00fff000; |
|
1065 s->regs[GT_PCI1_BS_CS20] = 0x01fff000; |
|
1066 s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000; |
|
1067 s->regs[GT_PCI1_BARE] = 0x0000000f; |
|
1068 s->regs[GT_PCI1_PREFMBR] = 0x00000040; |
|
1069 s->regs[GT_PCI1_SCS10_BAR] = 0x00000000; |
|
1070 s->regs[GT_PCI1_SCS32_BAR] = 0x01000000; |
|
1071 s->regs[GT_PCI1_CS20_BAR] = 0x1c000000; |
|
1072 s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000; |
|
1073 s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000; |
|
1074 s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000; |
|
1075 s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000; |
|
1076 s->regs[GT_PCI1_CFGADDR] = 0x00000000; |
|
1077 s->regs[GT_PCI1_CFGDATA] = 0x00000000; |
|
1078 s->regs[GT_PCI0_CFGADDR] = 0x00000000; |
|
1079 |
|
1080 /* Interrupt registers are all zeroed at reset */ |
|
1081 |
|
1082 gt64120_isd_mapping(s); |
|
1083 gt64120_pci_mapping(s); |
|
1084 } |
|
1085 |
|
1086 static uint32_t gt64120_read_config(PCIDevice *d, uint32_t address, int len) |
|
1087 { |
|
1088 return pci_default_read_config(d, address, len); |
|
1089 } |
|
1090 |
|
1091 static void gt64120_write_config(PCIDevice *d, uint32_t address, uint32_t val, |
|
1092 int len) |
|
1093 { |
|
1094 pci_default_write_config(d, address, val, len); |
|
1095 } |
|
1096 |
|
1097 static void gt64120_save(QEMUFile* f, void *opaque) |
|
1098 { |
|
1099 PCIDevice *d = opaque; |
|
1100 pci_device_save(d, f); |
|
1101 } |
|
1102 |
|
1103 static int gt64120_load(QEMUFile* f, void *opaque, int version_id) |
|
1104 { |
|
1105 PCIDevice *d = opaque; |
|
1106 int ret; |
|
1107 |
|
1108 if (version_id != 1) |
|
1109 return -EINVAL; |
|
1110 ret = pci_device_load(d, f); |
|
1111 if (ret < 0) |
|
1112 return ret; |
|
1113 return 0; |
|
1114 } |
|
1115 |
|
1116 PCIBus *pci_gt64120_init(qemu_irq *pic) |
|
1117 { |
|
1118 GT64120State *s; |
|
1119 PCIDevice *d; |
|
1120 |
|
1121 (void)&pci_host_data_writeb; /* avoid warning */ |
|
1122 (void)&pci_host_data_writew; /* avoid warning */ |
|
1123 (void)&pci_host_data_writel; /* avoid warning */ |
|
1124 (void)&pci_host_data_readb; /* avoid warning */ |
|
1125 (void)&pci_host_data_readw; /* avoid warning */ |
|
1126 (void)&pci_host_data_readl; /* avoid warning */ |
|
1127 |
|
1128 s = qemu_mallocz(sizeof(GT64120State)); |
|
1129 s->pci = qemu_mallocz(sizeof(GT64120PCIState)); |
|
1130 |
|
1131 s->pci->bus = pci_register_bus(pci_gt64120_set_irq, pci_gt64120_map_irq, |
|
1132 pic, 144, 4); |
|
1133 s->ISD_handle = cpu_register_io_memory(0, gt64120_read, gt64120_write, s); |
|
1134 d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice), |
|
1135 0, gt64120_read_config, gt64120_write_config); |
|
1136 |
|
1137 /* FIXME: Malta specific hw assumptions ahead */ |
|
1138 |
|
1139 d->config[0x00] = 0xab; /* vendor_id */ |
|
1140 d->config[0x01] = 0x11; |
|
1141 d->config[0x02] = 0x20; /* device_id */ |
|
1142 d->config[0x03] = 0x46; |
|
1143 |
|
1144 d->config[0x04] = 0x00; |
|
1145 d->config[0x05] = 0x00; |
|
1146 d->config[0x06] = 0x80; |
|
1147 d->config[0x07] = 0x02; |
|
1148 |
|
1149 d->config[0x08] = 0x10; |
|
1150 d->config[0x09] = 0x00; |
|
1151 d->config[0x0A] = 0x00; |
|
1152 d->config[0x0B] = 0x06; |
|
1153 |
|
1154 d->config[0x10] = 0x08; |
|
1155 d->config[0x14] = 0x08; |
|
1156 d->config[0x17] = 0x01; |
|
1157 d->config[0x1B] = 0x1c; |
|
1158 d->config[0x1F] = 0x1f; |
|
1159 d->config[0x23] = 0x14; |
|
1160 d->config[0x24] = 0x01; |
|
1161 d->config[0x27] = 0x14; |
|
1162 d->config[0x3D] = 0x01; |
|
1163 |
|
1164 gt64120_reset(s); |
|
1165 |
|
1166 register_savevm("GT64120 PCI Bus", 0, 1, gt64120_save, gt64120_load, d); |
|
1167 |
|
1168 return s->pci->bus; |
|
1169 } |