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1 /* |
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2 * QEMU Emulated HPET support |
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3 * |
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4 * Copyright IBM, Corp. 2008 |
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5 * |
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6 * Authors: |
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7 * Beth Kon <bkon@us.ibm.com> |
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8 * |
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9 * This work is licensed under the terms of the GNU GPL, version 2. See |
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10 * the COPYING file in the top-level directory. |
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11 * |
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12 */ |
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13 #ifndef QEMU_HPET_EMUL_H |
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14 #define QEMU_HPET_EMUL_H |
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15 |
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16 #define HPET_BASE 0xfed00000 |
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17 #define HPET_CLK_PERIOD 10000000ULL /* 10000000 femtoseconds == 10ns*/ |
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18 |
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19 #define FS_PER_NS 1000000 |
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20 #define HPET_NUM_TIMERS 3 |
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21 #define HPET_TIMER_TYPE_LEVEL 1 |
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22 #define HPET_TIMER_TYPE_EDGE 0 |
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23 #define HPET_TIMER_DELIVERY_APIC 0 |
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24 #define HPET_TIMER_DELIVERY_FSB 1 |
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25 #define HPET_TIMER_CAP_FSB_INT_DEL (1 << 15) |
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26 #define HPET_TIMER_CAP_PER_INT (1 << 4) |
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27 |
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28 #define HPET_CFG_ENABLE 0x001 |
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29 #define HPET_CFG_LEGACY 0x002 |
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30 |
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31 #define HPET_ID 0x000 |
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32 #define HPET_PERIOD 0x004 |
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33 #define HPET_CFG 0x010 |
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34 #define HPET_STATUS 0x020 |
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35 #define HPET_COUNTER 0x0f0 |
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36 #define HPET_TN_CFG 0x000 |
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37 #define HPET_TN_CMP 0x008 |
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38 #define HPET_TN_ROUTE 0x010 |
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39 |
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40 |
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41 #define HPET_TN_ENABLE 0x004 |
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42 #define HPET_TN_PERIODIC 0x008 |
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43 #define HPET_TN_PERIODIC_CAP 0x010 |
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44 #define HPET_TN_SIZE_CAP 0x020 |
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45 #define HPET_TN_SETVAL 0x040 |
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46 #define HPET_TN_32BIT 0x100 |
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47 #define HPET_TN_INT_ROUTE_MASK 0x3e00 |
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48 #define HPET_TN_INT_ROUTE_SHIFT 9 |
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49 #define HPET_TN_INT_ROUTE_CAP_SHIFT 32 |
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50 #define HPET_TN_CFG_BITS_READONLY_OR_RESERVED 0xffff80b1U |
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51 |
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52 struct HPETState; |
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53 typedef struct HPETTimer { /* timers */ |
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54 uint8_t tn; /*timer number*/ |
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55 QEMUTimer *qemu_timer; |
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56 struct HPETState *state; |
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57 /* Memory-mapped, software visible timer registers */ |
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58 uint64_t config; /* configuration/cap */ |
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59 uint64_t cmp; /* comparator */ |
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60 uint64_t fsb; /* FSB route, not supported now */ |
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61 /* Hidden register state */ |
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62 uint64_t period; /* Last value written to comparator */ |
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63 uint8_t wrap_flag; /* timer pop will indicate wrap for one-shot 32-bit |
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64 * mode. Next pop will be actual timer expiration. |
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65 */ |
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66 } HPETTimer; |
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67 |
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68 typedef struct HPETState { |
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69 uint64_t hpet_offset; |
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70 qemu_irq *irqs; |
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71 HPETTimer timer[HPET_NUM_TIMERS]; |
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72 |
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73 /* Memory-mapped, software visible registers */ |
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74 uint64_t capability; /* capabilities */ |
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75 uint64_t config; /* configuration */ |
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76 uint64_t isr; /* interrupt status reg */ |
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77 uint64_t hpet_counter; /* main counter */ |
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78 } HPETState; |
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79 |
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80 #if defined TARGET_I386 || defined TARGET_X86_64 |
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81 extern uint32_t hpet_in_legacy_mode(void); |
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82 extern void hpet_init(qemu_irq *irq); |
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83 #endif |
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84 |
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85 #endif |