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1 /* |
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2 * QEMU/mipssim emulation |
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3 * |
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4 * Emulates a very simple machine model similiar to the one use by the |
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5 * proprietary MIPS emulator. |
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6 * |
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7 * Copyright (c) 2007 Thiemo Seufer |
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8 * |
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9 * Permission is hereby granted, free of charge, to any person obtaining a copy |
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10 * of this software and associated documentation files (the "Software"), to deal |
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11 * in the Software without restriction, including without limitation the rights |
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12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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13 * copies of the Software, and to permit persons to whom the Software is |
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14 * furnished to do so, subject to the following conditions: |
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15 * |
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16 * The above copyright notice and this permission notice shall be included in |
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17 * all copies or substantial portions of the Software. |
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18 * |
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19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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25 * THE SOFTWARE. |
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26 */ |
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27 #include "hw.h" |
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28 #include "mips.h" |
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29 #include "pc.h" |
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30 #include "isa.h" |
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31 #include "net.h" |
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32 #include "sysemu.h" |
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33 #include "boards.h" |
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34 |
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35 #ifdef TARGET_WORDS_BIGENDIAN |
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36 #define BIOS_FILENAME "mips_bios.bin" |
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37 #else |
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38 #define BIOS_FILENAME "mipsel_bios.bin" |
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39 #endif |
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40 |
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41 #ifdef TARGET_MIPS64 |
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42 #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffULL) |
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43 #else |
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44 #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffU) |
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45 #endif |
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46 |
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47 #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000)) |
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48 |
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49 static struct _loaderparams { |
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50 int ram_size; |
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51 const char *kernel_filename; |
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52 const char *kernel_cmdline; |
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53 const char *initrd_filename; |
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54 } loaderparams; |
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55 |
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56 static void load_kernel (CPUState *env) |
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57 { |
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58 int64_t entry, kernel_low, kernel_high; |
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59 long kernel_size; |
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60 long initrd_size; |
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61 ram_addr_t initrd_offset; |
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62 |
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63 kernel_size = load_elf(loaderparams.kernel_filename, VIRT_TO_PHYS_ADDEND, |
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64 (uint64_t *)&entry, (uint64_t *)&kernel_low, |
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65 (uint64_t *)&kernel_high); |
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66 if (kernel_size >= 0) { |
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67 if ((entry & ~0x7fffffffULL) == 0x80000000) |
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68 entry = (int32_t)entry; |
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69 env->active_tc.PC = entry; |
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70 } else { |
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71 fprintf(stderr, "qemu: could not load kernel '%s'\n", |
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72 loaderparams.kernel_filename); |
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73 exit(1); |
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74 } |
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75 |
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76 /* load initrd */ |
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77 initrd_size = 0; |
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78 initrd_offset = 0; |
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79 if (loaderparams.initrd_filename) { |
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80 initrd_size = get_image_size (loaderparams.initrd_filename); |
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81 if (initrd_size > 0) { |
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82 initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK; |
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83 if (initrd_offset + initrd_size > loaderparams.ram_size) { |
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84 fprintf(stderr, |
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85 "qemu: memory too small for initial ram disk '%s'\n", |
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86 loaderparams.initrd_filename); |
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87 exit(1); |
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88 } |
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89 initrd_size = load_image(loaderparams.initrd_filename, |
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90 phys_ram_base + initrd_offset); |
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91 } |
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92 if (initrd_size == (target_ulong) -1) { |
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93 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", |
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94 loaderparams.initrd_filename); |
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95 exit(1); |
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96 } |
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97 } |
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98 } |
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99 |
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100 static void main_cpu_reset(void *opaque) |
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101 { |
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102 CPUState *env = opaque; |
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103 cpu_reset(env); |
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104 |
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105 if (loaderparams.kernel_filename) |
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106 load_kernel (env); |
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107 } |
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108 |
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109 static void |
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110 mips_mipssim_init (ram_addr_t ram_size, int vga_ram_size, |
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111 const char *boot_device, DisplayState *ds, |
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112 const char *kernel_filename, const char *kernel_cmdline, |
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113 const char *initrd_filename, const char *cpu_model) |
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114 { |
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115 char buf[1024]; |
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116 unsigned long bios_offset; |
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117 CPUState *env; |
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118 int bios_size; |
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119 |
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120 /* Init CPUs. */ |
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121 if (cpu_model == NULL) { |
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122 #ifdef TARGET_MIPS64 |
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123 cpu_model = "5Kf"; |
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124 #else |
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125 cpu_model = "24Kf"; |
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126 #endif |
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127 } |
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128 env = cpu_init(cpu_model); |
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129 if (!env) { |
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130 fprintf(stderr, "Unable to find CPU definition\n"); |
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131 exit(1); |
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132 } |
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133 qemu_register_reset(main_cpu_reset, env); |
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134 |
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135 /* Allocate RAM. */ |
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136 cpu_register_physical_memory(0, ram_size, IO_MEM_RAM); |
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137 |
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138 /* Load a BIOS / boot exception handler image. */ |
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139 bios_offset = ram_size + vga_ram_size; |
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140 if (bios_name == NULL) |
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141 bios_name = BIOS_FILENAME; |
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142 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
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143 bios_size = load_image(buf, phys_ram_base + bios_offset); |
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144 if ((bios_size < 0 || bios_size > BIOS_SIZE) && !kernel_filename) { |
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145 /* Bail out if we have neither a kernel image nor boot vector code. */ |
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146 fprintf(stderr, |
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147 "qemu: Could not load MIPS bios '%s', and no -kernel argument was specified\n", |
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148 buf); |
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149 exit(1); |
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150 } else { |
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151 /* Map the BIOS / boot exception handler. */ |
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152 cpu_register_physical_memory(0x1fc00000LL, |
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153 bios_size, bios_offset | IO_MEM_ROM); |
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154 /* We have a boot vector start address. */ |
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155 env->active_tc.PC = (target_long)(int32_t)0xbfc00000; |
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156 } |
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157 |
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158 if (kernel_filename) { |
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159 loaderparams.ram_size = ram_size; |
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160 loaderparams.kernel_filename = kernel_filename; |
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161 loaderparams.kernel_cmdline = kernel_cmdline; |
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162 loaderparams.initrd_filename = initrd_filename; |
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163 load_kernel(env); |
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164 } |
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165 |
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166 /* Init CPU internal devices. */ |
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167 cpu_mips_irq_init_cpu(env); |
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168 cpu_mips_clock_init(env); |
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169 |
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170 /* Register 64 KB of ISA IO space at 0x1fd00000. */ |
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171 isa_mmio_init(0x1fd00000, 0x00010000); |
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172 |
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173 /* A single 16450 sits at offset 0x3f8. It is attached to |
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174 MIPS CPU INT2, which is interrupt 4. */ |
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175 if (serial_hds[0]) |
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176 serial_init(0x3f8, env->irq[4], 115200, serial_hds[0]); |
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177 |
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178 if (nd_table[0].vlan) { |
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179 if (nd_table[0].model == NULL |
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180 || strcmp(nd_table[0].model, "mipsnet") == 0) { |
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181 /* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */ |
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182 mipsnet_init(0x4200, env->irq[2], &nd_table[0]); |
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183 } else if (strcmp(nd_table[0].model, "?") == 0) { |
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184 fprintf(stderr, "qemu: Supported NICs: mipsnet\n"); |
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185 exit (1); |
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186 } else { |
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187 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
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188 exit (1); |
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189 } |
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190 } |
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191 } |
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192 |
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193 QEMUMachine mips_mipssim_machine = { |
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194 .name = "mipssim", |
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195 .desc = "MIPS MIPSsim platform", |
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196 .init = mips_mipssim_init, |
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197 .ram_require = BIOS_SIZE + VGA_RAM_SIZE /* unused */, |
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198 .nodisk_ok = 1, |
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199 }; |