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1 /* |
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2 * Texas Instruments OMAP processors. |
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3 * |
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4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> |
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5 * |
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6 * This program is free software; you can redistribute it and/or |
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7 * modify it under the terms of the GNU General Public License as |
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8 * published by the Free Software Foundation; either version 2 or |
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9 * (at your option) version 3 of the License. |
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10 * |
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11 * This program is distributed in the hope that it will be useful, |
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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14 * GNU General Public License for more details. |
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15 * |
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16 * You should have received a copy of the GNU General Public License |
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17 * along with this program; if not, write to the Free Software |
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18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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19 * MA 02111-1307 USA |
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20 */ |
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21 #ifndef hw_omap_h |
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22 # define hw_omap_h "omap.h" |
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23 |
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24 # define OMAP_EMIFS_BASE 0x00000000 |
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25 # define OMAP2_Q0_BASE 0x00000000 |
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26 # define OMAP_CS0_BASE 0x00000000 |
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27 # define OMAP_CS1_BASE 0x04000000 |
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28 # define OMAP_CS2_BASE 0x08000000 |
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29 # define OMAP_CS3_BASE 0x0c000000 |
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30 # define OMAP_EMIFF_BASE 0x10000000 |
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31 # define OMAP_IMIF_BASE 0x20000000 |
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32 # define OMAP_LOCALBUS_BASE 0x30000000 |
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33 # define OMAP2_Q1_BASE 0x40000000 |
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34 # define OMAP2_L4_BASE 0x48000000 |
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35 # define OMAP2_SRAM_BASE 0x40200000 |
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36 # define OMAP2_L3_BASE 0x68000000 |
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37 # define OMAP2_Q2_BASE 0x80000000 |
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38 # define OMAP2_Q3_BASE 0xc0000000 |
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39 # define OMAP_MPUI_BASE 0xe1000000 |
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40 |
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41 # define OMAP730_SRAM_SIZE 0x00032000 |
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42 # define OMAP15XX_SRAM_SIZE 0x00030000 |
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43 # define OMAP16XX_SRAM_SIZE 0x00004000 |
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44 # define OMAP1611_SRAM_SIZE 0x0003e800 |
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45 # define OMAP242X_SRAM_SIZE 0x000a0000 |
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46 # define OMAP243X_SRAM_SIZE 0x00010000 |
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47 # define OMAP_CS0_SIZE 0x04000000 |
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48 # define OMAP_CS1_SIZE 0x04000000 |
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49 # define OMAP_CS2_SIZE 0x04000000 |
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50 # define OMAP_CS3_SIZE 0x04000000 |
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51 |
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52 /* omap_clk.c */ |
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53 struct omap_mpu_state_s; |
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54 typedef struct clk *omap_clk; |
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55 omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name); |
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56 void omap_clk_init(struct omap_mpu_state_s *mpu); |
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57 void omap_clk_adduser(struct clk *clk, qemu_irq user); |
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58 void omap_clk_get(omap_clk clk); |
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59 void omap_clk_put(omap_clk clk); |
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60 void omap_clk_onoff(omap_clk clk, int on); |
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61 void omap_clk_canidle(omap_clk clk, int can); |
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62 void omap_clk_setrate(omap_clk clk, int divide, int multiply); |
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63 int64_t omap_clk_getrate(omap_clk clk); |
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64 void omap_clk_reparent(omap_clk clk, omap_clk parent); |
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65 |
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66 /* omap[123].c */ |
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67 struct omap_l4_s; |
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68 struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num); |
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69 |
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70 struct omap_target_agent_s; |
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71 struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs); |
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72 target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region, |
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73 int iotype); |
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74 # define l4_register_io_memory cpu_register_io_memory |
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75 |
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76 struct omap_intr_handler_s; |
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77 struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base, |
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78 unsigned long size, unsigned char nbanks, qemu_irq **pins, |
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79 qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk); |
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80 struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base, |
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81 int size, int nbanks, qemu_irq **pins, |
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82 qemu_irq parent_irq, qemu_irq parent_fiq, |
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83 omap_clk fclk, omap_clk iclk); |
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84 void omap_inth_reset(struct omap_intr_handler_s *s); |
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85 |
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86 struct omap_prcm_s; |
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87 struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta, |
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88 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int, |
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89 struct omap_mpu_state_s *mpu); |
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90 |
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91 struct omap_sysctl_s; |
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92 struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta, |
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93 omap_clk iclk, struct omap_mpu_state_s *mpu); |
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94 |
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95 struct omap_sdrc_s; |
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96 struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base); |
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97 |
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98 struct omap_gpmc_s; |
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99 struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq); |
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100 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype, |
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101 void (*base_upd)(void *opaque, target_phys_addr_t new), |
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102 void (*unmap)(void *opaque), void *opaque); |
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103 |
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104 /* |
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105 * Common IRQ numbers for level 1 interrupt handler |
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106 * See /usr/include/asm-arm/arch-omap/irqs.h in Linux. |
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107 */ |
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108 # define OMAP_INT_CAMERA 1 |
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109 # define OMAP_INT_FIQ 3 |
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110 # define OMAP_INT_RTDX 6 |
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111 # define OMAP_INT_DSP_MMU_ABORT 7 |
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112 # define OMAP_INT_HOST 8 |
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113 # define OMAP_INT_ABORT 9 |
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114 # define OMAP_INT_BRIDGE_PRIV 13 |
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115 # define OMAP_INT_GPIO_BANK1 14 |
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116 # define OMAP_INT_UART3 15 |
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117 # define OMAP_INT_TIMER3 16 |
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118 # define OMAP_INT_DMA_CH0_6 19 |
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119 # define OMAP_INT_DMA_CH1_7 20 |
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120 # define OMAP_INT_DMA_CH2_8 21 |
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121 # define OMAP_INT_DMA_CH3 22 |
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122 # define OMAP_INT_DMA_CH4 23 |
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123 # define OMAP_INT_DMA_CH5 24 |
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124 # define OMAP_INT_DMA_LCD 25 |
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125 # define OMAP_INT_TIMER1 26 |
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126 # define OMAP_INT_WD_TIMER 27 |
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127 # define OMAP_INT_BRIDGE_PUB 28 |
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128 # define OMAP_INT_TIMER2 30 |
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129 # define OMAP_INT_LCD_CTRL 31 |
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130 |
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131 /* |
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132 * Common OMAP-15xx IRQ numbers for level 1 interrupt handler |
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133 */ |
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134 # define OMAP_INT_15XX_IH2_IRQ 0 |
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135 # define OMAP_INT_15XX_LB_MMU 17 |
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136 # define OMAP_INT_15XX_LOCAL_BUS 29 |
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137 |
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138 /* |
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139 * OMAP-1510 specific IRQ numbers for level 1 interrupt handler |
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140 */ |
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141 # define OMAP_INT_1510_SPI_TX 4 |
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142 # define OMAP_INT_1510_SPI_RX 5 |
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143 # define OMAP_INT_1510_DSP_MAILBOX1 10 |
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144 # define OMAP_INT_1510_DSP_MAILBOX2 11 |
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145 |
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146 /* |
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147 * OMAP-310 specific IRQ numbers for level 1 interrupt handler |
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148 */ |
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149 # define OMAP_INT_310_McBSP2_TX 4 |
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150 # define OMAP_INT_310_McBSP2_RX 5 |
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151 # define OMAP_INT_310_HSB_MAILBOX1 12 |
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152 # define OMAP_INT_310_HSAB_MMU 18 |
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153 |
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154 /* |
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155 * OMAP-1610 specific IRQ numbers for level 1 interrupt handler |
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156 */ |
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157 # define OMAP_INT_1610_IH2_IRQ 0 |
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158 # define OMAP_INT_1610_IH2_FIQ 2 |
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159 # define OMAP_INT_1610_McBSP2_TX 4 |
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160 # define OMAP_INT_1610_McBSP2_RX 5 |
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161 # define OMAP_INT_1610_DSP_MAILBOX1 10 |
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162 # define OMAP_INT_1610_DSP_MAILBOX2 11 |
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163 # define OMAP_INT_1610_LCD_LINE 12 |
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164 # define OMAP_INT_1610_GPTIMER1 17 |
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165 # define OMAP_INT_1610_GPTIMER2 18 |
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166 # define OMAP_INT_1610_SSR_FIFO_0 29 |
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167 |
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168 /* |
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169 * OMAP-730 specific IRQ numbers for level 1 interrupt handler |
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170 */ |
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171 # define OMAP_INT_730_IH2_FIQ 0 |
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172 # define OMAP_INT_730_IH2_IRQ 1 |
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173 # define OMAP_INT_730_USB_NON_ISO 2 |
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174 # define OMAP_INT_730_USB_ISO 3 |
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175 # define OMAP_INT_730_ICR 4 |
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176 # define OMAP_INT_730_EAC 5 |
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177 # define OMAP_INT_730_GPIO_BANK1 6 |
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178 # define OMAP_INT_730_GPIO_BANK2 7 |
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179 # define OMAP_INT_730_GPIO_BANK3 8 |
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180 # define OMAP_INT_730_McBSP2TX 10 |
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181 # define OMAP_INT_730_McBSP2RX 11 |
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182 # define OMAP_INT_730_McBSP2RX_OVF 12 |
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183 # define OMAP_INT_730_LCD_LINE 14 |
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184 # define OMAP_INT_730_GSM_PROTECT 15 |
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185 # define OMAP_INT_730_TIMER3 16 |
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186 # define OMAP_INT_730_GPIO_BANK5 17 |
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187 # define OMAP_INT_730_GPIO_BANK6 18 |
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188 # define OMAP_INT_730_SPGIO_WR 29 |
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189 |
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190 /* |
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191 * Common IRQ numbers for level 2 interrupt handler |
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192 */ |
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193 # define OMAP_INT_KEYBOARD 1 |
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194 # define OMAP_INT_uWireTX 2 |
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195 # define OMAP_INT_uWireRX 3 |
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196 # define OMAP_INT_I2C 4 |
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197 # define OMAP_INT_MPUIO 5 |
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198 # define OMAP_INT_USB_HHC_1 6 |
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199 # define OMAP_INT_McBSP3TX 10 |
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200 # define OMAP_INT_McBSP3RX 11 |
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201 # define OMAP_INT_McBSP1TX 12 |
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202 # define OMAP_INT_McBSP1RX 13 |
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203 # define OMAP_INT_UART1 14 |
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204 # define OMAP_INT_UART2 15 |
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205 # define OMAP_INT_USB_W2FC 20 |
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206 # define OMAP_INT_1WIRE 21 |
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207 # define OMAP_INT_OS_TIMER 22 |
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208 # define OMAP_INT_OQN 23 |
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209 # define OMAP_INT_GAUGE_32K 24 |
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210 # define OMAP_INT_RTC_TIMER 25 |
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211 # define OMAP_INT_RTC_ALARM 26 |
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212 # define OMAP_INT_DSP_MMU 28 |
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213 |
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214 /* |
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215 * OMAP-1510 specific IRQ numbers for level 2 interrupt handler |
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216 */ |
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217 # define OMAP_INT_1510_BT_MCSI1TX 16 |
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218 # define OMAP_INT_1510_BT_MCSI1RX 17 |
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219 # define OMAP_INT_1510_SoSSI_MATCH 19 |
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220 # define OMAP_INT_1510_MEM_STICK 27 |
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221 # define OMAP_INT_1510_COM_SPI_RO 31 |
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222 |
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223 /* |
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224 * OMAP-310 specific IRQ numbers for level 2 interrupt handler |
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225 */ |
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226 # define OMAP_INT_310_FAC 0 |
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227 # define OMAP_INT_310_USB_HHC_2 7 |
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228 # define OMAP_INT_310_MCSI1_FE 16 |
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229 # define OMAP_INT_310_MCSI2_FE 17 |
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230 # define OMAP_INT_310_USB_W2FC_ISO 29 |
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231 # define OMAP_INT_310_USB_W2FC_NON_ISO 30 |
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232 # define OMAP_INT_310_McBSP2RX_OF 31 |
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233 |
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234 /* |
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235 * OMAP-1610 specific IRQ numbers for level 2 interrupt handler |
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236 */ |
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237 # define OMAP_INT_1610_FAC 0 |
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238 # define OMAP_INT_1610_USB_HHC_2 7 |
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239 # define OMAP_INT_1610_USB_OTG 8 |
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240 # define OMAP_INT_1610_SoSSI 9 |
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241 # define OMAP_INT_1610_BT_MCSI1TX 16 |
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242 # define OMAP_INT_1610_BT_MCSI1RX 17 |
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243 # define OMAP_INT_1610_SoSSI_MATCH 19 |
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244 # define OMAP_INT_1610_MEM_STICK 27 |
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245 # define OMAP_INT_1610_McBSP2RX_OF 31 |
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246 # define OMAP_INT_1610_STI 32 |
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247 # define OMAP_INT_1610_STI_WAKEUP 33 |
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248 # define OMAP_INT_1610_GPTIMER3 34 |
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249 # define OMAP_INT_1610_GPTIMER4 35 |
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250 # define OMAP_INT_1610_GPTIMER5 36 |
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251 # define OMAP_INT_1610_GPTIMER6 37 |
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252 # define OMAP_INT_1610_GPTIMER7 38 |
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253 # define OMAP_INT_1610_GPTIMER8 39 |
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254 # define OMAP_INT_1610_GPIO_BANK2 40 |
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255 # define OMAP_INT_1610_GPIO_BANK3 41 |
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256 # define OMAP_INT_1610_MMC2 42 |
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257 # define OMAP_INT_1610_CF 43 |
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258 # define OMAP_INT_1610_WAKE_UP_REQ 46 |
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259 # define OMAP_INT_1610_GPIO_BANK4 48 |
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260 # define OMAP_INT_1610_SPI 49 |
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261 # define OMAP_INT_1610_DMA_CH6 53 |
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262 # define OMAP_INT_1610_DMA_CH7 54 |
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263 # define OMAP_INT_1610_DMA_CH8 55 |
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264 # define OMAP_INT_1610_DMA_CH9 56 |
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265 # define OMAP_INT_1610_DMA_CH10 57 |
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266 # define OMAP_INT_1610_DMA_CH11 58 |
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267 # define OMAP_INT_1610_DMA_CH12 59 |
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268 # define OMAP_INT_1610_DMA_CH13 60 |
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269 # define OMAP_INT_1610_DMA_CH14 61 |
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270 # define OMAP_INT_1610_DMA_CH15 62 |
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271 # define OMAP_INT_1610_NAND 63 |
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272 |
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273 /* |
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274 * OMAP-730 specific IRQ numbers for level 2 interrupt handler |
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275 */ |
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276 # define OMAP_INT_730_HW_ERRORS 0 |
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277 # define OMAP_INT_730_NFIQ_PWR_FAIL 1 |
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278 # define OMAP_INT_730_CFCD 2 |
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279 # define OMAP_INT_730_CFIREQ 3 |
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280 # define OMAP_INT_730_I2C 4 |
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281 # define OMAP_INT_730_PCC 5 |
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282 # define OMAP_INT_730_MPU_EXT_NIRQ 6 |
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283 # define OMAP_INT_730_SPI_100K_1 7 |
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284 # define OMAP_INT_730_SYREN_SPI 8 |
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285 # define OMAP_INT_730_VLYNQ 9 |
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286 # define OMAP_INT_730_GPIO_BANK4 10 |
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287 # define OMAP_INT_730_McBSP1TX 11 |
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288 # define OMAP_INT_730_McBSP1RX 12 |
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289 # define OMAP_INT_730_McBSP1RX_OF 13 |
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290 # define OMAP_INT_730_UART_MODEM_IRDA_2 14 |
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291 # define OMAP_INT_730_UART_MODEM_1 15 |
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292 # define OMAP_INT_730_MCSI 16 |
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293 # define OMAP_INT_730_uWireTX 17 |
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294 # define OMAP_INT_730_uWireRX 18 |
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295 # define OMAP_INT_730_SMC_CD 19 |
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296 # define OMAP_INT_730_SMC_IREQ 20 |
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297 # define OMAP_INT_730_HDQ_1WIRE 21 |
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298 # define OMAP_INT_730_TIMER32K 22 |
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299 # define OMAP_INT_730_MMC_SDIO 23 |
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300 # define OMAP_INT_730_UPLD 24 |
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301 # define OMAP_INT_730_USB_HHC_1 27 |
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302 # define OMAP_INT_730_USB_HHC_2 28 |
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303 # define OMAP_INT_730_USB_GENI 29 |
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304 # define OMAP_INT_730_USB_OTG 30 |
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305 # define OMAP_INT_730_CAMERA_IF 31 |
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306 # define OMAP_INT_730_RNG 32 |
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307 # define OMAP_INT_730_DUAL_MODE_TIMER 33 |
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308 # define OMAP_INT_730_DBB_RF_EN 34 |
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309 # define OMAP_INT_730_MPUIO_KEYPAD 35 |
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310 # define OMAP_INT_730_SHA1_MD5 36 |
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311 # define OMAP_INT_730_SPI_100K_2 37 |
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312 # define OMAP_INT_730_RNG_IDLE 38 |
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313 # define OMAP_INT_730_MPUIO 39 |
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314 # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40 |
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315 # define OMAP_INT_730_LLPC_OE_FALLING 41 |
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316 # define OMAP_INT_730_LLPC_OE_RISING 42 |
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317 # define OMAP_INT_730_LLPC_VSYNC 43 |
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318 # define OMAP_INT_730_WAKE_UP_REQ 46 |
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319 # define OMAP_INT_730_DMA_CH6 53 |
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320 # define OMAP_INT_730_DMA_CH7 54 |
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321 # define OMAP_INT_730_DMA_CH8 55 |
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322 # define OMAP_INT_730_DMA_CH9 56 |
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323 # define OMAP_INT_730_DMA_CH10 57 |
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324 # define OMAP_INT_730_DMA_CH11 58 |
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325 # define OMAP_INT_730_DMA_CH12 59 |
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326 # define OMAP_INT_730_DMA_CH13 60 |
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327 # define OMAP_INT_730_DMA_CH14 61 |
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328 # define OMAP_INT_730_DMA_CH15 62 |
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329 # define OMAP_INT_730_NAND 63 |
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330 |
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331 /* |
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332 * OMAP-24xx common IRQ numbers |
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333 */ |
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334 # define OMAP_INT_24XX_STI 4 |
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335 # define OMAP_INT_24XX_SYS_NIRQ 7 |
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336 # define OMAP_INT_24XX_L3_IRQ 10 |
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337 # define OMAP_INT_24XX_PRCM_MPU_IRQ 11 |
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338 # define OMAP_INT_24XX_SDMA_IRQ0 12 |
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339 # define OMAP_INT_24XX_SDMA_IRQ1 13 |
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340 # define OMAP_INT_24XX_SDMA_IRQ2 14 |
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341 # define OMAP_INT_24XX_SDMA_IRQ3 15 |
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342 # define OMAP_INT_243X_MCBSP2_IRQ 16 |
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343 # define OMAP_INT_243X_MCBSP3_IRQ 17 |
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344 # define OMAP_INT_243X_MCBSP4_IRQ 18 |
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345 # define OMAP_INT_243X_MCBSP5_IRQ 19 |
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346 # define OMAP_INT_24XX_GPMC_IRQ 20 |
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347 # define OMAP_INT_24XX_GUFFAW_IRQ 21 |
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348 # define OMAP_INT_24XX_IVA_IRQ 22 |
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349 # define OMAP_INT_24XX_EAC_IRQ 23 |
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350 # define OMAP_INT_24XX_CAM_IRQ 24 |
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351 # define OMAP_INT_24XX_DSS_IRQ 25 |
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352 # define OMAP_INT_24XX_MAIL_U0_MPU 26 |
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353 # define OMAP_INT_24XX_DSP_UMA 27 |
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354 # define OMAP_INT_24XX_DSP_MMU 28 |
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355 # define OMAP_INT_24XX_GPIO_BANK1 29 |
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356 # define OMAP_INT_24XX_GPIO_BANK2 30 |
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357 # define OMAP_INT_24XX_GPIO_BANK3 31 |
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358 # define OMAP_INT_24XX_GPIO_BANK4 32 |
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359 # define OMAP_INT_243X_GPIO_BANK5 33 |
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360 # define OMAP_INT_24XX_MAIL_U3_MPU 34 |
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361 # define OMAP_INT_24XX_WDT3 35 |
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362 # define OMAP_INT_24XX_WDT4 36 |
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363 # define OMAP_INT_24XX_GPTIMER1 37 |
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364 # define OMAP_INT_24XX_GPTIMER2 38 |
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365 # define OMAP_INT_24XX_GPTIMER3 39 |
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366 # define OMAP_INT_24XX_GPTIMER4 40 |
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367 # define OMAP_INT_24XX_GPTIMER5 41 |
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368 # define OMAP_INT_24XX_GPTIMER6 42 |
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369 # define OMAP_INT_24XX_GPTIMER7 43 |
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370 # define OMAP_INT_24XX_GPTIMER8 44 |
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371 # define OMAP_INT_24XX_GPTIMER9 45 |
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372 # define OMAP_INT_24XX_GPTIMER10 46 |
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373 # define OMAP_INT_24XX_GPTIMER11 47 |
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374 # define OMAP_INT_24XX_GPTIMER12 48 |
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375 # define OMAP_INT_24XX_PKA_IRQ 50 |
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376 # define OMAP_INT_24XX_SHA1MD5_IRQ 51 |
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377 # define OMAP_INT_24XX_RNG_IRQ 52 |
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378 # define OMAP_INT_24XX_MG_IRQ 53 |
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379 # define OMAP_INT_24XX_I2C1_IRQ 56 |
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380 # define OMAP_INT_24XX_I2C2_IRQ 57 |
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381 # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59 |
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382 # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60 |
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383 # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62 |
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384 # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63 |
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385 # define OMAP_INT_243X_MCBSP1_IRQ 64 |
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386 # define OMAP_INT_24XX_MCSPI1_IRQ 65 |
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387 # define OMAP_INT_24XX_MCSPI2_IRQ 66 |
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388 # define OMAP_INT_24XX_SSI1_IRQ0 67 |
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389 # define OMAP_INT_24XX_SSI1_IRQ1 68 |
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390 # define OMAP_INT_24XX_SSI2_IRQ0 69 |
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391 # define OMAP_INT_24XX_SSI2_IRQ1 70 |
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392 # define OMAP_INT_24XX_SSI_GDD_IRQ 71 |
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393 # define OMAP_INT_24XX_UART1_IRQ 72 |
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394 # define OMAP_INT_24XX_UART2_IRQ 73 |
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395 # define OMAP_INT_24XX_UART3_IRQ 74 |
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396 # define OMAP_INT_24XX_USB_IRQ_GEN 75 |
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397 # define OMAP_INT_24XX_USB_IRQ_NISO 76 |
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398 # define OMAP_INT_24XX_USB_IRQ_ISO 77 |
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399 # define OMAP_INT_24XX_USB_IRQ_HGEN 78 |
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400 # define OMAP_INT_24XX_USB_IRQ_HSOF 79 |
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401 # define OMAP_INT_24XX_USB_IRQ_OTG 80 |
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402 # define OMAP_INT_24XX_VLYNQ_IRQ 81 |
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403 # define OMAP_INT_24XX_MMC_IRQ 83 |
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404 # define OMAP_INT_24XX_MS_IRQ 84 |
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405 # define OMAP_INT_24XX_FAC_IRQ 85 |
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406 # define OMAP_INT_24XX_MCSPI3_IRQ 91 |
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407 # define OMAP_INT_243X_HS_USB_MC 92 |
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408 # define OMAP_INT_243X_HS_USB_DMA 93 |
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409 # define OMAP_INT_243X_CARKIT 94 |
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410 # define OMAP_INT_34XX_GPTIMER12 95 |
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411 |
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412 /* omap_dma.c */ |
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413 enum omap_dma_model { |
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414 omap_dma_3_0, |
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415 omap_dma_3_1, |
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416 omap_dma_3_2, |
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417 omap_dma_4, |
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418 }; |
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419 |
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420 struct soc_dma_s; |
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421 struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs, |
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422 qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, |
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423 enum omap_dma_model model); |
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424 struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs, |
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425 struct omap_mpu_state_s *mpu, int fifo, |
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426 int chans, omap_clk iclk, omap_clk fclk); |
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427 void omap_dma_reset(struct soc_dma_s *s); |
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428 |
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429 struct dma_irq_map { |
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430 int ih; |
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431 int intr; |
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432 }; |
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433 |
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434 /* Only used in OMAP DMA 3.x gigacells */ |
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435 enum omap_dma_port { |
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436 emiff = 0, |
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437 emifs, |
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438 imif, /* omap16xx: ocp_t1 */ |
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439 tipb, |
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440 local, /* omap16xx: ocp_t2 */ |
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441 tipb_mpui, |
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442 __omap_dma_port_last, |
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443 }; |
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444 |
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445 typedef enum { |
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446 constant = 0, |
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447 post_incremented, |
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448 single_index, |
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449 double_index, |
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450 } omap_dma_addressing_t; |
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451 |
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452 /* Only used in OMAP DMA 3.x gigacells */ |
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453 struct omap_dma_lcd_channel_s { |
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454 enum omap_dma_port src; |
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455 target_phys_addr_t src_f1_top; |
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456 target_phys_addr_t src_f1_bottom; |
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457 target_phys_addr_t src_f2_top; |
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458 target_phys_addr_t src_f2_bottom; |
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459 |
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460 /* Used in OMAP DMA 3.2 gigacell */ |
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461 unsigned char brust_f1; |
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462 unsigned char pack_f1; |
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463 unsigned char data_type_f1; |
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464 unsigned char brust_f2; |
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465 unsigned char pack_f2; |
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466 unsigned char data_type_f2; |
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467 unsigned char end_prog; |
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468 unsigned char repeat; |
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469 unsigned char auto_init; |
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470 unsigned char priority; |
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471 unsigned char fs; |
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472 unsigned char running; |
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473 unsigned char bs; |
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474 unsigned char omap_3_1_compatible_disable; |
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475 unsigned char dst; |
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476 unsigned char lch_type; |
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477 int16_t element_index_f1; |
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478 int16_t element_index_f2; |
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479 int32_t frame_index_f1; |
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480 int32_t frame_index_f2; |
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481 uint16_t elements_f1; |
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482 uint16_t frames_f1; |
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483 uint16_t elements_f2; |
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484 uint16_t frames_f2; |
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485 omap_dma_addressing_t mode_f1; |
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486 omap_dma_addressing_t mode_f2; |
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487 |
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488 /* Destination port is fixed. */ |
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489 int interrupts; |
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490 int condition; |
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491 int dual; |
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492 |
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493 int current_frame; |
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494 ram_addr_t phys_framebuffer[2]; |
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495 qemu_irq irq; |
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496 struct omap_mpu_state_s *mpu; |
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497 } *omap_dma_get_lcdch(struct soc_dma_s *s); |
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498 |
|
499 /* |
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500 * DMA request numbers for OMAP1 |
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501 * See /usr/include/asm-arm/arch-omap/dma.h in Linux. |
|
502 */ |
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503 # define OMAP_DMA_NO_DEVICE 0 |
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504 # define OMAP_DMA_MCSI1_TX 1 |
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505 # define OMAP_DMA_MCSI1_RX 2 |
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506 # define OMAP_DMA_I2C_RX 3 |
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507 # define OMAP_DMA_I2C_TX 4 |
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508 # define OMAP_DMA_EXT_NDMA_REQ0 5 |
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509 # define OMAP_DMA_EXT_NDMA_REQ1 6 |
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510 # define OMAP_DMA_UWIRE_TX 7 |
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511 # define OMAP_DMA_MCBSP1_TX 8 |
|
512 # define OMAP_DMA_MCBSP1_RX 9 |
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513 # define OMAP_DMA_MCBSP3_TX 10 |
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514 # define OMAP_DMA_MCBSP3_RX 11 |
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515 # define OMAP_DMA_UART1_TX 12 |
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516 # define OMAP_DMA_UART1_RX 13 |
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517 # define OMAP_DMA_UART2_TX 14 |
|
518 # define OMAP_DMA_UART2_RX 15 |
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519 # define OMAP_DMA_MCBSP2_TX 16 |
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520 # define OMAP_DMA_MCBSP2_RX 17 |
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521 # define OMAP_DMA_UART3_TX 18 |
|
522 # define OMAP_DMA_UART3_RX 19 |
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523 # define OMAP_DMA_CAMERA_IF_RX 20 |
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524 # define OMAP_DMA_MMC_TX 21 |
|
525 # define OMAP_DMA_MMC_RX 22 |
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526 # define OMAP_DMA_NAND 23 /* Not in OMAP310 */ |
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527 # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */ |
|
528 # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */ |
|
529 # define OMAP_DMA_USB_W2FC_RX0 26 |
|
530 # define OMAP_DMA_USB_W2FC_RX1 27 |
|
531 # define OMAP_DMA_USB_W2FC_RX2 28 |
|
532 # define OMAP_DMA_USB_W2FC_TX0 29 |
|
533 # define OMAP_DMA_USB_W2FC_TX1 30 |
|
534 # define OMAP_DMA_USB_W2FC_TX2 31 |
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535 |
|
536 /* These are only for 1610 */ |
|
537 # define OMAP_DMA_CRYPTO_DES_IN 32 |
|
538 # define OMAP_DMA_SPI_TX 33 |
|
539 # define OMAP_DMA_SPI_RX 34 |
|
540 # define OMAP_DMA_CRYPTO_HASH 35 |
|
541 # define OMAP_DMA_CCP_ATTN 36 |
|
542 # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 |
|
543 # define OMAP_DMA_CMT_APE_TX_CHAN_0 38 |
|
544 # define OMAP_DMA_CMT_APE_RV_CHAN_0 39 |
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545 # define OMAP_DMA_CMT_APE_TX_CHAN_1 40 |
|
546 # define OMAP_DMA_CMT_APE_RV_CHAN_1 41 |
|
547 # define OMAP_DMA_CMT_APE_TX_CHAN_2 42 |
|
548 # define OMAP_DMA_CMT_APE_RV_CHAN_2 43 |
|
549 # define OMAP_DMA_CMT_APE_TX_CHAN_3 44 |
|
550 # define OMAP_DMA_CMT_APE_RV_CHAN_3 45 |
|
551 # define OMAP_DMA_CMT_APE_TX_CHAN_4 46 |
|
552 # define OMAP_DMA_CMT_APE_RV_CHAN_4 47 |
|
553 # define OMAP_DMA_CMT_APE_TX_CHAN_5 48 |
|
554 # define OMAP_DMA_CMT_APE_RV_CHAN_5 49 |
|
555 # define OMAP_DMA_CMT_APE_TX_CHAN_6 50 |
|
556 # define OMAP_DMA_CMT_APE_RV_CHAN_6 51 |
|
557 # define OMAP_DMA_CMT_APE_TX_CHAN_7 52 |
|
558 # define OMAP_DMA_CMT_APE_RV_CHAN_7 53 |
|
559 # define OMAP_DMA_MMC2_TX 54 |
|
560 # define OMAP_DMA_MMC2_RX 55 |
|
561 # define OMAP_DMA_CRYPTO_DES_OUT 56 |
|
562 |
|
563 /* |
|
564 * DMA request numbers for the OMAP2 |
|
565 */ |
|
566 # define OMAP24XX_DMA_NO_DEVICE 0 |
|
567 # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */ |
|
568 # define OMAP24XX_DMA_EXT_DMAREQ0 2 |
|
569 # define OMAP24XX_DMA_EXT_DMAREQ1 3 |
|
570 # define OMAP24XX_DMA_GPMC 4 |
|
571 # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */ |
|
572 # define OMAP24XX_DMA_DSS 6 |
|
573 # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */ |
|
574 # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */ |
|
575 # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */ |
|
576 # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */ |
|
577 # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */ |
|
578 # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */ |
|
579 # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */ |
|
580 # define OMAP24XX_DMA_EXT_DMAREQ2 14 |
|
581 # define OMAP24XX_DMA_EXT_DMAREQ3 15 |
|
582 # define OMAP24XX_DMA_EXT_DMAREQ4 16 |
|
583 # define OMAP24XX_DMA_EAC_AC_RD 17 |
|
584 # define OMAP24XX_DMA_EAC_AC_WR 18 |
|
585 # define OMAP24XX_DMA_EAC_MD_UL_RD 19 |
|
586 # define OMAP24XX_DMA_EAC_MD_UL_WR 20 |
|
587 # define OMAP24XX_DMA_EAC_MD_DL_RD 21 |
|
588 # define OMAP24XX_DMA_EAC_MD_DL_WR 22 |
|
589 # define OMAP24XX_DMA_EAC_BT_UL_RD 23 |
|
590 # define OMAP24XX_DMA_EAC_BT_UL_WR 24 |
|
591 # define OMAP24XX_DMA_EAC_BT_DL_RD 25 |
|
592 # define OMAP24XX_DMA_EAC_BT_DL_WR 26 |
|
593 # define OMAP24XX_DMA_I2C1_TX 27 |
|
594 # define OMAP24XX_DMA_I2C1_RX 28 |
|
595 # define OMAP24XX_DMA_I2C2_TX 29 |
|
596 # define OMAP24XX_DMA_I2C2_RX 30 |
|
597 # define OMAP24XX_DMA_MCBSP1_TX 31 |
|
598 # define OMAP24XX_DMA_MCBSP1_RX 32 |
|
599 # define OMAP24XX_DMA_MCBSP2_TX 33 |
|
600 # define OMAP24XX_DMA_MCBSP2_RX 34 |
|
601 # define OMAP24XX_DMA_SPI1_TX0 35 |
|
602 # define OMAP24XX_DMA_SPI1_RX0 36 |
|
603 # define OMAP24XX_DMA_SPI1_TX1 37 |
|
604 # define OMAP24XX_DMA_SPI1_RX1 38 |
|
605 # define OMAP24XX_DMA_SPI1_TX2 39 |
|
606 # define OMAP24XX_DMA_SPI1_RX2 40 |
|
607 # define OMAP24XX_DMA_SPI1_TX3 41 |
|
608 # define OMAP24XX_DMA_SPI1_RX3 42 |
|
609 # define OMAP24XX_DMA_SPI2_TX0 43 |
|
610 # define OMAP24XX_DMA_SPI2_RX0 44 |
|
611 # define OMAP24XX_DMA_SPI2_TX1 45 |
|
612 # define OMAP24XX_DMA_SPI2_RX1 46 |
|
613 |
|
614 # define OMAP24XX_DMA_UART1_TX 49 |
|
615 # define OMAP24XX_DMA_UART1_RX 50 |
|
616 # define OMAP24XX_DMA_UART2_TX 51 |
|
617 # define OMAP24XX_DMA_UART2_RX 52 |
|
618 # define OMAP24XX_DMA_UART3_TX 53 |
|
619 # define OMAP24XX_DMA_UART3_RX 54 |
|
620 # define OMAP24XX_DMA_USB_W2FC_TX0 55 |
|
621 # define OMAP24XX_DMA_USB_W2FC_RX0 56 |
|
622 # define OMAP24XX_DMA_USB_W2FC_TX1 57 |
|
623 # define OMAP24XX_DMA_USB_W2FC_RX1 58 |
|
624 # define OMAP24XX_DMA_USB_W2FC_TX2 59 |
|
625 # define OMAP24XX_DMA_USB_W2FC_RX2 60 |
|
626 # define OMAP24XX_DMA_MMC1_TX 61 |
|
627 # define OMAP24XX_DMA_MMC1_RX 62 |
|
628 # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */ |
|
629 # define OMAP24XX_DMA_EXT_DMAREQ5 64 |
|
630 |
|
631 /* omap[123].c */ |
|
632 struct omap_mpu_timer_s; |
|
633 struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base, |
|
634 qemu_irq irq, omap_clk clk); |
|
635 |
|
636 struct omap_gp_timer_s; |
|
637 struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, |
|
638 qemu_irq irq, omap_clk fclk, omap_clk iclk); |
|
639 |
|
640 struct omap_watchdog_timer_s; |
|
641 struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base, |
|
642 qemu_irq irq, omap_clk clk); |
|
643 |
|
644 struct omap_32khz_timer_s; |
|
645 struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base, |
|
646 qemu_irq irq, omap_clk clk); |
|
647 |
|
648 void omap_synctimer_init(struct omap_target_agent_s *ta, |
|
649 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk); |
|
650 |
|
651 struct omap_tipb_bridge_s; |
|
652 struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base, |
|
653 qemu_irq abort_irq, omap_clk clk); |
|
654 |
|
655 struct omap_uart_s; |
|
656 struct omap_uart_s *omap_uart_init(target_phys_addr_t base, |
|
657 qemu_irq irq, omap_clk fclk, omap_clk iclk, |
|
658 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr); |
|
659 struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta, |
|
660 qemu_irq irq, omap_clk fclk, omap_clk iclk, |
|
661 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr); |
|
662 void omap_uart_reset(struct omap_uart_s *s); |
|
663 void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr); |
|
664 |
|
665 struct omap_mpuio_s; |
|
666 struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base, |
|
667 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, |
|
668 omap_clk clk); |
|
669 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s); |
|
670 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler); |
|
671 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down); |
|
672 |
|
673 struct omap_gpio_s; |
|
674 struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base, |
|
675 qemu_irq irq, omap_clk clk); |
|
676 qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s); |
|
677 void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler); |
|
678 |
|
679 struct omap_gpif_s; |
|
680 struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta, |
|
681 qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules); |
|
682 qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start); |
|
683 void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler); |
|
684 |
|
685 struct uwire_slave_s { |
|
686 uint16_t (*receive)(void *opaque); |
|
687 void (*send)(void *opaque, uint16_t data); |
|
688 void *opaque; |
|
689 }; |
|
690 struct omap_uwire_s; |
|
691 struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base, |
|
692 qemu_irq *irq, qemu_irq dma, omap_clk clk); |
|
693 void omap_uwire_attach(struct omap_uwire_s *s, |
|
694 struct uwire_slave_s *slave, int chipselect); |
|
695 |
|
696 struct omap_mcspi_s; |
|
697 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum, |
|
698 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk); |
|
699 void omap_mcspi_attach(struct omap_mcspi_s *s, |
|
700 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque, |
|
701 int chipselect); |
|
702 |
|
703 struct omap_rtc_s; |
|
704 struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base, |
|
705 qemu_irq *irq, omap_clk clk); |
|
706 |
|
707 struct i2s_codec_s { |
|
708 void *opaque; |
|
709 |
|
710 /* The CPU can call this if it is generating the clock signal on the |
|
711 * i2s port. The CODEC can ignore it if it is set up as a clock |
|
712 * master and generates its own clock. */ |
|
713 void (*set_rate)(void *opaque, int in, int out); |
|
714 |
|
715 void (*tx_swallow)(void *opaque); |
|
716 qemu_irq rx_swallow; |
|
717 qemu_irq tx_start; |
|
718 |
|
719 int tx_rate; |
|
720 int cts; |
|
721 int rx_rate; |
|
722 int rts; |
|
723 |
|
724 struct i2s_fifo_s { |
|
725 uint8_t *fifo; |
|
726 int len; |
|
727 int start; |
|
728 int size; |
|
729 } in, out; |
|
730 }; |
|
731 struct omap_mcbsp_s; |
|
732 struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base, |
|
733 qemu_irq *irq, qemu_irq *dma, omap_clk clk); |
|
734 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave); |
|
735 |
|
736 struct omap_lpg_s; |
|
737 struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk); |
|
738 |
|
739 void omap_tap_init(struct omap_target_agent_s *ta, |
|
740 struct omap_mpu_state_s *mpu); |
|
741 |
|
742 struct omap_eac_s; |
|
743 struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta, |
|
744 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk); |
|
745 |
|
746 /* omap_lcdc.c */ |
|
747 struct omap_lcd_panel_s; |
|
748 void omap_lcdc_reset(struct omap_lcd_panel_s *s); |
|
749 struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq, |
|
750 struct omap_dma_lcd_channel_s *dma, DisplayState *ds, |
|
751 ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk); |
|
752 |
|
753 /* omap_dss.c */ |
|
754 struct rfbi_chip_s { |
|
755 void *opaque; |
|
756 void (*write)(void *opaque, int dc, uint16_t value); |
|
757 void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch); |
|
758 uint16_t (*read)(void *opaque, int dc); |
|
759 }; |
|
760 struct omap_dss_s; |
|
761 void omap_dss_reset(struct omap_dss_s *s); |
|
762 struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, |
|
763 target_phys_addr_t l3_base, DisplayState *ds, |
|
764 qemu_irq irq, qemu_irq drq, |
|
765 omap_clk fck1, omap_clk fck2, omap_clk ck54m, |
|
766 omap_clk ick1, omap_clk ick2); |
|
767 void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip); |
|
768 |
|
769 /* omap_mmc.c */ |
|
770 struct omap_mmc_s; |
|
771 struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base, |
|
772 BlockDriverState *bd, |
|
773 qemu_irq irq, qemu_irq dma[], omap_clk clk); |
|
774 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, |
|
775 BlockDriverState *bd, qemu_irq irq, qemu_irq dma[], |
|
776 omap_clk fclk, omap_clk iclk); |
|
777 void omap_mmc_reset(struct omap_mmc_s *s); |
|
778 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover); |
|
779 void omap_mmc_enable(struct omap_mmc_s *s, int enable); |
|
780 |
|
781 /* omap_i2c.c */ |
|
782 struct omap_i2c_s; |
|
783 struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base, |
|
784 qemu_irq irq, qemu_irq *dma, omap_clk clk); |
|
785 struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta, |
|
786 qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk); |
|
787 void omap_i2c_reset(struct omap_i2c_s *s); |
|
788 i2c_bus *omap_i2c_bus(struct omap_i2c_s *s); |
|
789 |
|
790 # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310) |
|
791 # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510) |
|
792 # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610) |
|
793 # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710) |
|
794 # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410) |
|
795 # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420) |
|
796 # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430) |
|
797 # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430) |
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798 |
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799 # define cpu_is_omap15xx(cpu) \ |
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800 (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu)) |
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801 # define cpu_is_omap16xx(cpu) \ |
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802 (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu)) |
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803 # define cpu_is_omap24xx(cpu) \ |
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804 (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu)) |
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805 |
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806 # define cpu_class_omap1(cpu) \ |
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807 (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu)) |
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808 # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu) |
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809 # define cpu_class_omap3(cpu) cpu_is_omap3430(cpu) |
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810 |
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811 struct omap_mpu_state_s { |
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812 enum omap_mpu_model { |
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813 omap310, |
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814 omap1510, |
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815 omap1610, |
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816 omap1710, |
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817 omap2410, |
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818 omap2420, |
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819 omap2422, |
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820 omap2423, |
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821 omap2430, |
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822 omap3430, |
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823 } mpu_model; |
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824 |
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825 CPUState *env; |
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826 |
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827 qemu_irq *irq[2]; |
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828 qemu_irq *drq; |
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829 |
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830 qemu_irq wakeup; |
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831 |
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832 struct omap_dma_port_if_s { |
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833 uint32_t (*read[3])(struct omap_mpu_state_s *s, |
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834 target_phys_addr_t offset); |
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835 void (*write[3])(struct omap_mpu_state_s *s, |
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836 target_phys_addr_t offset, uint32_t value); |
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837 int (*addr_valid)(struct omap_mpu_state_s *s, |
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838 target_phys_addr_t addr); |
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839 } port[__omap_dma_port_last]; |
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840 |
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841 unsigned long sdram_size; |
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842 unsigned long sram_size; |
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843 |
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844 /* MPUI-TIPB peripherals */ |
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845 struct omap_uart_s *uart[3]; |
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846 |
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847 struct omap_gpio_s *gpio; |
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848 |
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849 struct omap_mcbsp_s *mcbsp1; |
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850 struct omap_mcbsp_s *mcbsp3; |
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851 |
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852 /* MPU public TIPB peripherals */ |
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853 struct omap_32khz_timer_s *os_timer; |
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854 |
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855 struct omap_mmc_s *mmc; |
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856 |
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857 struct omap_mpuio_s *mpuio; |
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858 |
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859 struct omap_uwire_s *microwire; |
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860 |
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861 struct { |
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862 uint8_t output; |
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863 uint8_t level; |
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864 uint8_t enable; |
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865 int clk; |
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866 } pwl; |
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867 |
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868 struct { |
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869 uint8_t frc; |
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870 uint8_t vrc; |
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871 uint8_t gcr; |
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872 omap_clk clk; |
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873 } pwt; |
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874 |
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875 struct omap_i2c_s *i2c[2]; |
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876 |
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877 struct omap_rtc_s *rtc; |
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878 |
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879 struct omap_mcbsp_s *mcbsp2; |
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880 |
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881 struct omap_lpg_s *led[2]; |
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882 |
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883 /* MPU private TIPB peripherals */ |
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884 struct omap_intr_handler_s *ih[2]; |
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885 |
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886 struct soc_dma_s *dma; |
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887 |
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888 struct omap_mpu_timer_s *timer[3]; |
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889 struct omap_watchdog_timer_s *wdt; |
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890 |
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891 struct omap_lcd_panel_s *lcd; |
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892 |
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893 uint32_t ulpd_pm_regs[21]; |
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894 int64_t ulpd_gauge_start; |
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895 |
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896 uint32_t func_mux_ctrl[14]; |
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897 uint32_t comp_mode_ctrl[1]; |
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898 uint32_t pull_dwn_ctrl[4]; |
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899 uint32_t gate_inh_ctrl[1]; |
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900 uint32_t voltage_ctrl[1]; |
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901 uint32_t test_dbg_ctrl[1]; |
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902 uint32_t mod_conf_ctrl[1]; |
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903 int compat1509; |
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904 |
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905 uint32_t mpui_ctrl; |
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906 |
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907 struct omap_tipb_bridge_s *private_tipb; |
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908 struct omap_tipb_bridge_s *public_tipb; |
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909 |
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910 uint32_t tcmi_regs[17]; |
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911 |
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912 struct dpll_ctl_s { |
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913 uint16_t mode; |
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914 omap_clk dpll; |
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915 } dpll[3]; |
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916 |
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917 omap_clk clks; |
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918 struct { |
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919 int cold_start; |
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920 int clocking_scheme; |
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921 uint16_t arm_ckctl; |
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922 uint16_t arm_idlect1; |
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923 uint16_t arm_idlect2; |
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924 uint16_t arm_ewupct; |
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925 uint16_t arm_rstct1; |
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926 uint16_t arm_rstct2; |
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927 uint16_t arm_ckout1; |
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928 int dpll1_mode; |
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929 uint16_t dsp_idlect1; |
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930 uint16_t dsp_idlect2; |
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931 uint16_t dsp_rstct2; |
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932 } clkm; |
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933 |
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934 /* OMAP2-only peripherals */ |
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935 struct omap_l4_s *l4; |
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936 |
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937 struct omap_gp_timer_s *gptimer[12]; |
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938 |
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939 struct omap_synctimer_s { |
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940 uint32_t val; |
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941 uint16_t readh; |
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942 } synctimer; |
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943 |
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944 struct omap_prcm_s *prcm; |
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945 struct omap_sdrc_s *sdrc; |
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946 struct omap_gpmc_s *gpmc; |
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947 struct omap_sysctl_s *sysc; |
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948 |
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949 struct omap_gpif_s *gpif; |
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950 |
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951 struct omap_mcspi_s *mcspi[2]; |
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952 |
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953 struct omap_dss_s *dss; |
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954 |
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955 struct omap_eac_s *eac; |
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956 }; |
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957 |
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958 /* omap1.c */ |
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959 struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size, |
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960 DisplayState *ds, const char *core); |
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961 |
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962 /* omap2.c */ |
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963 struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size, |
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964 DisplayState *ds, const char *core); |
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965 |
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966 # if TARGET_PHYS_ADDR_BITS == 32 |
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967 # define OMAP_FMT_plx "%#08x" |
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968 # elif TARGET_PHYS_ADDR_BITS == 64 |
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969 # define OMAP_FMT_plx "%#08" PRIx64 |
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970 # else |
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971 # error TARGET_PHYS_ADDR_BITS undefined |
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972 # endif |
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973 |
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974 uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr); |
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975 void omap_badwidth_write8(void *opaque, target_phys_addr_t addr, |
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976 uint32_t value); |
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977 uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr); |
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978 void omap_badwidth_write16(void *opaque, target_phys_addr_t addr, |
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979 uint32_t value); |
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980 uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr); |
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981 void omap_badwidth_write32(void *opaque, target_phys_addr_t addr, |
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982 uint32_t value); |
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983 |
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984 void omap_mpu_wakeup(void *opaque, int irq, int req); |
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985 |
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986 # define OMAP_BAD_REG(paddr) \ |
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987 fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n", \ |
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988 __FUNCTION__, paddr) |
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989 # define OMAP_RO_REG(paddr) \ |
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990 fprintf(stderr, "%s: Read-only register " OMAP_FMT_plx "\n", \ |
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991 __FUNCTION__, paddr) |
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992 |
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993 /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area |
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994 (Board-specifc tags are not here) */ |
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995 #define OMAP_TAG_CLOCK 0x4f01 |
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996 #define OMAP_TAG_MMC 0x4f02 |
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997 #define OMAP_TAG_SERIAL_CONSOLE 0x4f03 |
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998 #define OMAP_TAG_USB 0x4f04 |
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999 #define OMAP_TAG_LCD 0x4f05 |
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1000 #define OMAP_TAG_GPIO_SWITCH 0x4f06 |
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1001 #define OMAP_TAG_UART 0x4f07 |
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1002 #define OMAP_TAG_FBMEM 0x4f08 |
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1003 #define OMAP_TAG_STI_CONSOLE 0x4f09 |
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1004 #define OMAP_TAG_CAMERA_SENSOR 0x4f0a |
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1005 #define OMAP_TAG_PARTITION 0x4f0b |
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1006 #define OMAP_TAG_TEA5761 0x4f10 |
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1007 #define OMAP_TAG_TMP105 0x4f11 |
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1008 #define OMAP_TAG_BOOT_REASON 0x4f80 |
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1009 #define OMAP_TAG_FLASH_PART_STR 0x4f81 |
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1010 #define OMAP_TAG_VERSION_STR 0x4f82 |
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1011 |
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1012 enum { |
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1013 OMAP_GPIOSW_TYPE_COVER = 0 << 4, |
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1014 OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4, |
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1015 OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4, |
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1016 }; |
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1017 |
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1018 #define OMAP_GPIOSW_INVERTED 0x0001 |
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1019 #define OMAP_GPIOSW_OUTPUT 0x0002 |
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1020 |
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1021 # define TCMI_VERBOSE 1 |
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1022 //# define MEM_VERBOSE 1 |
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1023 |
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1024 # ifdef TCMI_VERBOSE |
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1025 # define OMAP_8B_REG(paddr) \ |
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1026 fprintf(stderr, "%s: 8-bit register " OMAP_FMT_plx "\n", \ |
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1027 __FUNCTION__, paddr) |
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1028 # define OMAP_16B_REG(paddr) \ |
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1029 fprintf(stderr, "%s: 16-bit register " OMAP_FMT_plx "\n", \ |
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1030 __FUNCTION__, paddr) |
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1031 # define OMAP_32B_REG(paddr) \ |
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1032 fprintf(stderr, "%s: 32-bit register " OMAP_FMT_plx "\n", \ |
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1033 __FUNCTION__, paddr) |
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1034 # else |
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1035 # define OMAP_8B_REG(paddr) |
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1036 # define OMAP_16B_REG(paddr) |
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1037 # define OMAP_32B_REG(paddr) |
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1038 # endif |
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1039 |
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1040 # define OMAP_MPUI_REG_MASK 0x000007ff |
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1041 |
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1042 # ifdef MEM_VERBOSE |
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1043 struct io_fn { |
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1044 CPUReadMemoryFunc **mem_read; |
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1045 CPUWriteMemoryFunc **mem_write; |
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1046 void *opaque; |
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1047 int in; |
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1048 }; |
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1049 |
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1050 static uint32_t io_readb(void *opaque, target_phys_addr_t addr) |
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1051 { |
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1052 struct io_fn *s = opaque; |
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1053 uint32_t ret; |
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1054 |
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1055 s->in ++; |
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1056 ret = s->mem_read[0](s->opaque, addr); |
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1057 s->in --; |
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1058 if (!s->in) |
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1059 fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret); |
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1060 return ret; |
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1061 } |
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1062 static uint32_t io_readh(void *opaque, target_phys_addr_t addr) |
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1063 { |
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1064 struct io_fn *s = opaque; |
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1065 uint32_t ret; |
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1066 |
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1067 s->in ++; |
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1068 ret = s->mem_read[1](s->opaque, addr); |
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1069 s->in --; |
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1070 if (!s->in) |
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1071 fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret); |
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1072 return ret; |
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1073 } |
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1074 static uint32_t io_readw(void *opaque, target_phys_addr_t addr) |
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1075 { |
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1076 struct io_fn *s = opaque; |
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1077 uint32_t ret; |
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1078 |
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1079 s->in ++; |
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1080 ret = s->mem_read[2](s->opaque, addr); |
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1081 s->in --; |
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1082 if (!s->in) |
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1083 fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret); |
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1084 return ret; |
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1085 } |
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1086 static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) |
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1087 { |
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1088 struct io_fn *s = opaque; |
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1089 |
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1090 if (!s->in) |
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1091 fprintf(stderr, "%08x <--- %02x\n", (uint32_t) addr, value); |
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1092 s->in ++; |
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1093 s->mem_write[0](s->opaque, addr, value); |
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1094 s->in --; |
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1095 } |
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1096 static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value) |
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1097 { |
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1098 struct io_fn *s = opaque; |
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1099 |
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1100 if (!s->in) |
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1101 fprintf(stderr, "%08x <--- %04x\n", (uint32_t) addr, value); |
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1102 s->in ++; |
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1103 s->mem_write[1](s->opaque, addr, value); |
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1104 s->in --; |
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1105 } |
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1106 static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value) |
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1107 { |
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1108 struct io_fn *s = opaque; |
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1109 |
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1110 if (!s->in) |
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1111 fprintf(stderr, "%08x <--- %08x\n", (uint32_t) addr, value); |
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1112 s->in ++; |
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1113 s->mem_write[2](s->opaque, addr, value); |
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1114 s->in --; |
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1115 } |
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1116 |
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1117 static CPUReadMemoryFunc *io_readfn[] = { io_readb, io_readh, io_readw, }; |
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1118 static CPUWriteMemoryFunc *io_writefn[] = { io_writeb, io_writeh, io_writew, }; |
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1119 |
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1120 inline static int debug_register_io_memory(int io_index, |
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1121 CPUReadMemoryFunc **mem_read, CPUWriteMemoryFunc **mem_write, |
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1122 void *opaque) |
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1123 { |
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1124 struct io_fn *s = qemu_malloc(sizeof(struct io_fn)); |
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1125 |
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1126 s->mem_read = mem_read; |
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1127 s->mem_write = mem_write; |
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1128 s->opaque = opaque; |
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1129 s->in = 0; |
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1130 return cpu_register_io_memory(io_index, io_readfn, io_writefn, s); |
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1131 } |
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1132 # define cpu_register_io_memory debug_register_io_memory |
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1133 # endif |
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1134 |
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1135 /* Define when we want to reduce the number of IO regions registered. */ |
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1136 /*# define L4_MUX_HACK*/ |
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1137 |
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1138 # ifdef L4_MUX_HACK |
|
1139 # undef l4_register_io_memory |
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1140 int l4_register_io_memory(int io_index, CPUReadMemoryFunc **mem_read, |
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1141 CPUWriteMemoryFunc **mem_write, void *opaque); |
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1142 # endif |
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1143 |
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1144 #endif /* hw_omap_h */ |