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1 /* |
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2 * TI OMAP processors emulation. |
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3 * |
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4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> |
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5 * |
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6 * This program is free software; you can redistribute it and/or |
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7 * modify it under the terms of the GNU General Public License as |
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8 * published by the Free Software Foundation; either version 2 or |
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9 * (at your option) version 3 of the License. |
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10 * |
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11 * This program is distributed in the hope that it will be useful, |
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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14 * GNU General Public License for more details. |
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15 * |
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16 * You should have received a copy of the GNU General Public License |
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17 * along with this program; if not, write to the Free Software |
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18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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19 * MA 02111-1307 USA |
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20 */ |
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21 #include "hw.h" |
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22 #include "arm-misc.h" |
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23 #include "omap.h" |
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24 #include "sysemu.h" |
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25 #include "qemu-timer.h" |
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26 #include "qemu-char.h" |
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27 #include "soc_dma.h" |
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28 /* We use pc-style serial ports. */ |
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29 #include "pc.h" |
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30 |
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31 /* Should signal the TCMI/GPMC */ |
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32 uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr) |
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33 { |
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34 uint8_t ret; |
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35 |
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36 OMAP_8B_REG(addr); |
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37 cpu_physical_memory_read(addr, (void *) &ret, 1); |
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38 return ret; |
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39 } |
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40 |
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41 void omap_badwidth_write8(void *opaque, target_phys_addr_t addr, |
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42 uint32_t value) |
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43 { |
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44 uint8_t val8 = value; |
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45 |
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46 OMAP_8B_REG(addr); |
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47 cpu_physical_memory_write(addr, (void *) &val8, 1); |
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48 } |
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49 |
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50 uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr) |
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51 { |
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52 uint16_t ret; |
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53 |
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54 OMAP_16B_REG(addr); |
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55 cpu_physical_memory_read(addr, (void *) &ret, 2); |
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56 return ret; |
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57 } |
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58 |
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59 void omap_badwidth_write16(void *opaque, target_phys_addr_t addr, |
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60 uint32_t value) |
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61 { |
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62 uint16_t val16 = value; |
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63 |
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64 OMAP_16B_REG(addr); |
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65 cpu_physical_memory_write(addr, (void *) &val16, 2); |
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66 } |
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67 |
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68 uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr) |
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69 { |
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70 uint32_t ret; |
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71 |
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72 OMAP_32B_REG(addr); |
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73 cpu_physical_memory_read(addr, (void *) &ret, 4); |
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74 return ret; |
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75 } |
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76 |
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77 void omap_badwidth_write32(void *opaque, target_phys_addr_t addr, |
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78 uint32_t value) |
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79 { |
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80 OMAP_32B_REG(addr); |
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81 cpu_physical_memory_write(addr, (void *) &value, 4); |
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82 } |
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83 |
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84 /* Interrupt Handlers */ |
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85 struct omap_intr_handler_bank_s { |
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86 uint32_t irqs; |
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87 uint32_t inputs; |
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88 uint32_t mask; |
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89 uint32_t fiq; |
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90 uint32_t sens_edge; |
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91 uint32_t swi; |
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92 unsigned char priority[32]; |
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93 }; |
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94 |
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95 struct omap_intr_handler_s { |
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96 qemu_irq *pins; |
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97 qemu_irq parent_intr[2]; |
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98 unsigned char nbanks; |
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99 int level_only; |
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100 |
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101 /* state */ |
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102 uint32_t new_agr[2]; |
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103 int sir_intr[2]; |
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104 int autoidle; |
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105 uint32_t mask; |
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106 struct omap_intr_handler_bank_s bank[]; |
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107 }; |
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108 |
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109 static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq) |
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110 { |
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111 int i, j, sir_intr, p_intr, p, f; |
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112 uint32_t level; |
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113 sir_intr = 0; |
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114 p_intr = 255; |
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115 |
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116 /* Find the interrupt line with the highest dynamic priority. |
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117 * Note: 0 denotes the hightest priority. |
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118 * If all interrupts have the same priority, the default order is IRQ_N, |
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119 * IRQ_N-1,...,IRQ_0. */ |
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120 for (j = 0; j < s->nbanks; ++j) { |
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121 level = s->bank[j].irqs & ~s->bank[j].mask & |
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122 (is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq); |
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123 for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f, |
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124 level >>= f) { |
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125 p = s->bank[j].priority[i]; |
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126 if (p <= p_intr) { |
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127 p_intr = p; |
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128 sir_intr = 32 * j + i; |
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129 } |
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130 f = ffs(level >> 1); |
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131 } |
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132 } |
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133 s->sir_intr[is_fiq] = sir_intr; |
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134 } |
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135 |
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136 static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq) |
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137 { |
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138 int i; |
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139 uint32_t has_intr = 0; |
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140 |
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141 for (i = 0; i < s->nbanks; ++i) |
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142 has_intr |= s->bank[i].irqs & ~s->bank[i].mask & |
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143 (is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq); |
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144 |
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145 if (s->new_agr[is_fiq] & has_intr & s->mask) { |
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146 s->new_agr[is_fiq] = 0; |
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147 omap_inth_sir_update(s, is_fiq); |
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148 qemu_set_irq(s->parent_intr[is_fiq], 1); |
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149 } |
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150 } |
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151 |
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152 #define INT_FALLING_EDGE 0 |
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153 #define INT_LOW_LEVEL 1 |
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154 |
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155 static void omap_set_intr(void *opaque, int irq, int req) |
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156 { |
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157 struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque; |
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158 uint32_t rise; |
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159 |
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160 struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5]; |
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161 int n = irq & 31; |
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162 |
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163 if (req) { |
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164 rise = ~bank->irqs & (1 << n); |
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165 if (~bank->sens_edge & (1 << n)) |
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166 rise &= ~bank->inputs; |
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167 |
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168 bank->inputs |= (1 << n); |
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169 if (rise) { |
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170 bank->irqs |= rise; |
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171 omap_inth_update(ih, 0); |
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172 omap_inth_update(ih, 1); |
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173 } |
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174 } else { |
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175 rise = bank->sens_edge & bank->irqs & (1 << n); |
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176 bank->irqs &= ~rise; |
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177 bank->inputs &= ~(1 << n); |
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178 } |
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179 } |
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180 |
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181 /* Simplified version with no edge detection */ |
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182 static void omap_set_intr_noedge(void *opaque, int irq, int req) |
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183 { |
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184 struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque; |
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185 uint32_t rise; |
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186 |
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187 struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5]; |
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188 int n = irq & 31; |
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189 |
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190 if (req) { |
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191 rise = ~bank->inputs & (1 << n); |
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192 if (rise) { |
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193 bank->irqs |= bank->inputs |= rise; |
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194 omap_inth_update(ih, 0); |
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195 omap_inth_update(ih, 1); |
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196 } |
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197 } else |
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198 bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi; |
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199 } |
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200 |
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201 static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr) |
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202 { |
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203 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
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204 int i, offset = addr; |
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205 int bank_no = offset >> 8; |
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206 int line_no; |
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207 struct omap_intr_handler_bank_s *bank = &s->bank[bank_no]; |
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208 offset &= 0xff; |
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209 |
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210 switch (offset) { |
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211 case 0x00: /* ITR */ |
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212 return bank->irqs; |
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213 |
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214 case 0x04: /* MIR */ |
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215 return bank->mask; |
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216 |
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217 case 0x10: /* SIR_IRQ_CODE */ |
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218 case 0x14: /* SIR_FIQ_CODE */ |
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219 if (bank_no != 0) |
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220 break; |
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221 line_no = s->sir_intr[(offset - 0x10) >> 2]; |
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222 bank = &s->bank[line_no >> 5]; |
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223 i = line_no & 31; |
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224 if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE) |
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225 bank->irqs &= ~(1 << i); |
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226 return line_no; |
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227 |
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228 case 0x18: /* CONTROL_REG */ |
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229 if (bank_no != 0) |
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230 break; |
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231 return 0; |
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232 |
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233 case 0x1c: /* ILR0 */ |
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234 case 0x20: /* ILR1 */ |
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235 case 0x24: /* ILR2 */ |
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236 case 0x28: /* ILR3 */ |
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237 case 0x2c: /* ILR4 */ |
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238 case 0x30: /* ILR5 */ |
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239 case 0x34: /* ILR6 */ |
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240 case 0x38: /* ILR7 */ |
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241 case 0x3c: /* ILR8 */ |
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242 case 0x40: /* ILR9 */ |
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243 case 0x44: /* ILR10 */ |
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244 case 0x48: /* ILR11 */ |
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245 case 0x4c: /* ILR12 */ |
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246 case 0x50: /* ILR13 */ |
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247 case 0x54: /* ILR14 */ |
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248 case 0x58: /* ILR15 */ |
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249 case 0x5c: /* ILR16 */ |
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250 case 0x60: /* ILR17 */ |
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251 case 0x64: /* ILR18 */ |
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252 case 0x68: /* ILR19 */ |
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253 case 0x6c: /* ILR20 */ |
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254 case 0x70: /* ILR21 */ |
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255 case 0x74: /* ILR22 */ |
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256 case 0x78: /* ILR23 */ |
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257 case 0x7c: /* ILR24 */ |
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258 case 0x80: /* ILR25 */ |
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259 case 0x84: /* ILR26 */ |
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260 case 0x88: /* ILR27 */ |
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261 case 0x8c: /* ILR28 */ |
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262 case 0x90: /* ILR29 */ |
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263 case 0x94: /* ILR30 */ |
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264 case 0x98: /* ILR31 */ |
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265 i = (offset - 0x1c) >> 2; |
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266 return (bank->priority[i] << 2) | |
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267 (((bank->sens_edge >> i) & 1) << 1) | |
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268 ((bank->fiq >> i) & 1); |
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269 |
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270 case 0x9c: /* ISR */ |
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271 return 0x00000000; |
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272 |
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273 } |
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274 OMAP_BAD_REG(addr); |
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275 return 0; |
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276 } |
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277 |
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278 static void omap_inth_write(void *opaque, target_phys_addr_t addr, |
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279 uint32_t value) |
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280 { |
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281 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
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282 int i, offset = addr; |
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283 int bank_no = offset >> 8; |
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284 struct omap_intr_handler_bank_s *bank = &s->bank[bank_no]; |
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285 offset &= 0xff; |
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286 |
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287 switch (offset) { |
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288 case 0x00: /* ITR */ |
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289 /* Important: ignore the clearing if the IRQ is level-triggered and |
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290 the input bit is 1 */ |
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291 bank->irqs &= value | (bank->inputs & bank->sens_edge); |
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292 return; |
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293 |
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294 case 0x04: /* MIR */ |
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295 bank->mask = value; |
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296 omap_inth_update(s, 0); |
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297 omap_inth_update(s, 1); |
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298 return; |
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299 |
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300 case 0x10: /* SIR_IRQ_CODE */ |
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301 case 0x14: /* SIR_FIQ_CODE */ |
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302 OMAP_RO_REG(addr); |
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303 break; |
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304 |
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305 case 0x18: /* CONTROL_REG */ |
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306 if (bank_no != 0) |
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307 break; |
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308 if (value & 2) { |
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309 qemu_set_irq(s->parent_intr[1], 0); |
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310 s->new_agr[1] = ~0; |
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311 omap_inth_update(s, 1); |
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312 } |
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313 if (value & 1) { |
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314 qemu_set_irq(s->parent_intr[0], 0); |
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315 s->new_agr[0] = ~0; |
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316 omap_inth_update(s, 0); |
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317 } |
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318 return; |
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319 |
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320 case 0x1c: /* ILR0 */ |
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321 case 0x20: /* ILR1 */ |
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322 case 0x24: /* ILR2 */ |
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323 case 0x28: /* ILR3 */ |
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324 case 0x2c: /* ILR4 */ |
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325 case 0x30: /* ILR5 */ |
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326 case 0x34: /* ILR6 */ |
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327 case 0x38: /* ILR7 */ |
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328 case 0x3c: /* ILR8 */ |
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329 case 0x40: /* ILR9 */ |
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330 case 0x44: /* ILR10 */ |
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331 case 0x48: /* ILR11 */ |
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332 case 0x4c: /* ILR12 */ |
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333 case 0x50: /* ILR13 */ |
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334 case 0x54: /* ILR14 */ |
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335 case 0x58: /* ILR15 */ |
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336 case 0x5c: /* ILR16 */ |
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337 case 0x60: /* ILR17 */ |
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338 case 0x64: /* ILR18 */ |
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339 case 0x68: /* ILR19 */ |
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340 case 0x6c: /* ILR20 */ |
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341 case 0x70: /* ILR21 */ |
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342 case 0x74: /* ILR22 */ |
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343 case 0x78: /* ILR23 */ |
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344 case 0x7c: /* ILR24 */ |
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345 case 0x80: /* ILR25 */ |
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346 case 0x84: /* ILR26 */ |
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347 case 0x88: /* ILR27 */ |
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348 case 0x8c: /* ILR28 */ |
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349 case 0x90: /* ILR29 */ |
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350 case 0x94: /* ILR30 */ |
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351 case 0x98: /* ILR31 */ |
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352 i = (offset - 0x1c) >> 2; |
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353 bank->priority[i] = (value >> 2) & 0x1f; |
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354 bank->sens_edge &= ~(1 << i); |
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355 bank->sens_edge |= ((value >> 1) & 1) << i; |
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356 bank->fiq &= ~(1 << i); |
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357 bank->fiq |= (value & 1) << i; |
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358 return; |
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359 |
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360 case 0x9c: /* ISR */ |
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361 for (i = 0; i < 32; i ++) |
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362 if (value & (1 << i)) { |
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363 omap_set_intr(s, 32 * bank_no + i, 1); |
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364 return; |
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365 } |
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366 return; |
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367 } |
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368 OMAP_BAD_REG(addr); |
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369 } |
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370 |
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371 static CPUReadMemoryFunc *omap_inth_readfn[] = { |
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372 omap_badwidth_read32, |
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373 omap_badwidth_read32, |
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374 omap_inth_read, |
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375 }; |
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376 |
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377 static CPUWriteMemoryFunc *omap_inth_writefn[] = { |
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378 omap_inth_write, |
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379 omap_inth_write, |
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380 omap_inth_write, |
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381 }; |
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382 |
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383 void omap_inth_reset(struct omap_intr_handler_s *s) |
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384 { |
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385 int i; |
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386 |
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387 for (i = 0; i < s->nbanks; ++i){ |
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388 s->bank[i].irqs = 0x00000000; |
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389 s->bank[i].mask = 0xffffffff; |
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390 s->bank[i].sens_edge = 0x00000000; |
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391 s->bank[i].fiq = 0x00000000; |
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392 s->bank[i].inputs = 0x00000000; |
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393 s->bank[i].swi = 0x00000000; |
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394 memset(s->bank[i].priority, 0, sizeof(s->bank[i].priority)); |
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395 |
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396 if (s->level_only) |
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397 s->bank[i].sens_edge = 0xffffffff; |
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398 } |
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399 |
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400 s->new_agr[0] = ~0; |
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401 s->new_agr[1] = ~0; |
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402 s->sir_intr[0] = 0; |
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403 s->sir_intr[1] = 0; |
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404 s->autoidle = 0; |
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405 s->mask = ~0; |
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406 |
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407 qemu_set_irq(s->parent_intr[0], 0); |
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408 qemu_set_irq(s->parent_intr[1], 0); |
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409 } |
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410 |
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411 struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base, |
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412 unsigned long size, unsigned char nbanks, qemu_irq **pins, |
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413 qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk) |
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414 { |
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415 int iomemtype; |
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416 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) |
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417 qemu_mallocz(sizeof(struct omap_intr_handler_s) + |
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418 sizeof(struct omap_intr_handler_bank_s) * nbanks); |
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419 |
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420 s->parent_intr[0] = parent_irq; |
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421 s->parent_intr[1] = parent_fiq; |
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422 s->nbanks = nbanks; |
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423 s->pins = qemu_allocate_irqs(omap_set_intr, s, nbanks * 32); |
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424 if (pins) |
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425 *pins = s->pins; |
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426 |
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427 omap_inth_reset(s); |
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428 |
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429 iomemtype = cpu_register_io_memory(0, omap_inth_readfn, |
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430 omap_inth_writefn, s); |
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431 cpu_register_physical_memory(base, size, iomemtype); |
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432 |
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433 return s; |
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434 } |
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435 |
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436 static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr) |
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437 { |
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438 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
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439 int offset = addr; |
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440 int bank_no, line_no; |
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441 struct omap_intr_handler_bank_s *bank = 0; |
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442 |
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443 if ((offset & 0xf80) == 0x80) { |
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444 bank_no = (offset & 0x60) >> 5; |
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445 if (bank_no < s->nbanks) { |
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446 offset &= ~0x60; |
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447 bank = &s->bank[bank_no]; |
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448 } |
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449 } |
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450 |
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451 switch (offset) { |
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452 case 0x00: /* INTC_REVISION */ |
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453 return 0x21; |
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454 |
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455 case 0x10: /* INTC_SYSCONFIG */ |
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456 return (s->autoidle >> 2) & 1; |
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457 |
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458 case 0x14: /* INTC_SYSSTATUS */ |
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459 return 1; /* RESETDONE */ |
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460 |
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461 case 0x40: /* INTC_SIR_IRQ */ |
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462 return s->sir_intr[0]; |
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463 |
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464 case 0x44: /* INTC_SIR_FIQ */ |
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465 return s->sir_intr[1]; |
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466 |
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467 case 0x48: /* INTC_CONTROL */ |
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468 return (!s->mask) << 2; /* GLOBALMASK */ |
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469 |
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470 case 0x4c: /* INTC_PROTECTION */ |
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471 return 0; |
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472 |
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473 case 0x50: /* INTC_IDLE */ |
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474 return s->autoidle & 3; |
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475 |
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476 /* Per-bank registers */ |
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477 case 0x80: /* INTC_ITR */ |
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478 return bank->inputs; |
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479 |
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480 case 0x84: /* INTC_MIR */ |
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481 return bank->mask; |
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482 |
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483 case 0x88: /* INTC_MIR_CLEAR */ |
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484 case 0x8c: /* INTC_MIR_SET */ |
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485 return 0; |
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486 |
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487 case 0x90: /* INTC_ISR_SET */ |
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488 return bank->swi; |
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489 |
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490 case 0x94: /* INTC_ISR_CLEAR */ |
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491 return 0; |
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492 |
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493 case 0x98: /* INTC_PENDING_IRQ */ |
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494 return bank->irqs & ~bank->mask & ~bank->fiq; |
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495 |
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496 case 0x9c: /* INTC_PENDING_FIQ */ |
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497 return bank->irqs & ~bank->mask & bank->fiq; |
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498 |
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499 /* Per-line registers */ |
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500 case 0x100 ... 0x300: /* INTC_ILR */ |
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501 bank_no = (offset - 0x100) >> 7; |
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502 if (bank_no > s->nbanks) |
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503 break; |
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504 bank = &s->bank[bank_no]; |
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505 line_no = (offset & 0x7f) >> 2; |
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506 return (bank->priority[line_no] << 2) | |
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507 ((bank->fiq >> line_no) & 1); |
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508 } |
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509 OMAP_BAD_REG(addr); |
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510 return 0; |
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511 } |
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512 |
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513 static void omap2_inth_write(void *opaque, target_phys_addr_t addr, |
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514 uint32_t value) |
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515 { |
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516 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque; |
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517 int offset = addr; |
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518 int bank_no, line_no; |
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519 struct omap_intr_handler_bank_s *bank = 0; |
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520 |
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521 if ((offset & 0xf80) == 0x80) { |
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522 bank_no = (offset & 0x60) >> 5; |
|
523 if (bank_no < s->nbanks) { |
|
524 offset &= ~0x60; |
|
525 bank = &s->bank[bank_no]; |
|
526 } |
|
527 } |
|
528 |
|
529 switch (offset) { |
|
530 case 0x10: /* INTC_SYSCONFIG */ |
|
531 s->autoidle &= 4; |
|
532 s->autoidle |= (value & 1) << 2; |
|
533 if (value & 2) /* SOFTRESET */ |
|
534 omap_inth_reset(s); |
|
535 return; |
|
536 |
|
537 case 0x48: /* INTC_CONTROL */ |
|
538 s->mask = (value & 4) ? 0 : ~0; /* GLOBALMASK */ |
|
539 if (value & 2) { /* NEWFIQAGR */ |
|
540 qemu_set_irq(s->parent_intr[1], 0); |
|
541 s->new_agr[1] = ~0; |
|
542 omap_inth_update(s, 1); |
|
543 } |
|
544 if (value & 1) { /* NEWIRQAGR */ |
|
545 qemu_set_irq(s->parent_intr[0], 0); |
|
546 s->new_agr[0] = ~0; |
|
547 omap_inth_update(s, 0); |
|
548 } |
|
549 return; |
|
550 |
|
551 case 0x4c: /* INTC_PROTECTION */ |
|
552 /* TODO: Make a bitmap (or sizeof(char)map) of access privileges |
|
553 * for every register, see Chapter 3 and 4 for privileged mode. */ |
|
554 if (value & 1) |
|
555 fprintf(stderr, "%s: protection mode enable attempt\n", |
|
556 __FUNCTION__); |
|
557 return; |
|
558 |
|
559 case 0x50: /* INTC_IDLE */ |
|
560 s->autoidle &= ~3; |
|
561 s->autoidle |= value & 3; |
|
562 return; |
|
563 |
|
564 /* Per-bank registers */ |
|
565 case 0x84: /* INTC_MIR */ |
|
566 bank->mask = value; |
|
567 omap_inth_update(s, 0); |
|
568 omap_inth_update(s, 1); |
|
569 return; |
|
570 |
|
571 case 0x88: /* INTC_MIR_CLEAR */ |
|
572 bank->mask &= ~value; |
|
573 omap_inth_update(s, 0); |
|
574 omap_inth_update(s, 1); |
|
575 return; |
|
576 |
|
577 case 0x8c: /* INTC_MIR_SET */ |
|
578 bank->mask |= value; |
|
579 return; |
|
580 |
|
581 case 0x90: /* INTC_ISR_SET */ |
|
582 bank->irqs |= bank->swi |= value; |
|
583 omap_inth_update(s, 0); |
|
584 omap_inth_update(s, 1); |
|
585 return; |
|
586 |
|
587 case 0x94: /* INTC_ISR_CLEAR */ |
|
588 bank->swi &= ~value; |
|
589 bank->irqs = bank->swi & bank->inputs; |
|
590 return; |
|
591 |
|
592 /* Per-line registers */ |
|
593 case 0x100 ... 0x300: /* INTC_ILR */ |
|
594 bank_no = (offset - 0x100) >> 7; |
|
595 if (bank_no > s->nbanks) |
|
596 break; |
|
597 bank = &s->bank[bank_no]; |
|
598 line_no = (offset & 0x7f) >> 2; |
|
599 bank->priority[line_no] = (value >> 2) & 0x3f; |
|
600 bank->fiq &= ~(1 << line_no); |
|
601 bank->fiq |= (value & 1) << line_no; |
|
602 return; |
|
603 |
|
604 case 0x00: /* INTC_REVISION */ |
|
605 case 0x14: /* INTC_SYSSTATUS */ |
|
606 case 0x40: /* INTC_SIR_IRQ */ |
|
607 case 0x44: /* INTC_SIR_FIQ */ |
|
608 case 0x80: /* INTC_ITR */ |
|
609 case 0x98: /* INTC_PENDING_IRQ */ |
|
610 case 0x9c: /* INTC_PENDING_FIQ */ |
|
611 OMAP_RO_REG(addr); |
|
612 return; |
|
613 } |
|
614 OMAP_BAD_REG(addr); |
|
615 } |
|
616 |
|
617 static CPUReadMemoryFunc *omap2_inth_readfn[] = { |
|
618 omap_badwidth_read32, |
|
619 omap_badwidth_read32, |
|
620 omap2_inth_read, |
|
621 }; |
|
622 |
|
623 static CPUWriteMemoryFunc *omap2_inth_writefn[] = { |
|
624 omap2_inth_write, |
|
625 omap2_inth_write, |
|
626 omap2_inth_write, |
|
627 }; |
|
628 |
|
629 struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base, |
|
630 int size, int nbanks, qemu_irq **pins, |
|
631 qemu_irq parent_irq, qemu_irq parent_fiq, |
|
632 omap_clk fclk, omap_clk iclk) |
|
633 { |
|
634 int iomemtype; |
|
635 struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) |
|
636 qemu_mallocz(sizeof(struct omap_intr_handler_s) + |
|
637 sizeof(struct omap_intr_handler_bank_s) * nbanks); |
|
638 |
|
639 s->parent_intr[0] = parent_irq; |
|
640 s->parent_intr[1] = parent_fiq; |
|
641 s->nbanks = nbanks; |
|
642 s->level_only = 1; |
|
643 s->pins = qemu_allocate_irqs(omap_set_intr_noedge, s, nbanks * 32); |
|
644 if (pins) |
|
645 *pins = s->pins; |
|
646 |
|
647 omap_inth_reset(s); |
|
648 |
|
649 iomemtype = cpu_register_io_memory(0, omap2_inth_readfn, |
|
650 omap2_inth_writefn, s); |
|
651 cpu_register_physical_memory(base, size, iomemtype); |
|
652 |
|
653 return s; |
|
654 } |
|
655 |
|
656 /* MPU OS timers */ |
|
657 struct omap_mpu_timer_s { |
|
658 qemu_irq irq; |
|
659 omap_clk clk; |
|
660 uint32_t val; |
|
661 int64_t time; |
|
662 QEMUTimer *timer; |
|
663 QEMUBH *tick; |
|
664 int64_t rate; |
|
665 int it_ena; |
|
666 |
|
667 int enable; |
|
668 int ptv; |
|
669 int ar; |
|
670 int st; |
|
671 uint32_t reset_val; |
|
672 }; |
|
673 |
|
674 static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer) |
|
675 { |
|
676 uint64_t distance = qemu_get_clock(vm_clock) - timer->time; |
|
677 |
|
678 if (timer->st && timer->enable && timer->rate) |
|
679 return timer->val - muldiv64(distance >> (timer->ptv + 1), |
|
680 timer->rate, ticks_per_sec); |
|
681 else |
|
682 return timer->val; |
|
683 } |
|
684 |
|
685 static inline void omap_timer_sync(struct omap_mpu_timer_s *timer) |
|
686 { |
|
687 timer->val = omap_timer_read(timer); |
|
688 timer->time = qemu_get_clock(vm_clock); |
|
689 } |
|
690 |
|
691 static inline void omap_timer_update(struct omap_mpu_timer_s *timer) |
|
692 { |
|
693 int64_t expires; |
|
694 |
|
695 if (timer->enable && timer->st && timer->rate) { |
|
696 timer->val = timer->reset_val; /* Should skip this on clk enable */ |
|
697 expires = muldiv64((uint64_t) timer->val << (timer->ptv + 1), |
|
698 ticks_per_sec, timer->rate); |
|
699 |
|
700 /* If timer expiry would be sooner than in about 1 ms and |
|
701 * auto-reload isn't set, then fire immediately. This is a hack |
|
702 * to make systems like PalmOS run in acceptable time. PalmOS |
|
703 * sets the interval to a very low value and polls the status bit |
|
704 * in a busy loop when it wants to sleep just a couple of CPU |
|
705 * ticks. */ |
|
706 if (expires > (ticks_per_sec >> 10) || timer->ar) |
|
707 qemu_mod_timer(timer->timer, timer->time + expires); |
|
708 else |
|
709 qemu_bh_schedule(timer->tick); |
|
710 } else |
|
711 qemu_del_timer(timer->timer); |
|
712 } |
|
713 |
|
714 static void omap_timer_fire(void *opaque) |
|
715 { |
|
716 struct omap_mpu_timer_s *timer = opaque; |
|
717 |
|
718 if (!timer->ar) { |
|
719 timer->val = 0; |
|
720 timer->st = 0; |
|
721 } |
|
722 |
|
723 if (timer->it_ena) |
|
724 /* Edge-triggered irq */ |
|
725 qemu_irq_pulse(timer->irq); |
|
726 } |
|
727 |
|
728 static void omap_timer_tick(void *opaque) |
|
729 { |
|
730 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; |
|
731 |
|
732 omap_timer_sync(timer); |
|
733 omap_timer_fire(timer); |
|
734 omap_timer_update(timer); |
|
735 } |
|
736 |
|
737 static void omap_timer_clk_update(void *opaque, int line, int on) |
|
738 { |
|
739 struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque; |
|
740 |
|
741 omap_timer_sync(timer); |
|
742 timer->rate = on ? omap_clk_getrate(timer->clk) : 0; |
|
743 omap_timer_update(timer); |
|
744 } |
|
745 |
|
746 static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer) |
|
747 { |
|
748 omap_clk_adduser(timer->clk, |
|
749 qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]); |
|
750 timer->rate = omap_clk_getrate(timer->clk); |
|
751 } |
|
752 |
|
753 static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr) |
|
754 { |
|
755 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; |
|
756 |
|
757 switch (addr) { |
|
758 case 0x00: /* CNTL_TIMER */ |
|
759 return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st; |
|
760 |
|
761 case 0x04: /* LOAD_TIM */ |
|
762 break; |
|
763 |
|
764 case 0x08: /* READ_TIM */ |
|
765 return omap_timer_read(s); |
|
766 } |
|
767 |
|
768 OMAP_BAD_REG(addr); |
|
769 return 0; |
|
770 } |
|
771 |
|
772 static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr, |
|
773 uint32_t value) |
|
774 { |
|
775 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque; |
|
776 |
|
777 switch (addr) { |
|
778 case 0x00: /* CNTL_TIMER */ |
|
779 omap_timer_sync(s); |
|
780 s->enable = (value >> 5) & 1; |
|
781 s->ptv = (value >> 2) & 7; |
|
782 s->ar = (value >> 1) & 1; |
|
783 s->st = value & 1; |
|
784 omap_timer_update(s); |
|
785 return; |
|
786 |
|
787 case 0x04: /* LOAD_TIM */ |
|
788 s->reset_val = value; |
|
789 return; |
|
790 |
|
791 case 0x08: /* READ_TIM */ |
|
792 OMAP_RO_REG(addr); |
|
793 break; |
|
794 |
|
795 default: |
|
796 OMAP_BAD_REG(addr); |
|
797 } |
|
798 } |
|
799 |
|
800 static CPUReadMemoryFunc *omap_mpu_timer_readfn[] = { |
|
801 omap_badwidth_read32, |
|
802 omap_badwidth_read32, |
|
803 omap_mpu_timer_read, |
|
804 }; |
|
805 |
|
806 static CPUWriteMemoryFunc *omap_mpu_timer_writefn[] = { |
|
807 omap_badwidth_write32, |
|
808 omap_badwidth_write32, |
|
809 omap_mpu_timer_write, |
|
810 }; |
|
811 |
|
812 static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s) |
|
813 { |
|
814 qemu_del_timer(s->timer); |
|
815 s->enable = 0; |
|
816 s->reset_val = 31337; |
|
817 s->val = 0; |
|
818 s->ptv = 0; |
|
819 s->ar = 0; |
|
820 s->st = 0; |
|
821 s->it_ena = 1; |
|
822 } |
|
823 |
|
824 struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base, |
|
825 qemu_irq irq, omap_clk clk) |
|
826 { |
|
827 int iomemtype; |
|
828 struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) |
|
829 qemu_mallocz(sizeof(struct omap_mpu_timer_s)); |
|
830 |
|
831 s->irq = irq; |
|
832 s->clk = clk; |
|
833 s->timer = qemu_new_timer(vm_clock, omap_timer_tick, s); |
|
834 s->tick = qemu_bh_new(omap_timer_fire, s); |
|
835 omap_mpu_timer_reset(s); |
|
836 omap_timer_clk_setup(s); |
|
837 |
|
838 iomemtype = cpu_register_io_memory(0, omap_mpu_timer_readfn, |
|
839 omap_mpu_timer_writefn, s); |
|
840 cpu_register_physical_memory(base, 0x100, iomemtype); |
|
841 |
|
842 return s; |
|
843 } |
|
844 |
|
845 /* Watchdog timer */ |
|
846 struct omap_watchdog_timer_s { |
|
847 struct omap_mpu_timer_s timer; |
|
848 uint8_t last_wr; |
|
849 int mode; |
|
850 int free; |
|
851 int reset; |
|
852 }; |
|
853 |
|
854 static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr) |
|
855 { |
|
856 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; |
|
857 |
|
858 switch (addr) { |
|
859 case 0x00: /* CNTL_TIMER */ |
|
860 return (s->timer.ptv << 9) | (s->timer.ar << 8) | |
|
861 (s->timer.st << 7) | (s->free << 1); |
|
862 |
|
863 case 0x04: /* READ_TIMER */ |
|
864 return omap_timer_read(&s->timer); |
|
865 |
|
866 case 0x08: /* TIMER_MODE */ |
|
867 return s->mode << 15; |
|
868 } |
|
869 |
|
870 OMAP_BAD_REG(addr); |
|
871 return 0; |
|
872 } |
|
873 |
|
874 static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr, |
|
875 uint32_t value) |
|
876 { |
|
877 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque; |
|
878 |
|
879 switch (addr) { |
|
880 case 0x00: /* CNTL_TIMER */ |
|
881 omap_timer_sync(&s->timer); |
|
882 s->timer.ptv = (value >> 9) & 7; |
|
883 s->timer.ar = (value >> 8) & 1; |
|
884 s->timer.st = (value >> 7) & 1; |
|
885 s->free = (value >> 1) & 1; |
|
886 omap_timer_update(&s->timer); |
|
887 break; |
|
888 |
|
889 case 0x04: /* LOAD_TIMER */ |
|
890 s->timer.reset_val = value & 0xffff; |
|
891 break; |
|
892 |
|
893 case 0x08: /* TIMER_MODE */ |
|
894 if (!s->mode && ((value >> 15) & 1)) |
|
895 omap_clk_get(s->timer.clk); |
|
896 s->mode |= (value >> 15) & 1; |
|
897 if (s->last_wr == 0xf5) { |
|
898 if ((value & 0xff) == 0xa0) { |
|
899 if (s->mode) { |
|
900 s->mode = 0; |
|
901 omap_clk_put(s->timer.clk); |
|
902 } |
|
903 } else { |
|
904 /* XXX: on T|E hardware somehow this has no effect, |
|
905 * on Zire 71 it works as specified. */ |
|
906 s->reset = 1; |
|
907 qemu_system_reset_request(); |
|
908 } |
|
909 } |
|
910 s->last_wr = value & 0xff; |
|
911 break; |
|
912 |
|
913 default: |
|
914 OMAP_BAD_REG(addr); |
|
915 } |
|
916 } |
|
917 |
|
918 static CPUReadMemoryFunc *omap_wd_timer_readfn[] = { |
|
919 omap_badwidth_read16, |
|
920 omap_wd_timer_read, |
|
921 omap_badwidth_read16, |
|
922 }; |
|
923 |
|
924 static CPUWriteMemoryFunc *omap_wd_timer_writefn[] = { |
|
925 omap_badwidth_write16, |
|
926 omap_wd_timer_write, |
|
927 omap_badwidth_write16, |
|
928 }; |
|
929 |
|
930 static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s) |
|
931 { |
|
932 qemu_del_timer(s->timer.timer); |
|
933 if (!s->mode) |
|
934 omap_clk_get(s->timer.clk); |
|
935 s->mode = 1; |
|
936 s->free = 1; |
|
937 s->reset = 0; |
|
938 s->timer.enable = 1; |
|
939 s->timer.it_ena = 1; |
|
940 s->timer.reset_val = 0xffff; |
|
941 s->timer.val = 0; |
|
942 s->timer.st = 0; |
|
943 s->timer.ptv = 0; |
|
944 s->timer.ar = 0; |
|
945 omap_timer_update(&s->timer); |
|
946 } |
|
947 |
|
948 struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base, |
|
949 qemu_irq irq, omap_clk clk) |
|
950 { |
|
951 int iomemtype; |
|
952 struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) |
|
953 qemu_mallocz(sizeof(struct omap_watchdog_timer_s)); |
|
954 |
|
955 s->timer.irq = irq; |
|
956 s->timer.clk = clk; |
|
957 s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer); |
|
958 omap_wd_timer_reset(s); |
|
959 omap_timer_clk_setup(&s->timer); |
|
960 |
|
961 iomemtype = cpu_register_io_memory(0, omap_wd_timer_readfn, |
|
962 omap_wd_timer_writefn, s); |
|
963 cpu_register_physical_memory(base, 0x100, iomemtype); |
|
964 |
|
965 return s; |
|
966 } |
|
967 |
|
968 /* 32-kHz timer */ |
|
969 struct omap_32khz_timer_s { |
|
970 struct omap_mpu_timer_s timer; |
|
971 }; |
|
972 |
|
973 static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr) |
|
974 { |
|
975 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; |
|
976 int offset = addr & OMAP_MPUI_REG_MASK; |
|
977 |
|
978 switch (offset) { |
|
979 case 0x00: /* TVR */ |
|
980 return s->timer.reset_val; |
|
981 |
|
982 case 0x04: /* TCR */ |
|
983 return omap_timer_read(&s->timer); |
|
984 |
|
985 case 0x08: /* CR */ |
|
986 return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st; |
|
987 |
|
988 default: |
|
989 break; |
|
990 } |
|
991 OMAP_BAD_REG(addr); |
|
992 return 0; |
|
993 } |
|
994 |
|
995 static void omap_os_timer_write(void *opaque, target_phys_addr_t addr, |
|
996 uint32_t value) |
|
997 { |
|
998 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque; |
|
999 int offset = addr & OMAP_MPUI_REG_MASK; |
|
1000 |
|
1001 switch (offset) { |
|
1002 case 0x00: /* TVR */ |
|
1003 s->timer.reset_val = value & 0x00ffffff; |
|
1004 break; |
|
1005 |
|
1006 case 0x04: /* TCR */ |
|
1007 OMAP_RO_REG(addr); |
|
1008 break; |
|
1009 |
|
1010 case 0x08: /* CR */ |
|
1011 s->timer.ar = (value >> 3) & 1; |
|
1012 s->timer.it_ena = (value >> 2) & 1; |
|
1013 if (s->timer.st != (value & 1) || (value & 2)) { |
|
1014 omap_timer_sync(&s->timer); |
|
1015 s->timer.enable = value & 1; |
|
1016 s->timer.st = value & 1; |
|
1017 omap_timer_update(&s->timer); |
|
1018 } |
|
1019 break; |
|
1020 |
|
1021 default: |
|
1022 OMAP_BAD_REG(addr); |
|
1023 } |
|
1024 } |
|
1025 |
|
1026 static CPUReadMemoryFunc *omap_os_timer_readfn[] = { |
|
1027 omap_badwidth_read32, |
|
1028 omap_badwidth_read32, |
|
1029 omap_os_timer_read, |
|
1030 }; |
|
1031 |
|
1032 static CPUWriteMemoryFunc *omap_os_timer_writefn[] = { |
|
1033 omap_badwidth_write32, |
|
1034 omap_badwidth_write32, |
|
1035 omap_os_timer_write, |
|
1036 }; |
|
1037 |
|
1038 static void omap_os_timer_reset(struct omap_32khz_timer_s *s) |
|
1039 { |
|
1040 qemu_del_timer(s->timer.timer); |
|
1041 s->timer.enable = 0; |
|
1042 s->timer.it_ena = 0; |
|
1043 s->timer.reset_val = 0x00ffffff; |
|
1044 s->timer.val = 0; |
|
1045 s->timer.st = 0; |
|
1046 s->timer.ptv = 0; |
|
1047 s->timer.ar = 1; |
|
1048 } |
|
1049 |
|
1050 struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base, |
|
1051 qemu_irq irq, omap_clk clk) |
|
1052 { |
|
1053 int iomemtype; |
|
1054 struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) |
|
1055 qemu_mallocz(sizeof(struct omap_32khz_timer_s)); |
|
1056 |
|
1057 s->timer.irq = irq; |
|
1058 s->timer.clk = clk; |
|
1059 s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer); |
|
1060 omap_os_timer_reset(s); |
|
1061 omap_timer_clk_setup(&s->timer); |
|
1062 |
|
1063 iomemtype = cpu_register_io_memory(0, omap_os_timer_readfn, |
|
1064 omap_os_timer_writefn, s); |
|
1065 cpu_register_physical_memory(base, 0x800, iomemtype); |
|
1066 |
|
1067 return s; |
|
1068 } |
|
1069 |
|
1070 /* Ultra Low-Power Device Module */ |
|
1071 static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr) |
|
1072 { |
|
1073 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
|
1074 uint16_t ret; |
|
1075 |
|
1076 switch (addr) { |
|
1077 case 0x14: /* IT_STATUS */ |
|
1078 ret = s->ulpd_pm_regs[addr >> 2]; |
|
1079 s->ulpd_pm_regs[addr >> 2] = 0; |
|
1080 qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]); |
|
1081 return ret; |
|
1082 |
|
1083 case 0x18: /* Reserved */ |
|
1084 case 0x1c: /* Reserved */ |
|
1085 case 0x20: /* Reserved */ |
|
1086 case 0x28: /* Reserved */ |
|
1087 case 0x2c: /* Reserved */ |
|
1088 OMAP_BAD_REG(addr); |
|
1089 case 0x00: /* COUNTER_32_LSB */ |
|
1090 case 0x04: /* COUNTER_32_MSB */ |
|
1091 case 0x08: /* COUNTER_HIGH_FREQ_LSB */ |
|
1092 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ |
|
1093 case 0x10: /* GAUGING_CTRL */ |
|
1094 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ |
|
1095 case 0x30: /* CLOCK_CTRL */ |
|
1096 case 0x34: /* SOFT_REQ */ |
|
1097 case 0x38: /* COUNTER_32_FIQ */ |
|
1098 case 0x3c: /* DPLL_CTRL */ |
|
1099 case 0x40: /* STATUS_REQ */ |
|
1100 /* XXX: check clk::usecount state for every clock */ |
|
1101 case 0x48: /* LOCL_TIME */ |
|
1102 case 0x4c: /* APLL_CTRL */ |
|
1103 case 0x50: /* POWER_CTRL */ |
|
1104 return s->ulpd_pm_regs[addr >> 2]; |
|
1105 } |
|
1106 |
|
1107 OMAP_BAD_REG(addr); |
|
1108 return 0; |
|
1109 } |
|
1110 |
|
1111 static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s, |
|
1112 uint16_t diff, uint16_t value) |
|
1113 { |
|
1114 if (diff & (1 << 4)) /* USB_MCLK_EN */ |
|
1115 omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1); |
|
1116 if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */ |
|
1117 omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1); |
|
1118 } |
|
1119 |
|
1120 static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s, |
|
1121 uint16_t diff, uint16_t value) |
|
1122 { |
|
1123 if (diff & (1 << 0)) /* SOFT_DPLL_REQ */ |
|
1124 omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1); |
|
1125 if (diff & (1 << 1)) /* SOFT_COM_REQ */ |
|
1126 omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1); |
|
1127 if (diff & (1 << 2)) /* SOFT_SDW_REQ */ |
|
1128 omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1); |
|
1129 if (diff & (1 << 3)) /* SOFT_USB_REQ */ |
|
1130 omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1); |
|
1131 } |
|
1132 |
|
1133 static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr, |
|
1134 uint32_t value) |
|
1135 { |
|
1136 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
|
1137 int64_t now, ticks; |
|
1138 int div, mult; |
|
1139 static const int bypass_div[4] = { 1, 2, 4, 4 }; |
|
1140 uint16_t diff; |
|
1141 |
|
1142 switch (addr) { |
|
1143 case 0x00: /* COUNTER_32_LSB */ |
|
1144 case 0x04: /* COUNTER_32_MSB */ |
|
1145 case 0x08: /* COUNTER_HIGH_FREQ_LSB */ |
|
1146 case 0x0c: /* COUNTER_HIGH_FREQ_MSB */ |
|
1147 case 0x14: /* IT_STATUS */ |
|
1148 case 0x40: /* STATUS_REQ */ |
|
1149 OMAP_RO_REG(addr); |
|
1150 break; |
|
1151 |
|
1152 case 0x10: /* GAUGING_CTRL */ |
|
1153 /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */ |
|
1154 if ((s->ulpd_pm_regs[addr >> 2] ^ value) & 1) { |
|
1155 now = qemu_get_clock(vm_clock); |
|
1156 |
|
1157 if (value & 1) |
|
1158 s->ulpd_gauge_start = now; |
|
1159 else { |
|
1160 now -= s->ulpd_gauge_start; |
|
1161 |
|
1162 /* 32-kHz ticks */ |
|
1163 ticks = muldiv64(now, 32768, ticks_per_sec); |
|
1164 s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff; |
|
1165 s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff; |
|
1166 if (ticks >> 32) /* OVERFLOW_32K */ |
|
1167 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2; |
|
1168 |
|
1169 /* High frequency ticks */ |
|
1170 ticks = muldiv64(now, 12000000, ticks_per_sec); |
|
1171 s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff; |
|
1172 s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff; |
|
1173 if (ticks >> 32) /* OVERFLOW_HI_FREQ */ |
|
1174 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1; |
|
1175 |
|
1176 s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */ |
|
1177 qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]); |
|
1178 } |
|
1179 } |
|
1180 s->ulpd_pm_regs[addr >> 2] = value; |
|
1181 break; |
|
1182 |
|
1183 case 0x18: /* Reserved */ |
|
1184 case 0x1c: /* Reserved */ |
|
1185 case 0x20: /* Reserved */ |
|
1186 case 0x28: /* Reserved */ |
|
1187 case 0x2c: /* Reserved */ |
|
1188 OMAP_BAD_REG(addr); |
|
1189 case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */ |
|
1190 case 0x38: /* COUNTER_32_FIQ */ |
|
1191 case 0x48: /* LOCL_TIME */ |
|
1192 case 0x50: /* POWER_CTRL */ |
|
1193 s->ulpd_pm_regs[addr >> 2] = value; |
|
1194 break; |
|
1195 |
|
1196 case 0x30: /* CLOCK_CTRL */ |
|
1197 diff = s->ulpd_pm_regs[addr >> 2] ^ value; |
|
1198 s->ulpd_pm_regs[addr >> 2] = value & 0x3f; |
|
1199 omap_ulpd_clk_update(s, diff, value); |
|
1200 break; |
|
1201 |
|
1202 case 0x34: /* SOFT_REQ */ |
|
1203 diff = s->ulpd_pm_regs[addr >> 2] ^ value; |
|
1204 s->ulpd_pm_regs[addr >> 2] = value & 0x1f; |
|
1205 omap_ulpd_req_update(s, diff, value); |
|
1206 break; |
|
1207 |
|
1208 case 0x3c: /* DPLL_CTRL */ |
|
1209 /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is |
|
1210 * omitted altogether, probably a typo. */ |
|
1211 /* This register has identical semantics with DPLL(1:3) control |
|
1212 * registers, see omap_dpll_write() */ |
|
1213 diff = s->ulpd_pm_regs[addr >> 2] & value; |
|
1214 s->ulpd_pm_regs[addr >> 2] = value & 0x2fff; |
|
1215 if (diff & (0x3ff << 2)) { |
|
1216 if (value & (1 << 4)) { /* PLL_ENABLE */ |
|
1217 div = ((value >> 5) & 3) + 1; /* PLL_DIV */ |
|
1218 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ |
|
1219 } else { |
|
1220 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ |
|
1221 mult = 1; |
|
1222 } |
|
1223 omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult); |
|
1224 } |
|
1225 |
|
1226 /* Enter the desired mode. */ |
|
1227 s->ulpd_pm_regs[addr >> 2] = |
|
1228 (s->ulpd_pm_regs[addr >> 2] & 0xfffe) | |
|
1229 ((s->ulpd_pm_regs[addr >> 2] >> 4) & 1); |
|
1230 |
|
1231 /* Act as if the lock is restored. */ |
|
1232 s->ulpd_pm_regs[addr >> 2] |= 2; |
|
1233 break; |
|
1234 |
|
1235 case 0x4c: /* APLL_CTRL */ |
|
1236 diff = s->ulpd_pm_regs[addr >> 2] & value; |
|
1237 s->ulpd_pm_regs[addr >> 2] = value & 0xf; |
|
1238 if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */ |
|
1239 omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s, |
|
1240 (value & (1 << 0)) ? "apll" : "dpll4")); |
|
1241 break; |
|
1242 |
|
1243 default: |
|
1244 OMAP_BAD_REG(addr); |
|
1245 } |
|
1246 } |
|
1247 |
|
1248 static CPUReadMemoryFunc *omap_ulpd_pm_readfn[] = { |
|
1249 omap_badwidth_read16, |
|
1250 omap_ulpd_pm_read, |
|
1251 omap_badwidth_read16, |
|
1252 }; |
|
1253 |
|
1254 static CPUWriteMemoryFunc *omap_ulpd_pm_writefn[] = { |
|
1255 omap_badwidth_write16, |
|
1256 omap_ulpd_pm_write, |
|
1257 omap_badwidth_write16, |
|
1258 }; |
|
1259 |
|
1260 static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu) |
|
1261 { |
|
1262 mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001; |
|
1263 mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000; |
|
1264 mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001; |
|
1265 mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000; |
|
1266 mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000; |
|
1267 mpu->ulpd_pm_regs[0x18 >> 2] = 0x01; |
|
1268 mpu->ulpd_pm_regs[0x1c >> 2] = 0x01; |
|
1269 mpu->ulpd_pm_regs[0x20 >> 2] = 0x01; |
|
1270 mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff; |
|
1271 mpu->ulpd_pm_regs[0x28 >> 2] = 0x01; |
|
1272 mpu->ulpd_pm_regs[0x2c >> 2] = 0x01; |
|
1273 omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000); |
|
1274 mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000; |
|
1275 omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000); |
|
1276 mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000; |
|
1277 mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001; |
|
1278 mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211; |
|
1279 mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */ |
|
1280 mpu->ulpd_pm_regs[0x48 >> 2] = 0x960; |
|
1281 mpu->ulpd_pm_regs[0x4c >> 2] = 0x08; |
|
1282 mpu->ulpd_pm_regs[0x50 >> 2] = 0x08; |
|
1283 omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4); |
|
1284 omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4")); |
|
1285 } |
|
1286 |
|
1287 static void omap_ulpd_pm_init(target_phys_addr_t base, |
|
1288 struct omap_mpu_state_s *mpu) |
|
1289 { |
|
1290 int iomemtype = cpu_register_io_memory(0, omap_ulpd_pm_readfn, |
|
1291 omap_ulpd_pm_writefn, mpu); |
|
1292 |
|
1293 cpu_register_physical_memory(base, 0x800, iomemtype); |
|
1294 omap_ulpd_pm_reset(mpu); |
|
1295 } |
|
1296 |
|
1297 /* OMAP Pin Configuration */ |
|
1298 static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr) |
|
1299 { |
|
1300 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
|
1301 |
|
1302 switch (addr) { |
|
1303 case 0x00: /* FUNC_MUX_CTRL_0 */ |
|
1304 case 0x04: /* FUNC_MUX_CTRL_1 */ |
|
1305 case 0x08: /* FUNC_MUX_CTRL_2 */ |
|
1306 return s->func_mux_ctrl[addr >> 2]; |
|
1307 |
|
1308 case 0x0c: /* COMP_MODE_CTRL_0 */ |
|
1309 return s->comp_mode_ctrl[0]; |
|
1310 |
|
1311 case 0x10: /* FUNC_MUX_CTRL_3 */ |
|
1312 case 0x14: /* FUNC_MUX_CTRL_4 */ |
|
1313 case 0x18: /* FUNC_MUX_CTRL_5 */ |
|
1314 case 0x1c: /* FUNC_MUX_CTRL_6 */ |
|
1315 case 0x20: /* FUNC_MUX_CTRL_7 */ |
|
1316 case 0x24: /* FUNC_MUX_CTRL_8 */ |
|
1317 case 0x28: /* FUNC_MUX_CTRL_9 */ |
|
1318 case 0x2c: /* FUNC_MUX_CTRL_A */ |
|
1319 case 0x30: /* FUNC_MUX_CTRL_B */ |
|
1320 case 0x34: /* FUNC_MUX_CTRL_C */ |
|
1321 case 0x38: /* FUNC_MUX_CTRL_D */ |
|
1322 return s->func_mux_ctrl[(addr >> 2) - 1]; |
|
1323 |
|
1324 case 0x40: /* PULL_DWN_CTRL_0 */ |
|
1325 case 0x44: /* PULL_DWN_CTRL_1 */ |
|
1326 case 0x48: /* PULL_DWN_CTRL_2 */ |
|
1327 case 0x4c: /* PULL_DWN_CTRL_3 */ |
|
1328 return s->pull_dwn_ctrl[(addr & 0xf) >> 2]; |
|
1329 |
|
1330 case 0x50: /* GATE_INH_CTRL_0 */ |
|
1331 return s->gate_inh_ctrl[0]; |
|
1332 |
|
1333 case 0x60: /* VOLTAGE_CTRL_0 */ |
|
1334 return s->voltage_ctrl[0]; |
|
1335 |
|
1336 case 0x70: /* TEST_DBG_CTRL_0 */ |
|
1337 return s->test_dbg_ctrl[0]; |
|
1338 |
|
1339 case 0x80: /* MOD_CONF_CTRL_0 */ |
|
1340 return s->mod_conf_ctrl[0]; |
|
1341 } |
|
1342 |
|
1343 OMAP_BAD_REG(addr); |
|
1344 return 0; |
|
1345 } |
|
1346 |
|
1347 static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s, |
|
1348 uint32_t diff, uint32_t value) |
|
1349 { |
|
1350 if (s->compat1509) { |
|
1351 if (diff & (1 << 9)) /* BLUETOOTH */ |
|
1352 omap_clk_onoff(omap_findclk(s, "bt_mclk_out"), |
|
1353 (~value >> 9) & 1); |
|
1354 if (diff & (1 << 7)) /* USB.CLKO */ |
|
1355 omap_clk_onoff(omap_findclk(s, "usb.clko"), |
|
1356 (value >> 7) & 1); |
|
1357 } |
|
1358 } |
|
1359 |
|
1360 static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s, |
|
1361 uint32_t diff, uint32_t value) |
|
1362 { |
|
1363 if (s->compat1509) { |
|
1364 if (diff & (1 << 31)) /* MCBSP3_CLK_HIZ_DI */ |
|
1365 omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"), |
|
1366 (value >> 31) & 1); |
|
1367 if (diff & (1 << 1)) /* CLK32K */ |
|
1368 omap_clk_onoff(omap_findclk(s, "clk32k_out"), |
|
1369 (~value >> 1) & 1); |
|
1370 } |
|
1371 } |
|
1372 |
|
1373 static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s, |
|
1374 uint32_t diff, uint32_t value) |
|
1375 { |
|
1376 if (diff & (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */ |
|
1377 omap_clk_reparent(omap_findclk(s, "uart3_ck"), |
|
1378 omap_findclk(s, ((value >> 31) & 1) ? |
|
1379 "ck_48m" : "armper_ck")); |
|
1380 if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */ |
|
1381 omap_clk_reparent(omap_findclk(s, "uart2_ck"), |
|
1382 omap_findclk(s, ((value >> 30) & 1) ? |
|
1383 "ck_48m" : "armper_ck")); |
|
1384 if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */ |
|
1385 omap_clk_reparent(omap_findclk(s, "uart1_ck"), |
|
1386 omap_findclk(s, ((value >> 29) & 1) ? |
|
1387 "ck_48m" : "armper_ck")); |
|
1388 if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */ |
|
1389 omap_clk_reparent(omap_findclk(s, "mmc_ck"), |
|
1390 omap_findclk(s, ((value >> 23) & 1) ? |
|
1391 "ck_48m" : "armper_ck")); |
|
1392 if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */ |
|
1393 omap_clk_reparent(omap_findclk(s, "com_mclk_out"), |
|
1394 omap_findclk(s, ((value >> 12) & 1) ? |
|
1395 "ck_48m" : "armper_ck")); |
|
1396 if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */ |
|
1397 omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1); |
|
1398 } |
|
1399 |
|
1400 static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr, |
|
1401 uint32_t value) |
|
1402 { |
|
1403 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
|
1404 uint32_t diff; |
|
1405 |
|
1406 switch (addr) { |
|
1407 case 0x00: /* FUNC_MUX_CTRL_0 */ |
|
1408 diff = s->func_mux_ctrl[addr >> 2] ^ value; |
|
1409 s->func_mux_ctrl[addr >> 2] = value; |
|
1410 omap_pin_funcmux0_update(s, diff, value); |
|
1411 return; |
|
1412 |
|
1413 case 0x04: /* FUNC_MUX_CTRL_1 */ |
|
1414 diff = s->func_mux_ctrl[addr >> 2] ^ value; |
|
1415 s->func_mux_ctrl[addr >> 2] = value; |
|
1416 omap_pin_funcmux1_update(s, diff, value); |
|
1417 return; |
|
1418 |
|
1419 case 0x08: /* FUNC_MUX_CTRL_2 */ |
|
1420 s->func_mux_ctrl[addr >> 2] = value; |
|
1421 return; |
|
1422 |
|
1423 case 0x0c: /* COMP_MODE_CTRL_0 */ |
|
1424 s->comp_mode_ctrl[0] = value; |
|
1425 s->compat1509 = (value != 0x0000eaef); |
|
1426 omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]); |
|
1427 omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]); |
|
1428 return; |
|
1429 |
|
1430 case 0x10: /* FUNC_MUX_CTRL_3 */ |
|
1431 case 0x14: /* FUNC_MUX_CTRL_4 */ |
|
1432 case 0x18: /* FUNC_MUX_CTRL_5 */ |
|
1433 case 0x1c: /* FUNC_MUX_CTRL_6 */ |
|
1434 case 0x20: /* FUNC_MUX_CTRL_7 */ |
|
1435 case 0x24: /* FUNC_MUX_CTRL_8 */ |
|
1436 case 0x28: /* FUNC_MUX_CTRL_9 */ |
|
1437 case 0x2c: /* FUNC_MUX_CTRL_A */ |
|
1438 case 0x30: /* FUNC_MUX_CTRL_B */ |
|
1439 case 0x34: /* FUNC_MUX_CTRL_C */ |
|
1440 case 0x38: /* FUNC_MUX_CTRL_D */ |
|
1441 s->func_mux_ctrl[(addr >> 2) - 1] = value; |
|
1442 return; |
|
1443 |
|
1444 case 0x40: /* PULL_DWN_CTRL_0 */ |
|
1445 case 0x44: /* PULL_DWN_CTRL_1 */ |
|
1446 case 0x48: /* PULL_DWN_CTRL_2 */ |
|
1447 case 0x4c: /* PULL_DWN_CTRL_3 */ |
|
1448 s->pull_dwn_ctrl[(addr & 0xf) >> 2] = value; |
|
1449 return; |
|
1450 |
|
1451 case 0x50: /* GATE_INH_CTRL_0 */ |
|
1452 s->gate_inh_ctrl[0] = value; |
|
1453 return; |
|
1454 |
|
1455 case 0x60: /* VOLTAGE_CTRL_0 */ |
|
1456 s->voltage_ctrl[0] = value; |
|
1457 return; |
|
1458 |
|
1459 case 0x70: /* TEST_DBG_CTRL_0 */ |
|
1460 s->test_dbg_ctrl[0] = value; |
|
1461 return; |
|
1462 |
|
1463 case 0x80: /* MOD_CONF_CTRL_0 */ |
|
1464 diff = s->mod_conf_ctrl[0] ^ value; |
|
1465 s->mod_conf_ctrl[0] = value; |
|
1466 omap_pin_modconf1_update(s, diff, value); |
|
1467 return; |
|
1468 |
|
1469 default: |
|
1470 OMAP_BAD_REG(addr); |
|
1471 } |
|
1472 } |
|
1473 |
|
1474 static CPUReadMemoryFunc *omap_pin_cfg_readfn[] = { |
|
1475 omap_badwidth_read32, |
|
1476 omap_badwidth_read32, |
|
1477 omap_pin_cfg_read, |
|
1478 }; |
|
1479 |
|
1480 static CPUWriteMemoryFunc *omap_pin_cfg_writefn[] = { |
|
1481 omap_badwidth_write32, |
|
1482 omap_badwidth_write32, |
|
1483 omap_pin_cfg_write, |
|
1484 }; |
|
1485 |
|
1486 static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu) |
|
1487 { |
|
1488 /* Start in Compatibility Mode. */ |
|
1489 mpu->compat1509 = 1; |
|
1490 omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0); |
|
1491 omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0); |
|
1492 omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0); |
|
1493 memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl)); |
|
1494 memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl)); |
|
1495 memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl)); |
|
1496 memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl)); |
|
1497 memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl)); |
|
1498 memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl)); |
|
1499 memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl)); |
|
1500 } |
|
1501 |
|
1502 static void omap_pin_cfg_init(target_phys_addr_t base, |
|
1503 struct omap_mpu_state_s *mpu) |
|
1504 { |
|
1505 int iomemtype = cpu_register_io_memory(0, omap_pin_cfg_readfn, |
|
1506 omap_pin_cfg_writefn, mpu); |
|
1507 |
|
1508 cpu_register_physical_memory(base, 0x800, iomemtype); |
|
1509 omap_pin_cfg_reset(mpu); |
|
1510 } |
|
1511 |
|
1512 /* Device Identification, Die Identification */ |
|
1513 static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr) |
|
1514 { |
|
1515 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
|
1516 |
|
1517 switch (addr) { |
|
1518 case 0xfffe1800: /* DIE_ID_LSB */ |
|
1519 return 0xc9581f0e; |
|
1520 case 0xfffe1804: /* DIE_ID_MSB */ |
|
1521 return 0xa8858bfa; |
|
1522 |
|
1523 case 0xfffe2000: /* PRODUCT_ID_LSB */ |
|
1524 return 0x00aaaafc; |
|
1525 case 0xfffe2004: /* PRODUCT_ID_MSB */ |
|
1526 return 0xcafeb574; |
|
1527 |
|
1528 case 0xfffed400: /* JTAG_ID_LSB */ |
|
1529 switch (s->mpu_model) { |
|
1530 case omap310: |
|
1531 return 0x03310315; |
|
1532 case omap1510: |
|
1533 return 0x03310115; |
|
1534 default: |
|
1535 cpu_abort(cpu_single_env, "%s: bad mpu model\n", __FUNCTION__); |
|
1536 } |
|
1537 break; |
|
1538 |
|
1539 case 0xfffed404: /* JTAG_ID_MSB */ |
|
1540 switch (s->mpu_model) { |
|
1541 case omap310: |
|
1542 return 0xfb57402f; |
|
1543 case omap1510: |
|
1544 return 0xfb47002f; |
|
1545 default: |
|
1546 cpu_abort(cpu_single_env, "%s: bad mpu model\n", __FUNCTION__); |
|
1547 } |
|
1548 break; |
|
1549 } |
|
1550 |
|
1551 OMAP_BAD_REG(addr); |
|
1552 return 0; |
|
1553 } |
|
1554 |
|
1555 static void omap_id_write(void *opaque, target_phys_addr_t addr, |
|
1556 uint32_t value) |
|
1557 { |
|
1558 OMAP_BAD_REG(addr); |
|
1559 } |
|
1560 |
|
1561 static CPUReadMemoryFunc *omap_id_readfn[] = { |
|
1562 omap_badwidth_read32, |
|
1563 omap_badwidth_read32, |
|
1564 omap_id_read, |
|
1565 }; |
|
1566 |
|
1567 static CPUWriteMemoryFunc *omap_id_writefn[] = { |
|
1568 omap_badwidth_write32, |
|
1569 omap_badwidth_write32, |
|
1570 omap_id_write, |
|
1571 }; |
|
1572 |
|
1573 static void omap_id_init(struct omap_mpu_state_s *mpu) |
|
1574 { |
|
1575 int iomemtype = cpu_register_io_memory(0, omap_id_readfn, |
|
1576 omap_id_writefn, mpu); |
|
1577 cpu_register_physical_memory_offset(0xfffe1800, 0x800, iomemtype, 0xfffe1800); |
|
1578 cpu_register_physical_memory_offset(0xfffed400, 0x100, iomemtype, 0xfffed400); |
|
1579 if (!cpu_is_omap15xx(mpu)) |
|
1580 cpu_register_physical_memory_offset(0xfffe2000, 0x800, iomemtype, 0xfffe2000); |
|
1581 } |
|
1582 |
|
1583 /* MPUI Control (Dummy) */ |
|
1584 static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr) |
|
1585 { |
|
1586 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
|
1587 |
|
1588 switch (addr) { |
|
1589 case 0x00: /* CTRL */ |
|
1590 return s->mpui_ctrl; |
|
1591 case 0x04: /* DEBUG_ADDR */ |
|
1592 return 0x01ffffff; |
|
1593 case 0x08: /* DEBUG_DATA */ |
|
1594 return 0xffffffff; |
|
1595 case 0x0c: /* DEBUG_FLAG */ |
|
1596 return 0x00000800; |
|
1597 case 0x10: /* STATUS */ |
|
1598 return 0x00000000; |
|
1599 |
|
1600 /* Not in OMAP310 */ |
|
1601 case 0x14: /* DSP_STATUS */ |
|
1602 case 0x18: /* DSP_BOOT_CONFIG */ |
|
1603 return 0x00000000; |
|
1604 case 0x1c: /* DSP_MPUI_CONFIG */ |
|
1605 return 0x0000ffff; |
|
1606 } |
|
1607 |
|
1608 OMAP_BAD_REG(addr); |
|
1609 return 0; |
|
1610 } |
|
1611 |
|
1612 static void omap_mpui_write(void *opaque, target_phys_addr_t addr, |
|
1613 uint32_t value) |
|
1614 { |
|
1615 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
|
1616 |
|
1617 switch (addr) { |
|
1618 case 0x00: /* CTRL */ |
|
1619 s->mpui_ctrl = value & 0x007fffff; |
|
1620 break; |
|
1621 |
|
1622 case 0x04: /* DEBUG_ADDR */ |
|
1623 case 0x08: /* DEBUG_DATA */ |
|
1624 case 0x0c: /* DEBUG_FLAG */ |
|
1625 case 0x10: /* STATUS */ |
|
1626 /* Not in OMAP310 */ |
|
1627 case 0x14: /* DSP_STATUS */ |
|
1628 OMAP_RO_REG(addr); |
|
1629 case 0x18: /* DSP_BOOT_CONFIG */ |
|
1630 case 0x1c: /* DSP_MPUI_CONFIG */ |
|
1631 break; |
|
1632 |
|
1633 default: |
|
1634 OMAP_BAD_REG(addr); |
|
1635 } |
|
1636 } |
|
1637 |
|
1638 static CPUReadMemoryFunc *omap_mpui_readfn[] = { |
|
1639 omap_badwidth_read32, |
|
1640 omap_badwidth_read32, |
|
1641 omap_mpui_read, |
|
1642 }; |
|
1643 |
|
1644 static CPUWriteMemoryFunc *omap_mpui_writefn[] = { |
|
1645 omap_badwidth_write32, |
|
1646 omap_badwidth_write32, |
|
1647 omap_mpui_write, |
|
1648 }; |
|
1649 |
|
1650 static void omap_mpui_reset(struct omap_mpu_state_s *s) |
|
1651 { |
|
1652 s->mpui_ctrl = 0x0003ff1b; |
|
1653 } |
|
1654 |
|
1655 static void omap_mpui_init(target_phys_addr_t base, |
|
1656 struct omap_mpu_state_s *mpu) |
|
1657 { |
|
1658 int iomemtype = cpu_register_io_memory(0, omap_mpui_readfn, |
|
1659 omap_mpui_writefn, mpu); |
|
1660 |
|
1661 cpu_register_physical_memory(base, 0x100, iomemtype); |
|
1662 |
|
1663 omap_mpui_reset(mpu); |
|
1664 } |
|
1665 |
|
1666 /* TIPB Bridges */ |
|
1667 struct omap_tipb_bridge_s { |
|
1668 qemu_irq abort; |
|
1669 |
|
1670 int width_intr; |
|
1671 uint16_t control; |
|
1672 uint16_t alloc; |
|
1673 uint16_t buffer; |
|
1674 uint16_t enh_control; |
|
1675 }; |
|
1676 |
|
1677 static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr) |
|
1678 { |
|
1679 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; |
|
1680 |
|
1681 switch (addr) { |
|
1682 case 0x00: /* TIPB_CNTL */ |
|
1683 return s->control; |
|
1684 case 0x04: /* TIPB_BUS_ALLOC */ |
|
1685 return s->alloc; |
|
1686 case 0x08: /* MPU_TIPB_CNTL */ |
|
1687 return s->buffer; |
|
1688 case 0x0c: /* ENHANCED_TIPB_CNTL */ |
|
1689 return s->enh_control; |
|
1690 case 0x10: /* ADDRESS_DBG */ |
|
1691 case 0x14: /* DATA_DEBUG_LOW */ |
|
1692 case 0x18: /* DATA_DEBUG_HIGH */ |
|
1693 return 0xffff; |
|
1694 case 0x1c: /* DEBUG_CNTR_SIG */ |
|
1695 return 0x00f8; |
|
1696 } |
|
1697 |
|
1698 OMAP_BAD_REG(addr); |
|
1699 return 0; |
|
1700 } |
|
1701 |
|
1702 static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr, |
|
1703 uint32_t value) |
|
1704 { |
|
1705 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque; |
|
1706 |
|
1707 switch (addr) { |
|
1708 case 0x00: /* TIPB_CNTL */ |
|
1709 s->control = value & 0xffff; |
|
1710 break; |
|
1711 |
|
1712 case 0x04: /* TIPB_BUS_ALLOC */ |
|
1713 s->alloc = value & 0x003f; |
|
1714 break; |
|
1715 |
|
1716 case 0x08: /* MPU_TIPB_CNTL */ |
|
1717 s->buffer = value & 0x0003; |
|
1718 break; |
|
1719 |
|
1720 case 0x0c: /* ENHANCED_TIPB_CNTL */ |
|
1721 s->width_intr = !(value & 2); |
|
1722 s->enh_control = value & 0x000f; |
|
1723 break; |
|
1724 |
|
1725 case 0x10: /* ADDRESS_DBG */ |
|
1726 case 0x14: /* DATA_DEBUG_LOW */ |
|
1727 case 0x18: /* DATA_DEBUG_HIGH */ |
|
1728 case 0x1c: /* DEBUG_CNTR_SIG */ |
|
1729 OMAP_RO_REG(addr); |
|
1730 break; |
|
1731 |
|
1732 default: |
|
1733 OMAP_BAD_REG(addr); |
|
1734 } |
|
1735 } |
|
1736 |
|
1737 static CPUReadMemoryFunc *omap_tipb_bridge_readfn[] = { |
|
1738 omap_badwidth_read16, |
|
1739 omap_tipb_bridge_read, |
|
1740 omap_tipb_bridge_read, |
|
1741 }; |
|
1742 |
|
1743 static CPUWriteMemoryFunc *omap_tipb_bridge_writefn[] = { |
|
1744 omap_badwidth_write16, |
|
1745 omap_tipb_bridge_write, |
|
1746 omap_tipb_bridge_write, |
|
1747 }; |
|
1748 |
|
1749 static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s) |
|
1750 { |
|
1751 s->control = 0xffff; |
|
1752 s->alloc = 0x0009; |
|
1753 s->buffer = 0x0000; |
|
1754 s->enh_control = 0x000f; |
|
1755 } |
|
1756 |
|
1757 struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base, |
|
1758 qemu_irq abort_irq, omap_clk clk) |
|
1759 { |
|
1760 int iomemtype; |
|
1761 struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) |
|
1762 qemu_mallocz(sizeof(struct omap_tipb_bridge_s)); |
|
1763 |
|
1764 s->abort = abort_irq; |
|
1765 omap_tipb_bridge_reset(s); |
|
1766 |
|
1767 iomemtype = cpu_register_io_memory(0, omap_tipb_bridge_readfn, |
|
1768 omap_tipb_bridge_writefn, s); |
|
1769 cpu_register_physical_memory(base, 0x100, iomemtype); |
|
1770 |
|
1771 return s; |
|
1772 } |
|
1773 |
|
1774 /* Dummy Traffic Controller's Memory Interface */ |
|
1775 static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr) |
|
1776 { |
|
1777 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
|
1778 uint32_t ret; |
|
1779 |
|
1780 switch (addr) { |
|
1781 case 0x00: /* IMIF_PRIO */ |
|
1782 case 0x04: /* EMIFS_PRIO */ |
|
1783 case 0x08: /* EMIFF_PRIO */ |
|
1784 case 0x0c: /* EMIFS_CONFIG */ |
|
1785 case 0x10: /* EMIFS_CS0_CONFIG */ |
|
1786 case 0x14: /* EMIFS_CS1_CONFIG */ |
|
1787 case 0x18: /* EMIFS_CS2_CONFIG */ |
|
1788 case 0x1c: /* EMIFS_CS3_CONFIG */ |
|
1789 case 0x24: /* EMIFF_MRS */ |
|
1790 case 0x28: /* TIMEOUT1 */ |
|
1791 case 0x2c: /* TIMEOUT2 */ |
|
1792 case 0x30: /* TIMEOUT3 */ |
|
1793 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ |
|
1794 case 0x40: /* EMIFS_CFG_DYN_WAIT */ |
|
1795 return s->tcmi_regs[addr >> 2]; |
|
1796 |
|
1797 case 0x20: /* EMIFF_SDRAM_CONFIG */ |
|
1798 ret = s->tcmi_regs[addr >> 2]; |
|
1799 s->tcmi_regs[addr >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */ |
|
1800 /* XXX: We can try using the VGA_DIRTY flag for this */ |
|
1801 return ret; |
|
1802 } |
|
1803 |
|
1804 OMAP_BAD_REG(addr); |
|
1805 return 0; |
|
1806 } |
|
1807 |
|
1808 static void omap_tcmi_write(void *opaque, target_phys_addr_t addr, |
|
1809 uint32_t value) |
|
1810 { |
|
1811 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
|
1812 |
|
1813 switch (addr) { |
|
1814 case 0x00: /* IMIF_PRIO */ |
|
1815 case 0x04: /* EMIFS_PRIO */ |
|
1816 case 0x08: /* EMIFF_PRIO */ |
|
1817 case 0x10: /* EMIFS_CS0_CONFIG */ |
|
1818 case 0x14: /* EMIFS_CS1_CONFIG */ |
|
1819 case 0x18: /* EMIFS_CS2_CONFIG */ |
|
1820 case 0x1c: /* EMIFS_CS3_CONFIG */ |
|
1821 case 0x20: /* EMIFF_SDRAM_CONFIG */ |
|
1822 case 0x24: /* EMIFF_MRS */ |
|
1823 case 0x28: /* TIMEOUT1 */ |
|
1824 case 0x2c: /* TIMEOUT2 */ |
|
1825 case 0x30: /* TIMEOUT3 */ |
|
1826 case 0x3c: /* EMIFF_SDRAM_CONFIG_2 */ |
|
1827 case 0x40: /* EMIFS_CFG_DYN_WAIT */ |
|
1828 s->tcmi_regs[addr >> 2] = value; |
|
1829 break; |
|
1830 case 0x0c: /* EMIFS_CONFIG */ |
|
1831 s->tcmi_regs[addr >> 2] = (value & 0xf) | (1 << 4); |
|
1832 break; |
|
1833 |
|
1834 default: |
|
1835 OMAP_BAD_REG(addr); |
|
1836 } |
|
1837 } |
|
1838 |
|
1839 static CPUReadMemoryFunc *omap_tcmi_readfn[] = { |
|
1840 omap_badwidth_read32, |
|
1841 omap_badwidth_read32, |
|
1842 omap_tcmi_read, |
|
1843 }; |
|
1844 |
|
1845 static CPUWriteMemoryFunc *omap_tcmi_writefn[] = { |
|
1846 omap_badwidth_write32, |
|
1847 omap_badwidth_write32, |
|
1848 omap_tcmi_write, |
|
1849 }; |
|
1850 |
|
1851 static void omap_tcmi_reset(struct omap_mpu_state_s *mpu) |
|
1852 { |
|
1853 mpu->tcmi_regs[0x00 >> 2] = 0x00000000; |
|
1854 mpu->tcmi_regs[0x04 >> 2] = 0x00000000; |
|
1855 mpu->tcmi_regs[0x08 >> 2] = 0x00000000; |
|
1856 mpu->tcmi_regs[0x0c >> 2] = 0x00000010; |
|
1857 mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb; |
|
1858 mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb; |
|
1859 mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb; |
|
1860 mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb; |
|
1861 mpu->tcmi_regs[0x20 >> 2] = 0x00618800; |
|
1862 mpu->tcmi_regs[0x24 >> 2] = 0x00000037; |
|
1863 mpu->tcmi_regs[0x28 >> 2] = 0x00000000; |
|
1864 mpu->tcmi_regs[0x2c >> 2] = 0x00000000; |
|
1865 mpu->tcmi_regs[0x30 >> 2] = 0x00000000; |
|
1866 mpu->tcmi_regs[0x3c >> 2] = 0x00000003; |
|
1867 mpu->tcmi_regs[0x40 >> 2] = 0x00000000; |
|
1868 } |
|
1869 |
|
1870 static void omap_tcmi_init(target_phys_addr_t base, |
|
1871 struct omap_mpu_state_s *mpu) |
|
1872 { |
|
1873 int iomemtype = cpu_register_io_memory(0, omap_tcmi_readfn, |
|
1874 omap_tcmi_writefn, mpu); |
|
1875 |
|
1876 cpu_register_physical_memory(base, 0x100, iomemtype); |
|
1877 omap_tcmi_reset(mpu); |
|
1878 } |
|
1879 |
|
1880 /* Digital phase-locked loops control */ |
|
1881 static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr) |
|
1882 { |
|
1883 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; |
|
1884 |
|
1885 if (addr == 0x00) /* CTL_REG */ |
|
1886 return s->mode; |
|
1887 |
|
1888 OMAP_BAD_REG(addr); |
|
1889 return 0; |
|
1890 } |
|
1891 |
|
1892 static void omap_dpll_write(void *opaque, target_phys_addr_t addr, |
|
1893 uint32_t value) |
|
1894 { |
|
1895 struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque; |
|
1896 uint16_t diff; |
|
1897 static const int bypass_div[4] = { 1, 2, 4, 4 }; |
|
1898 int div, mult; |
|
1899 |
|
1900 if (addr == 0x00) { /* CTL_REG */ |
|
1901 /* See omap_ulpd_pm_write() too */ |
|
1902 diff = s->mode & value; |
|
1903 s->mode = value & 0x2fff; |
|
1904 if (diff & (0x3ff << 2)) { |
|
1905 if (value & (1 << 4)) { /* PLL_ENABLE */ |
|
1906 div = ((value >> 5) & 3) + 1; /* PLL_DIV */ |
|
1907 mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */ |
|
1908 } else { |
|
1909 div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */ |
|
1910 mult = 1; |
|
1911 } |
|
1912 omap_clk_setrate(s->dpll, div, mult); |
|
1913 } |
|
1914 |
|
1915 /* Enter the desired mode. */ |
|
1916 s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1); |
|
1917 |
|
1918 /* Act as if the lock is restored. */ |
|
1919 s->mode |= 2; |
|
1920 } else { |
|
1921 OMAP_BAD_REG(addr); |
|
1922 } |
|
1923 } |
|
1924 |
|
1925 static CPUReadMemoryFunc *omap_dpll_readfn[] = { |
|
1926 omap_badwidth_read16, |
|
1927 omap_dpll_read, |
|
1928 omap_badwidth_read16, |
|
1929 }; |
|
1930 |
|
1931 static CPUWriteMemoryFunc *omap_dpll_writefn[] = { |
|
1932 omap_badwidth_write16, |
|
1933 omap_dpll_write, |
|
1934 omap_badwidth_write16, |
|
1935 }; |
|
1936 |
|
1937 static void omap_dpll_reset(struct dpll_ctl_s *s) |
|
1938 { |
|
1939 s->mode = 0x2002; |
|
1940 omap_clk_setrate(s->dpll, 1, 1); |
|
1941 } |
|
1942 |
|
1943 static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base, |
|
1944 omap_clk clk) |
|
1945 { |
|
1946 int iomemtype = cpu_register_io_memory(0, omap_dpll_readfn, |
|
1947 omap_dpll_writefn, s); |
|
1948 |
|
1949 s->dpll = clk; |
|
1950 omap_dpll_reset(s); |
|
1951 |
|
1952 cpu_register_physical_memory(base, 0x100, iomemtype); |
|
1953 } |
|
1954 |
|
1955 /* UARTs */ |
|
1956 struct omap_uart_s { |
|
1957 target_phys_addr_t base; |
|
1958 SerialState *serial; /* TODO */ |
|
1959 struct omap_target_agent_s *ta; |
|
1960 omap_clk fclk; |
|
1961 qemu_irq irq; |
|
1962 |
|
1963 uint8_t eblr; |
|
1964 uint8_t syscontrol; |
|
1965 uint8_t wkup; |
|
1966 uint8_t cfps; |
|
1967 uint8_t mdr[2]; |
|
1968 uint8_t scr; |
|
1969 uint8_t clksel; |
|
1970 }; |
|
1971 |
|
1972 void omap_uart_reset(struct omap_uart_s *s) |
|
1973 { |
|
1974 s->eblr = 0x00; |
|
1975 s->syscontrol = 0; |
|
1976 s->wkup = 0x3f; |
|
1977 s->cfps = 0x69; |
|
1978 s->clksel = 0; |
|
1979 } |
|
1980 |
|
1981 struct omap_uart_s *omap_uart_init(target_phys_addr_t base, |
|
1982 qemu_irq irq, omap_clk fclk, omap_clk iclk, |
|
1983 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr) |
|
1984 { |
|
1985 struct omap_uart_s *s = (struct omap_uart_s *) |
|
1986 qemu_mallocz(sizeof(struct omap_uart_s)); |
|
1987 |
|
1988 s->base = base; |
|
1989 s->fclk = fclk; |
|
1990 s->irq = irq; |
|
1991 s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16, |
|
1992 chr ?: qemu_chr_open("null", "null"), 1); |
|
1993 |
|
1994 return s; |
|
1995 } |
|
1996 |
|
1997 static uint32_t omap_uart_read(void *opaque, target_phys_addr_t addr) |
|
1998 { |
|
1999 struct omap_uart_s *s = (struct omap_uart_s *) opaque; |
|
2000 |
|
2001 addr &= 0xff; |
|
2002 switch (addr) { |
|
2003 case 0x20: /* MDR1 */ |
|
2004 return s->mdr[0]; |
|
2005 case 0x24: /* MDR2 */ |
|
2006 return s->mdr[1]; |
|
2007 case 0x40: /* SCR */ |
|
2008 return s->scr; |
|
2009 case 0x44: /* SSR */ |
|
2010 return 0x0; |
|
2011 case 0x48: /* EBLR (OMAP2) */ |
|
2012 return s->eblr; |
|
2013 case 0x4C: /* OSC_12M_SEL (OMAP1) */ |
|
2014 return s->clksel; |
|
2015 case 0x50: /* MVR */ |
|
2016 return 0x30; |
|
2017 case 0x54: /* SYSC (OMAP2) */ |
|
2018 return s->syscontrol; |
|
2019 case 0x58: /* SYSS (OMAP2) */ |
|
2020 return 1; |
|
2021 case 0x5c: /* WER (OMAP2) */ |
|
2022 return s->wkup; |
|
2023 case 0x60: /* CFPS (OMAP2) */ |
|
2024 return s->cfps; |
|
2025 } |
|
2026 |
|
2027 OMAP_BAD_REG(addr); |
|
2028 return 0; |
|
2029 } |
|
2030 |
|
2031 static void omap_uart_write(void *opaque, target_phys_addr_t addr, |
|
2032 uint32_t value) |
|
2033 { |
|
2034 struct omap_uart_s *s = (struct omap_uart_s *) opaque; |
|
2035 |
|
2036 addr &= 0xff; |
|
2037 switch (addr) { |
|
2038 case 0x20: /* MDR1 */ |
|
2039 s->mdr[0] = value & 0x7f; |
|
2040 break; |
|
2041 case 0x24: /* MDR2 */ |
|
2042 s->mdr[1] = value & 0xff; |
|
2043 break; |
|
2044 case 0x40: /* SCR */ |
|
2045 s->scr = value & 0xff; |
|
2046 break; |
|
2047 case 0x48: /* EBLR (OMAP2) */ |
|
2048 s->eblr = value & 0xff; |
|
2049 break; |
|
2050 case 0x4C: /* OSC_12M_SEL (OMAP1) */ |
|
2051 s->clksel = value & 1; |
|
2052 break; |
|
2053 case 0x44: /* SSR */ |
|
2054 case 0x50: /* MVR */ |
|
2055 case 0x58: /* SYSS (OMAP2) */ |
|
2056 OMAP_RO_REG(addr); |
|
2057 break; |
|
2058 case 0x54: /* SYSC (OMAP2) */ |
|
2059 s->syscontrol = value & 0x1d; |
|
2060 if (value & 2) |
|
2061 omap_uart_reset(s); |
|
2062 break; |
|
2063 case 0x5c: /* WER (OMAP2) */ |
|
2064 s->wkup = value & 0x7f; |
|
2065 break; |
|
2066 case 0x60: /* CFPS (OMAP2) */ |
|
2067 s->cfps = value & 0xff; |
|
2068 break; |
|
2069 default: |
|
2070 OMAP_BAD_REG(addr); |
|
2071 } |
|
2072 } |
|
2073 |
|
2074 static CPUReadMemoryFunc *omap_uart_readfn[] = { |
|
2075 omap_uart_read, |
|
2076 omap_uart_read, |
|
2077 omap_badwidth_read8, |
|
2078 }; |
|
2079 |
|
2080 static CPUWriteMemoryFunc *omap_uart_writefn[] = { |
|
2081 omap_uart_write, |
|
2082 omap_uart_write, |
|
2083 omap_badwidth_write8, |
|
2084 }; |
|
2085 |
|
2086 struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta, |
|
2087 qemu_irq irq, omap_clk fclk, omap_clk iclk, |
|
2088 qemu_irq txdma, qemu_irq rxdma, CharDriverState *chr) |
|
2089 { |
|
2090 target_phys_addr_t base = omap_l4_attach(ta, 0, 0); |
|
2091 struct omap_uart_s *s = omap_uart_init(base, irq, |
|
2092 fclk, iclk, txdma, rxdma, chr); |
|
2093 int iomemtype = cpu_register_io_memory(0, omap_uart_readfn, |
|
2094 omap_uart_writefn, s); |
|
2095 |
|
2096 s->ta = ta; |
|
2097 |
|
2098 cpu_register_physical_memory(base + 0x20, 0x100, iomemtype); |
|
2099 |
|
2100 return s; |
|
2101 } |
|
2102 |
|
2103 void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr) |
|
2104 { |
|
2105 /* TODO: Should reuse or destroy current s->serial */ |
|
2106 s->serial = serial_mm_init(s->base, 2, s->irq, |
|
2107 omap_clk_getrate(s->fclk) / 16, |
|
2108 chr ?: qemu_chr_open("null", "null"), 1); |
|
2109 } |
|
2110 |
|
2111 /* MPU Clock/Reset/Power Mode Control */ |
|
2112 static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr) |
|
2113 { |
|
2114 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
|
2115 |
|
2116 switch (addr) { |
|
2117 case 0x00: /* ARM_CKCTL */ |
|
2118 return s->clkm.arm_ckctl; |
|
2119 |
|
2120 case 0x04: /* ARM_IDLECT1 */ |
|
2121 return s->clkm.arm_idlect1; |
|
2122 |
|
2123 case 0x08: /* ARM_IDLECT2 */ |
|
2124 return s->clkm.arm_idlect2; |
|
2125 |
|
2126 case 0x0c: /* ARM_EWUPCT */ |
|
2127 return s->clkm.arm_ewupct; |
|
2128 |
|
2129 case 0x10: /* ARM_RSTCT1 */ |
|
2130 return s->clkm.arm_rstct1; |
|
2131 |
|
2132 case 0x14: /* ARM_RSTCT2 */ |
|
2133 return s->clkm.arm_rstct2; |
|
2134 |
|
2135 case 0x18: /* ARM_SYSST */ |
|
2136 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start; |
|
2137 |
|
2138 case 0x1c: /* ARM_CKOUT1 */ |
|
2139 return s->clkm.arm_ckout1; |
|
2140 |
|
2141 case 0x20: /* ARM_CKOUT2 */ |
|
2142 break; |
|
2143 } |
|
2144 |
|
2145 OMAP_BAD_REG(addr); |
|
2146 return 0; |
|
2147 } |
|
2148 |
|
2149 static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s, |
|
2150 uint16_t diff, uint16_t value) |
|
2151 { |
|
2152 omap_clk clk; |
|
2153 |
|
2154 if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */ |
|
2155 if (value & (1 << 14)) |
|
2156 /* Reserved */; |
|
2157 else { |
|
2158 clk = omap_findclk(s, "arminth_ck"); |
|
2159 omap_clk_reparent(clk, omap_findclk(s, "tc_ck")); |
|
2160 } |
|
2161 } |
|
2162 if (diff & (1 << 12)) { /* ARM_TIMXO */ |
|
2163 clk = omap_findclk(s, "armtim_ck"); |
|
2164 if (value & (1 << 12)) |
|
2165 omap_clk_reparent(clk, omap_findclk(s, "clkin")); |
|
2166 else |
|
2167 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1")); |
|
2168 } |
|
2169 /* XXX: en_dspck */ |
|
2170 if (diff & (3 << 10)) { /* DSPMMUDIV */ |
|
2171 clk = omap_findclk(s, "dspmmu_ck"); |
|
2172 omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1); |
|
2173 } |
|
2174 if (diff & (3 << 8)) { /* TCDIV */ |
|
2175 clk = omap_findclk(s, "tc_ck"); |
|
2176 omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1); |
|
2177 } |
|
2178 if (diff & (3 << 6)) { /* DSPDIV */ |
|
2179 clk = omap_findclk(s, "dsp_ck"); |
|
2180 omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1); |
|
2181 } |
|
2182 if (diff & (3 << 4)) { /* ARMDIV */ |
|
2183 clk = omap_findclk(s, "arm_ck"); |
|
2184 omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1); |
|
2185 } |
|
2186 if (diff & (3 << 2)) { /* LCDDIV */ |
|
2187 clk = omap_findclk(s, "lcd_ck"); |
|
2188 omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1); |
|
2189 } |
|
2190 if (diff & (3 << 0)) { /* PERDIV */ |
|
2191 clk = omap_findclk(s, "armper_ck"); |
|
2192 omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1); |
|
2193 } |
|
2194 } |
|
2195 |
|
2196 static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s, |
|
2197 uint16_t diff, uint16_t value) |
|
2198 { |
|
2199 omap_clk clk; |
|
2200 |
|
2201 if (value & (1 << 11)) /* SETARM_IDLE */ |
|
2202 cpu_interrupt(s->env, CPU_INTERRUPT_HALT); |
|
2203 if (!(value & (1 << 10))) /* WKUP_MODE */ |
|
2204 qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */ |
|
2205 |
|
2206 #define SET_CANIDLE(clock, bit) \ |
|
2207 if (diff & (1 << bit)) { \ |
|
2208 clk = omap_findclk(s, clock); \ |
|
2209 omap_clk_canidle(clk, (value >> bit) & 1); \ |
|
2210 } |
|
2211 SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */ |
|
2212 SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */ |
|
2213 SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */ |
|
2214 SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */ |
|
2215 SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */ |
|
2216 SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */ |
|
2217 SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */ |
|
2218 SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */ |
|
2219 SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */ |
|
2220 SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */ |
|
2221 SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */ |
|
2222 SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */ |
|
2223 SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */ |
|
2224 SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */ |
|
2225 } |
|
2226 |
|
2227 static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s, |
|
2228 uint16_t diff, uint16_t value) |
|
2229 { |
|
2230 omap_clk clk; |
|
2231 |
|
2232 #define SET_ONOFF(clock, bit) \ |
|
2233 if (diff & (1 << bit)) { \ |
|
2234 clk = omap_findclk(s, clock); \ |
|
2235 omap_clk_onoff(clk, (value >> bit) & 1); \ |
|
2236 } |
|
2237 SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */ |
|
2238 SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */ |
|
2239 SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */ |
|
2240 SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */ |
|
2241 SET_ONOFF("lb_ck", 4) /* EN_LBCK */ |
|
2242 SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */ |
|
2243 SET_ONOFF("mpui_ck", 6) /* EN_APICK */ |
|
2244 SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */ |
|
2245 SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */ |
|
2246 SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */ |
|
2247 SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */ |
|
2248 } |
|
2249 |
|
2250 static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s, |
|
2251 uint16_t diff, uint16_t value) |
|
2252 { |
|
2253 omap_clk clk; |
|
2254 |
|
2255 if (diff & (3 << 4)) { /* TCLKOUT */ |
|
2256 clk = omap_findclk(s, "tclk_out"); |
|
2257 switch ((value >> 4) & 3) { |
|
2258 case 1: |
|
2259 omap_clk_reparent(clk, omap_findclk(s, "ck_gen3")); |
|
2260 omap_clk_onoff(clk, 1); |
|
2261 break; |
|
2262 case 2: |
|
2263 omap_clk_reparent(clk, omap_findclk(s, "tc_ck")); |
|
2264 omap_clk_onoff(clk, 1); |
|
2265 break; |
|
2266 default: |
|
2267 omap_clk_onoff(clk, 0); |
|
2268 } |
|
2269 } |
|
2270 if (diff & (3 << 2)) { /* DCLKOUT */ |
|
2271 clk = omap_findclk(s, "dclk_out"); |
|
2272 switch ((value >> 2) & 3) { |
|
2273 case 0: |
|
2274 omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck")); |
|
2275 break; |
|
2276 case 1: |
|
2277 omap_clk_reparent(clk, omap_findclk(s, "ck_gen2")); |
|
2278 break; |
|
2279 case 2: |
|
2280 omap_clk_reparent(clk, omap_findclk(s, "dsp_ck")); |
|
2281 break; |
|
2282 case 3: |
|
2283 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14")); |
|
2284 break; |
|
2285 } |
|
2286 } |
|
2287 if (diff & (3 << 0)) { /* ACLKOUT */ |
|
2288 clk = omap_findclk(s, "aclk_out"); |
|
2289 switch ((value >> 0) & 3) { |
|
2290 case 1: |
|
2291 omap_clk_reparent(clk, omap_findclk(s, "ck_gen1")); |
|
2292 omap_clk_onoff(clk, 1); |
|
2293 break; |
|
2294 case 2: |
|
2295 omap_clk_reparent(clk, omap_findclk(s, "arm_ck")); |
|
2296 omap_clk_onoff(clk, 1); |
|
2297 break; |
|
2298 case 3: |
|
2299 omap_clk_reparent(clk, omap_findclk(s, "ck_ref14")); |
|
2300 omap_clk_onoff(clk, 1); |
|
2301 break; |
|
2302 default: |
|
2303 omap_clk_onoff(clk, 0); |
|
2304 } |
|
2305 } |
|
2306 } |
|
2307 |
|
2308 static void omap_clkm_write(void *opaque, target_phys_addr_t addr, |
|
2309 uint32_t value) |
|
2310 { |
|
2311 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
|
2312 uint16_t diff; |
|
2313 omap_clk clk; |
|
2314 static const char *clkschemename[8] = { |
|
2315 "fully synchronous", "fully asynchronous", "synchronous scalable", |
|
2316 "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4", |
|
2317 }; |
|
2318 |
|
2319 switch (addr) { |
|
2320 case 0x00: /* ARM_CKCTL */ |
|
2321 diff = s->clkm.arm_ckctl ^ value; |
|
2322 s->clkm.arm_ckctl = value & 0x7fff; |
|
2323 omap_clkm_ckctl_update(s, diff, value); |
|
2324 return; |
|
2325 |
|
2326 case 0x04: /* ARM_IDLECT1 */ |
|
2327 diff = s->clkm.arm_idlect1 ^ value; |
|
2328 s->clkm.arm_idlect1 = value & 0x0fff; |
|
2329 omap_clkm_idlect1_update(s, diff, value); |
|
2330 return; |
|
2331 |
|
2332 case 0x08: /* ARM_IDLECT2 */ |
|
2333 diff = s->clkm.arm_idlect2 ^ value; |
|
2334 s->clkm.arm_idlect2 = value & 0x07ff; |
|
2335 omap_clkm_idlect2_update(s, diff, value); |
|
2336 return; |
|
2337 |
|
2338 case 0x0c: /* ARM_EWUPCT */ |
|
2339 diff = s->clkm.arm_ewupct ^ value; |
|
2340 s->clkm.arm_ewupct = value & 0x003f; |
|
2341 return; |
|
2342 |
|
2343 case 0x10: /* ARM_RSTCT1 */ |
|
2344 diff = s->clkm.arm_rstct1 ^ value; |
|
2345 s->clkm.arm_rstct1 = value & 0x0007; |
|
2346 if (value & 9) { |
|
2347 qemu_system_reset_request(); |
|
2348 s->clkm.cold_start = 0xa; |
|
2349 } |
|
2350 if (diff & ~value & 4) { /* DSP_RST */ |
|
2351 omap_mpui_reset(s); |
|
2352 omap_tipb_bridge_reset(s->private_tipb); |
|
2353 omap_tipb_bridge_reset(s->public_tipb); |
|
2354 } |
|
2355 if (diff & 2) { /* DSP_EN */ |
|
2356 clk = omap_findclk(s, "dsp_ck"); |
|
2357 omap_clk_canidle(clk, (~value >> 1) & 1); |
|
2358 } |
|
2359 return; |
|
2360 |
|
2361 case 0x14: /* ARM_RSTCT2 */ |
|
2362 s->clkm.arm_rstct2 = value & 0x0001; |
|
2363 return; |
|
2364 |
|
2365 case 0x18: /* ARM_SYSST */ |
|
2366 if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) { |
|
2367 s->clkm.clocking_scheme = (value >> 11) & 7; |
|
2368 printf("%s: clocking scheme set to %s\n", __FUNCTION__, |
|
2369 clkschemename[s->clkm.clocking_scheme]); |
|
2370 } |
|
2371 s->clkm.cold_start &= value & 0x3f; |
|
2372 return; |
|
2373 |
|
2374 case 0x1c: /* ARM_CKOUT1 */ |
|
2375 diff = s->clkm.arm_ckout1 ^ value; |
|
2376 s->clkm.arm_ckout1 = value & 0x003f; |
|
2377 omap_clkm_ckout1_update(s, diff, value); |
|
2378 return; |
|
2379 |
|
2380 case 0x20: /* ARM_CKOUT2 */ |
|
2381 default: |
|
2382 OMAP_BAD_REG(addr); |
|
2383 } |
|
2384 } |
|
2385 |
|
2386 static CPUReadMemoryFunc *omap_clkm_readfn[] = { |
|
2387 omap_badwidth_read16, |
|
2388 omap_clkm_read, |
|
2389 omap_badwidth_read16, |
|
2390 }; |
|
2391 |
|
2392 static CPUWriteMemoryFunc *omap_clkm_writefn[] = { |
|
2393 omap_badwidth_write16, |
|
2394 omap_clkm_write, |
|
2395 omap_badwidth_write16, |
|
2396 }; |
|
2397 |
|
2398 static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr) |
|
2399 { |
|
2400 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
|
2401 |
|
2402 switch (addr) { |
|
2403 case 0x04: /* DSP_IDLECT1 */ |
|
2404 return s->clkm.dsp_idlect1; |
|
2405 |
|
2406 case 0x08: /* DSP_IDLECT2 */ |
|
2407 return s->clkm.dsp_idlect2; |
|
2408 |
|
2409 case 0x14: /* DSP_RSTCT2 */ |
|
2410 return s->clkm.dsp_rstct2; |
|
2411 |
|
2412 case 0x18: /* DSP_SYSST */ |
|
2413 return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start | |
|
2414 (s->env->halted << 6); /* Quite useless... */ |
|
2415 } |
|
2416 |
|
2417 OMAP_BAD_REG(addr); |
|
2418 return 0; |
|
2419 } |
|
2420 |
|
2421 static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s, |
|
2422 uint16_t diff, uint16_t value) |
|
2423 { |
|
2424 omap_clk clk; |
|
2425 |
|
2426 SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */ |
|
2427 } |
|
2428 |
|
2429 static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s, |
|
2430 uint16_t diff, uint16_t value) |
|
2431 { |
|
2432 omap_clk clk; |
|
2433 |
|
2434 SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */ |
|
2435 } |
|
2436 |
|
2437 static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr, |
|
2438 uint32_t value) |
|
2439 { |
|
2440 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
|
2441 uint16_t diff; |
|
2442 |
|
2443 switch (addr) { |
|
2444 case 0x04: /* DSP_IDLECT1 */ |
|
2445 diff = s->clkm.dsp_idlect1 ^ value; |
|
2446 s->clkm.dsp_idlect1 = value & 0x01f7; |
|
2447 omap_clkdsp_idlect1_update(s, diff, value); |
|
2448 break; |
|
2449 |
|
2450 case 0x08: /* DSP_IDLECT2 */ |
|
2451 s->clkm.dsp_idlect2 = value & 0x0037; |
|
2452 diff = s->clkm.dsp_idlect1 ^ value; |
|
2453 omap_clkdsp_idlect2_update(s, diff, value); |
|
2454 break; |
|
2455 |
|
2456 case 0x14: /* DSP_RSTCT2 */ |
|
2457 s->clkm.dsp_rstct2 = value & 0x0001; |
|
2458 break; |
|
2459 |
|
2460 case 0x18: /* DSP_SYSST */ |
|
2461 s->clkm.cold_start &= value & 0x3f; |
|
2462 break; |
|
2463 |
|
2464 default: |
|
2465 OMAP_BAD_REG(addr); |
|
2466 } |
|
2467 } |
|
2468 |
|
2469 static CPUReadMemoryFunc *omap_clkdsp_readfn[] = { |
|
2470 omap_badwidth_read16, |
|
2471 omap_clkdsp_read, |
|
2472 omap_badwidth_read16, |
|
2473 }; |
|
2474 |
|
2475 static CPUWriteMemoryFunc *omap_clkdsp_writefn[] = { |
|
2476 omap_badwidth_write16, |
|
2477 omap_clkdsp_write, |
|
2478 omap_badwidth_write16, |
|
2479 }; |
|
2480 |
|
2481 static void omap_clkm_reset(struct omap_mpu_state_s *s) |
|
2482 { |
|
2483 if (s->wdt && s->wdt->reset) |
|
2484 s->clkm.cold_start = 0x6; |
|
2485 s->clkm.clocking_scheme = 0; |
|
2486 omap_clkm_ckctl_update(s, ~0, 0x3000); |
|
2487 s->clkm.arm_ckctl = 0x3000; |
|
2488 omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 ^ 0x0400, 0x0400); |
|
2489 s->clkm.arm_idlect1 = 0x0400; |
|
2490 omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 ^ 0x0100, 0x0100); |
|
2491 s->clkm.arm_idlect2 = 0x0100; |
|
2492 s->clkm.arm_ewupct = 0x003f; |
|
2493 s->clkm.arm_rstct1 = 0x0000; |
|
2494 s->clkm.arm_rstct2 = 0x0000; |
|
2495 s->clkm.arm_ckout1 = 0x0015; |
|
2496 s->clkm.dpll1_mode = 0x2002; |
|
2497 omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040); |
|
2498 s->clkm.dsp_idlect1 = 0x0040; |
|
2499 omap_clkdsp_idlect2_update(s, ~0, 0x0000); |
|
2500 s->clkm.dsp_idlect2 = 0x0000; |
|
2501 s->clkm.dsp_rstct2 = 0x0000; |
|
2502 } |
|
2503 |
|
2504 static void omap_clkm_init(target_phys_addr_t mpu_base, |
|
2505 target_phys_addr_t dsp_base, struct omap_mpu_state_s *s) |
|
2506 { |
|
2507 int iomemtype[2] = { |
|
2508 cpu_register_io_memory(0, omap_clkm_readfn, omap_clkm_writefn, s), |
|
2509 cpu_register_io_memory(0, omap_clkdsp_readfn, omap_clkdsp_writefn, s), |
|
2510 }; |
|
2511 |
|
2512 s->clkm.arm_idlect1 = 0x03ff; |
|
2513 s->clkm.arm_idlect2 = 0x0100; |
|
2514 s->clkm.dsp_idlect1 = 0x0002; |
|
2515 omap_clkm_reset(s); |
|
2516 s->clkm.cold_start = 0x3a; |
|
2517 |
|
2518 cpu_register_physical_memory(mpu_base, 0x100, iomemtype[0]); |
|
2519 cpu_register_physical_memory(dsp_base, 0x1000, iomemtype[1]); |
|
2520 } |
|
2521 |
|
2522 /* MPU I/O */ |
|
2523 struct omap_mpuio_s { |
|
2524 qemu_irq irq; |
|
2525 qemu_irq kbd_irq; |
|
2526 qemu_irq *in; |
|
2527 qemu_irq handler[16]; |
|
2528 qemu_irq wakeup; |
|
2529 |
|
2530 uint16_t inputs; |
|
2531 uint16_t outputs; |
|
2532 uint16_t dir; |
|
2533 uint16_t edge; |
|
2534 uint16_t mask; |
|
2535 uint16_t ints; |
|
2536 |
|
2537 uint16_t debounce; |
|
2538 uint16_t latch; |
|
2539 uint8_t event; |
|
2540 |
|
2541 uint8_t buttons[5]; |
|
2542 uint8_t row_latch; |
|
2543 uint8_t cols; |
|
2544 int kbd_mask; |
|
2545 int clk; |
|
2546 }; |
|
2547 |
|
2548 static void omap_mpuio_set(void *opaque, int line, int level) |
|
2549 { |
|
2550 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
|
2551 uint16_t prev = s->inputs; |
|
2552 |
|
2553 if (level) |
|
2554 s->inputs |= 1 << line; |
|
2555 else |
|
2556 s->inputs &= ~(1 << line); |
|
2557 |
|
2558 if (((1 << line) & s->dir & ~s->mask) && s->clk) { |
|
2559 if ((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) { |
|
2560 s->ints |= 1 << line; |
|
2561 qemu_irq_raise(s->irq); |
|
2562 /* TODO: wakeup */ |
|
2563 } |
|
2564 if ((s->event & (1 << 0)) && /* SET_GPIO_EVENT_MODE */ |
|
2565 (s->event >> 1) == line) /* PIN_SELECT */ |
|
2566 s->latch = s->inputs; |
|
2567 } |
|
2568 } |
|
2569 |
|
2570 static void omap_mpuio_kbd_update(struct omap_mpuio_s *s) |
|
2571 { |
|
2572 int i; |
|
2573 uint8_t *row, rows = 0, cols = ~s->cols; |
|
2574 |
|
2575 for (row = s->buttons + 4, i = 1 << 4; i; row --, i >>= 1) |
|
2576 if (*row & cols) |
|
2577 rows |= i; |
|
2578 |
|
2579 qemu_set_irq(s->kbd_irq, rows && !s->kbd_mask && s->clk); |
|
2580 s->row_latch = ~rows; |
|
2581 } |
|
2582 |
|
2583 static uint32_t omap_mpuio_read(void *opaque, target_phys_addr_t addr) |
|
2584 { |
|
2585 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
|
2586 int offset = addr & OMAP_MPUI_REG_MASK; |
|
2587 uint16_t ret; |
|
2588 |
|
2589 switch (offset) { |
|
2590 case 0x00: /* INPUT_LATCH */ |
|
2591 return s->inputs; |
|
2592 |
|
2593 case 0x04: /* OUTPUT_REG */ |
|
2594 return s->outputs; |
|
2595 |
|
2596 case 0x08: /* IO_CNTL */ |
|
2597 return s->dir; |
|
2598 |
|
2599 case 0x10: /* KBR_LATCH */ |
|
2600 return s->row_latch; |
|
2601 |
|
2602 case 0x14: /* KBC_REG */ |
|
2603 return s->cols; |
|
2604 |
|
2605 case 0x18: /* GPIO_EVENT_MODE_REG */ |
|
2606 return s->event; |
|
2607 |
|
2608 case 0x1c: /* GPIO_INT_EDGE_REG */ |
|
2609 return s->edge; |
|
2610 |
|
2611 case 0x20: /* KBD_INT */ |
|
2612 return (~s->row_latch & 0x1f) && !s->kbd_mask; |
|
2613 |
|
2614 case 0x24: /* GPIO_INT */ |
|
2615 ret = s->ints; |
|
2616 s->ints &= s->mask; |
|
2617 if (ret) |
|
2618 qemu_irq_lower(s->irq); |
|
2619 return ret; |
|
2620 |
|
2621 case 0x28: /* KBD_MASKIT */ |
|
2622 return s->kbd_mask; |
|
2623 |
|
2624 case 0x2c: /* GPIO_MASKIT */ |
|
2625 return s->mask; |
|
2626 |
|
2627 case 0x30: /* GPIO_DEBOUNCING_REG */ |
|
2628 return s->debounce; |
|
2629 |
|
2630 case 0x34: /* GPIO_LATCH_REG */ |
|
2631 return s->latch; |
|
2632 } |
|
2633 |
|
2634 OMAP_BAD_REG(addr); |
|
2635 return 0; |
|
2636 } |
|
2637 |
|
2638 static void omap_mpuio_write(void *opaque, target_phys_addr_t addr, |
|
2639 uint32_t value) |
|
2640 { |
|
2641 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
|
2642 int offset = addr & OMAP_MPUI_REG_MASK; |
|
2643 uint16_t diff; |
|
2644 int ln; |
|
2645 |
|
2646 switch (offset) { |
|
2647 case 0x04: /* OUTPUT_REG */ |
|
2648 diff = (s->outputs ^ value) & ~s->dir; |
|
2649 s->outputs = value; |
|
2650 while ((ln = ffs(diff))) { |
|
2651 ln --; |
|
2652 if (s->handler[ln]) |
|
2653 qemu_set_irq(s->handler[ln], (value >> ln) & 1); |
|
2654 diff &= ~(1 << ln); |
|
2655 } |
|
2656 break; |
|
2657 |
|
2658 case 0x08: /* IO_CNTL */ |
|
2659 diff = s->outputs & (s->dir ^ value); |
|
2660 s->dir = value; |
|
2661 |
|
2662 value = s->outputs & ~s->dir; |
|
2663 while ((ln = ffs(diff))) { |
|
2664 ln --; |
|
2665 if (s->handler[ln]) |
|
2666 qemu_set_irq(s->handler[ln], (value >> ln) & 1); |
|
2667 diff &= ~(1 << ln); |
|
2668 } |
|
2669 break; |
|
2670 |
|
2671 case 0x14: /* KBC_REG */ |
|
2672 s->cols = value; |
|
2673 omap_mpuio_kbd_update(s); |
|
2674 break; |
|
2675 |
|
2676 case 0x18: /* GPIO_EVENT_MODE_REG */ |
|
2677 s->event = value & 0x1f; |
|
2678 break; |
|
2679 |
|
2680 case 0x1c: /* GPIO_INT_EDGE_REG */ |
|
2681 s->edge = value; |
|
2682 break; |
|
2683 |
|
2684 case 0x28: /* KBD_MASKIT */ |
|
2685 s->kbd_mask = value & 1; |
|
2686 omap_mpuio_kbd_update(s); |
|
2687 break; |
|
2688 |
|
2689 case 0x2c: /* GPIO_MASKIT */ |
|
2690 s->mask = value; |
|
2691 break; |
|
2692 |
|
2693 case 0x30: /* GPIO_DEBOUNCING_REG */ |
|
2694 s->debounce = value & 0x1ff; |
|
2695 break; |
|
2696 |
|
2697 case 0x00: /* INPUT_LATCH */ |
|
2698 case 0x10: /* KBR_LATCH */ |
|
2699 case 0x20: /* KBD_INT */ |
|
2700 case 0x24: /* GPIO_INT */ |
|
2701 case 0x34: /* GPIO_LATCH_REG */ |
|
2702 OMAP_RO_REG(addr); |
|
2703 return; |
|
2704 |
|
2705 default: |
|
2706 OMAP_BAD_REG(addr); |
|
2707 return; |
|
2708 } |
|
2709 } |
|
2710 |
|
2711 static CPUReadMemoryFunc *omap_mpuio_readfn[] = { |
|
2712 omap_badwidth_read16, |
|
2713 omap_mpuio_read, |
|
2714 omap_badwidth_read16, |
|
2715 }; |
|
2716 |
|
2717 static CPUWriteMemoryFunc *omap_mpuio_writefn[] = { |
|
2718 omap_badwidth_write16, |
|
2719 omap_mpuio_write, |
|
2720 omap_badwidth_write16, |
|
2721 }; |
|
2722 |
|
2723 static void omap_mpuio_reset(struct omap_mpuio_s *s) |
|
2724 { |
|
2725 s->inputs = 0; |
|
2726 s->outputs = 0; |
|
2727 s->dir = ~0; |
|
2728 s->event = 0; |
|
2729 s->edge = 0; |
|
2730 s->kbd_mask = 0; |
|
2731 s->mask = 0; |
|
2732 s->debounce = 0; |
|
2733 s->latch = 0; |
|
2734 s->ints = 0; |
|
2735 s->row_latch = 0x1f; |
|
2736 s->clk = 1; |
|
2737 } |
|
2738 |
|
2739 static void omap_mpuio_onoff(void *opaque, int line, int on) |
|
2740 { |
|
2741 struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque; |
|
2742 |
|
2743 s->clk = on; |
|
2744 if (on) |
|
2745 omap_mpuio_kbd_update(s); |
|
2746 } |
|
2747 |
|
2748 struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base, |
|
2749 qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup, |
|
2750 omap_clk clk) |
|
2751 { |
|
2752 int iomemtype; |
|
2753 struct omap_mpuio_s *s = (struct omap_mpuio_s *) |
|
2754 qemu_mallocz(sizeof(struct omap_mpuio_s)); |
|
2755 |
|
2756 s->irq = gpio_int; |
|
2757 s->kbd_irq = kbd_int; |
|
2758 s->wakeup = wakeup; |
|
2759 s->in = qemu_allocate_irqs(omap_mpuio_set, s, 16); |
|
2760 omap_mpuio_reset(s); |
|
2761 |
|
2762 iomemtype = cpu_register_io_memory(0, omap_mpuio_readfn, |
|
2763 omap_mpuio_writefn, s); |
|
2764 cpu_register_physical_memory(base, 0x800, iomemtype); |
|
2765 |
|
2766 omap_clk_adduser(clk, qemu_allocate_irqs(omap_mpuio_onoff, s, 1)[0]); |
|
2767 |
|
2768 return s; |
|
2769 } |
|
2770 |
|
2771 qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s) |
|
2772 { |
|
2773 return s->in; |
|
2774 } |
|
2775 |
|
2776 void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler) |
|
2777 { |
|
2778 if (line >= 16 || line < 0) |
|
2779 cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line); |
|
2780 s->handler[line] = handler; |
|
2781 } |
|
2782 |
|
2783 void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down) |
|
2784 { |
|
2785 if (row >= 5 || row < 0) |
|
2786 cpu_abort(cpu_single_env, "%s: No key %i-%i\n", |
|
2787 __FUNCTION__, col, row); |
|
2788 |
|
2789 if (down) |
|
2790 s->buttons[row] |= 1 << col; |
|
2791 else |
|
2792 s->buttons[row] &= ~(1 << col); |
|
2793 |
|
2794 omap_mpuio_kbd_update(s); |
|
2795 } |
|
2796 |
|
2797 /* General-Purpose I/O */ |
|
2798 struct omap_gpio_s { |
|
2799 qemu_irq irq; |
|
2800 qemu_irq *in; |
|
2801 qemu_irq handler[16]; |
|
2802 |
|
2803 uint16_t inputs; |
|
2804 uint16_t outputs; |
|
2805 uint16_t dir; |
|
2806 uint16_t edge; |
|
2807 uint16_t mask; |
|
2808 uint16_t ints; |
|
2809 uint16_t pins; |
|
2810 }; |
|
2811 |
|
2812 static void omap_gpio_set(void *opaque, int line, int level) |
|
2813 { |
|
2814 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; |
|
2815 uint16_t prev = s->inputs; |
|
2816 |
|
2817 if (level) |
|
2818 s->inputs |= 1 << line; |
|
2819 else |
|
2820 s->inputs &= ~(1 << line); |
|
2821 |
|
2822 if (((s->edge & s->inputs & ~prev) | (~s->edge & ~s->inputs & prev)) & |
|
2823 (1 << line) & s->dir & ~s->mask) { |
|
2824 s->ints |= 1 << line; |
|
2825 qemu_irq_raise(s->irq); |
|
2826 } |
|
2827 } |
|
2828 |
|
2829 static uint32_t omap_gpio_read(void *opaque, target_phys_addr_t addr) |
|
2830 { |
|
2831 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; |
|
2832 int offset = addr & OMAP_MPUI_REG_MASK; |
|
2833 |
|
2834 switch (offset) { |
|
2835 case 0x00: /* DATA_INPUT */ |
|
2836 return s->inputs & s->pins; |
|
2837 |
|
2838 case 0x04: /* DATA_OUTPUT */ |
|
2839 return s->outputs; |
|
2840 |
|
2841 case 0x08: /* DIRECTION_CONTROL */ |
|
2842 return s->dir; |
|
2843 |
|
2844 case 0x0c: /* INTERRUPT_CONTROL */ |
|
2845 return s->edge; |
|
2846 |
|
2847 case 0x10: /* INTERRUPT_MASK */ |
|
2848 return s->mask; |
|
2849 |
|
2850 case 0x14: /* INTERRUPT_STATUS */ |
|
2851 return s->ints; |
|
2852 |
|
2853 case 0x18: /* PIN_CONTROL (not in OMAP310) */ |
|
2854 OMAP_BAD_REG(addr); |
|
2855 return s->pins; |
|
2856 } |
|
2857 |
|
2858 OMAP_BAD_REG(addr); |
|
2859 return 0; |
|
2860 } |
|
2861 |
|
2862 static void omap_gpio_write(void *opaque, target_phys_addr_t addr, |
|
2863 uint32_t value) |
|
2864 { |
|
2865 struct omap_gpio_s *s = (struct omap_gpio_s *) opaque; |
|
2866 int offset = addr & OMAP_MPUI_REG_MASK; |
|
2867 uint16_t diff; |
|
2868 int ln; |
|
2869 |
|
2870 switch (offset) { |
|
2871 case 0x00: /* DATA_INPUT */ |
|
2872 OMAP_RO_REG(addr); |
|
2873 return; |
|
2874 |
|
2875 case 0x04: /* DATA_OUTPUT */ |
|
2876 diff = (s->outputs ^ value) & ~s->dir; |
|
2877 s->outputs = value; |
|
2878 while ((ln = ffs(diff))) { |
|
2879 ln --; |
|
2880 if (s->handler[ln]) |
|
2881 qemu_set_irq(s->handler[ln], (value >> ln) & 1); |
|
2882 diff &= ~(1 << ln); |
|
2883 } |
|
2884 break; |
|
2885 |
|
2886 case 0x08: /* DIRECTION_CONTROL */ |
|
2887 diff = s->outputs & (s->dir ^ value); |
|
2888 s->dir = value; |
|
2889 |
|
2890 value = s->outputs & ~s->dir; |
|
2891 while ((ln = ffs(diff))) { |
|
2892 ln --; |
|
2893 if (s->handler[ln]) |
|
2894 qemu_set_irq(s->handler[ln], (value >> ln) & 1); |
|
2895 diff &= ~(1 << ln); |
|
2896 } |
|
2897 break; |
|
2898 |
|
2899 case 0x0c: /* INTERRUPT_CONTROL */ |
|
2900 s->edge = value; |
|
2901 break; |
|
2902 |
|
2903 case 0x10: /* INTERRUPT_MASK */ |
|
2904 s->mask = value; |
|
2905 break; |
|
2906 |
|
2907 case 0x14: /* INTERRUPT_STATUS */ |
|
2908 s->ints &= ~value; |
|
2909 if (!s->ints) |
|
2910 qemu_irq_lower(s->irq); |
|
2911 break; |
|
2912 |
|
2913 case 0x18: /* PIN_CONTROL (not in OMAP310 TRM) */ |
|
2914 OMAP_BAD_REG(addr); |
|
2915 s->pins = value; |
|
2916 break; |
|
2917 |
|
2918 default: |
|
2919 OMAP_BAD_REG(addr); |
|
2920 return; |
|
2921 } |
|
2922 } |
|
2923 |
|
2924 /* *Some* sources say the memory region is 32-bit. */ |
|
2925 static CPUReadMemoryFunc *omap_gpio_readfn[] = { |
|
2926 omap_badwidth_read16, |
|
2927 omap_gpio_read, |
|
2928 omap_badwidth_read16, |
|
2929 }; |
|
2930 |
|
2931 static CPUWriteMemoryFunc *omap_gpio_writefn[] = { |
|
2932 omap_badwidth_write16, |
|
2933 omap_gpio_write, |
|
2934 omap_badwidth_write16, |
|
2935 }; |
|
2936 |
|
2937 static void omap_gpio_reset(struct omap_gpio_s *s) |
|
2938 { |
|
2939 s->inputs = 0; |
|
2940 s->outputs = ~0; |
|
2941 s->dir = ~0; |
|
2942 s->edge = ~0; |
|
2943 s->mask = ~0; |
|
2944 s->ints = 0; |
|
2945 s->pins = ~0; |
|
2946 } |
|
2947 |
|
2948 struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base, |
|
2949 qemu_irq irq, omap_clk clk) |
|
2950 { |
|
2951 int iomemtype; |
|
2952 struct omap_gpio_s *s = (struct omap_gpio_s *) |
|
2953 qemu_mallocz(sizeof(struct omap_gpio_s)); |
|
2954 |
|
2955 s->irq = irq; |
|
2956 s->in = qemu_allocate_irqs(omap_gpio_set, s, 16); |
|
2957 omap_gpio_reset(s); |
|
2958 |
|
2959 iomemtype = cpu_register_io_memory(0, omap_gpio_readfn, |
|
2960 omap_gpio_writefn, s); |
|
2961 cpu_register_physical_memory(base, 0x1000, iomemtype); |
|
2962 |
|
2963 return s; |
|
2964 } |
|
2965 |
|
2966 qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s) |
|
2967 { |
|
2968 return s->in; |
|
2969 } |
|
2970 |
|
2971 void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler) |
|
2972 { |
|
2973 if (line >= 16 || line < 0) |
|
2974 cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line); |
|
2975 s->handler[line] = handler; |
|
2976 } |
|
2977 |
|
2978 /* MicroWire Interface */ |
|
2979 struct omap_uwire_s { |
|
2980 qemu_irq txirq; |
|
2981 qemu_irq rxirq; |
|
2982 qemu_irq txdrq; |
|
2983 |
|
2984 uint16_t txbuf; |
|
2985 uint16_t rxbuf; |
|
2986 uint16_t control; |
|
2987 uint16_t setup[5]; |
|
2988 |
|
2989 struct uwire_slave_s *chip[4]; |
|
2990 }; |
|
2991 |
|
2992 static void omap_uwire_transfer_start(struct omap_uwire_s *s) |
|
2993 { |
|
2994 int chipselect = (s->control >> 10) & 3; /* INDEX */ |
|
2995 struct uwire_slave_s *slave = s->chip[chipselect]; |
|
2996 |
|
2997 if ((s->control >> 5) & 0x1f) { /* NB_BITS_WR */ |
|
2998 if (s->control & (1 << 12)) /* CS_CMD */ |
|
2999 if (slave && slave->send) |
|
3000 slave->send(slave->opaque, |
|
3001 s->txbuf >> (16 - ((s->control >> 5) & 0x1f))); |
|
3002 s->control &= ~(1 << 14); /* CSRB */ |
|
3003 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or |
|
3004 * a DRQ. When is the level IRQ supposed to be reset? */ |
|
3005 } |
|
3006 |
|
3007 if ((s->control >> 0) & 0x1f) { /* NB_BITS_RD */ |
|
3008 if (s->control & (1 << 12)) /* CS_CMD */ |
|
3009 if (slave && slave->receive) |
|
3010 s->rxbuf = slave->receive(slave->opaque); |
|
3011 s->control |= 1 << 15; /* RDRB */ |
|
3012 /* TODO: depending on s->setup[4] bits [1:0] assert an IRQ or |
|
3013 * a DRQ. When is the level IRQ supposed to be reset? */ |
|
3014 } |
|
3015 } |
|
3016 |
|
3017 static uint32_t omap_uwire_read(void *opaque, target_phys_addr_t addr) |
|
3018 { |
|
3019 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; |
|
3020 int offset = addr & OMAP_MPUI_REG_MASK; |
|
3021 |
|
3022 switch (offset) { |
|
3023 case 0x00: /* RDR */ |
|
3024 s->control &= ~(1 << 15); /* RDRB */ |
|
3025 return s->rxbuf; |
|
3026 |
|
3027 case 0x04: /* CSR */ |
|
3028 return s->control; |
|
3029 |
|
3030 case 0x08: /* SR1 */ |
|
3031 return s->setup[0]; |
|
3032 case 0x0c: /* SR2 */ |
|
3033 return s->setup[1]; |
|
3034 case 0x10: /* SR3 */ |
|
3035 return s->setup[2]; |
|
3036 case 0x14: /* SR4 */ |
|
3037 return s->setup[3]; |
|
3038 case 0x18: /* SR5 */ |
|
3039 return s->setup[4]; |
|
3040 } |
|
3041 |
|
3042 OMAP_BAD_REG(addr); |
|
3043 return 0; |
|
3044 } |
|
3045 |
|
3046 static void omap_uwire_write(void *opaque, target_phys_addr_t addr, |
|
3047 uint32_t value) |
|
3048 { |
|
3049 struct omap_uwire_s *s = (struct omap_uwire_s *) opaque; |
|
3050 int offset = addr & OMAP_MPUI_REG_MASK; |
|
3051 |
|
3052 switch (offset) { |
|
3053 case 0x00: /* TDR */ |
|
3054 s->txbuf = value; /* TD */ |
|
3055 if ((s->setup[4] & (1 << 2)) && /* AUTO_TX_EN */ |
|
3056 ((s->setup[4] & (1 << 3)) || /* CS_TOGGLE_TX_EN */ |
|
3057 (s->control & (1 << 12)))) { /* CS_CMD */ |
|
3058 s->control |= 1 << 14; /* CSRB */ |
|
3059 omap_uwire_transfer_start(s); |
|
3060 } |
|
3061 break; |
|
3062 |
|
3063 case 0x04: /* CSR */ |
|
3064 s->control = value & 0x1fff; |
|
3065 if (value & (1 << 13)) /* START */ |
|
3066 omap_uwire_transfer_start(s); |
|
3067 break; |
|
3068 |
|
3069 case 0x08: /* SR1 */ |
|
3070 s->setup[0] = value & 0x003f; |
|
3071 break; |
|
3072 |
|
3073 case 0x0c: /* SR2 */ |
|
3074 s->setup[1] = value & 0x0fc0; |
|
3075 break; |
|
3076 |
|
3077 case 0x10: /* SR3 */ |
|
3078 s->setup[2] = value & 0x0003; |
|
3079 break; |
|
3080 |
|
3081 case 0x14: /* SR4 */ |
|
3082 s->setup[3] = value & 0x0001; |
|
3083 break; |
|
3084 |
|
3085 case 0x18: /* SR5 */ |
|
3086 s->setup[4] = value & 0x000f; |
|
3087 break; |
|
3088 |
|
3089 default: |
|
3090 OMAP_BAD_REG(addr); |
|
3091 return; |
|
3092 } |
|
3093 } |
|
3094 |
|
3095 static CPUReadMemoryFunc *omap_uwire_readfn[] = { |
|
3096 omap_badwidth_read16, |
|
3097 omap_uwire_read, |
|
3098 omap_badwidth_read16, |
|
3099 }; |
|
3100 |
|
3101 static CPUWriteMemoryFunc *omap_uwire_writefn[] = { |
|
3102 omap_badwidth_write16, |
|
3103 omap_uwire_write, |
|
3104 omap_badwidth_write16, |
|
3105 }; |
|
3106 |
|
3107 static void omap_uwire_reset(struct omap_uwire_s *s) |
|
3108 { |
|
3109 s->control = 0; |
|
3110 s->setup[0] = 0; |
|
3111 s->setup[1] = 0; |
|
3112 s->setup[2] = 0; |
|
3113 s->setup[3] = 0; |
|
3114 s->setup[4] = 0; |
|
3115 } |
|
3116 |
|
3117 struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base, |
|
3118 qemu_irq *irq, qemu_irq dma, omap_clk clk) |
|
3119 { |
|
3120 int iomemtype; |
|
3121 struct omap_uwire_s *s = (struct omap_uwire_s *) |
|
3122 qemu_mallocz(sizeof(struct omap_uwire_s)); |
|
3123 |
|
3124 s->txirq = irq[0]; |
|
3125 s->rxirq = irq[1]; |
|
3126 s->txdrq = dma; |
|
3127 omap_uwire_reset(s); |
|
3128 |
|
3129 iomemtype = cpu_register_io_memory(0, omap_uwire_readfn, |
|
3130 omap_uwire_writefn, s); |
|
3131 cpu_register_physical_memory(base, 0x800, iomemtype); |
|
3132 |
|
3133 return s; |
|
3134 } |
|
3135 |
|
3136 void omap_uwire_attach(struct omap_uwire_s *s, |
|
3137 struct uwire_slave_s *slave, int chipselect) |
|
3138 { |
|
3139 if (chipselect < 0 || chipselect > 3) { |
|
3140 fprintf(stderr, "%s: Bad chipselect %i\n", __FUNCTION__, chipselect); |
|
3141 exit(-1); |
|
3142 } |
|
3143 |
|
3144 s->chip[chipselect] = slave; |
|
3145 } |
|
3146 |
|
3147 /* Pseudonoise Pulse-Width Light Modulator */ |
|
3148 static void omap_pwl_update(struct omap_mpu_state_s *s) |
|
3149 { |
|
3150 int output = (s->pwl.clk && s->pwl.enable) ? s->pwl.level : 0; |
|
3151 |
|
3152 if (output != s->pwl.output) { |
|
3153 s->pwl.output = output; |
|
3154 printf("%s: Backlight now at %i/256\n", __FUNCTION__, output); |
|
3155 } |
|
3156 } |
|
3157 |
|
3158 static uint32_t omap_pwl_read(void *opaque, target_phys_addr_t addr) |
|
3159 { |
|
3160 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
|
3161 int offset = addr & OMAP_MPUI_REG_MASK; |
|
3162 |
|
3163 switch (offset) { |
|
3164 case 0x00: /* PWL_LEVEL */ |
|
3165 return s->pwl.level; |
|
3166 case 0x04: /* PWL_CTRL */ |
|
3167 return s->pwl.enable; |
|
3168 } |
|
3169 OMAP_BAD_REG(addr); |
|
3170 return 0; |
|
3171 } |
|
3172 |
|
3173 static void omap_pwl_write(void *opaque, target_phys_addr_t addr, |
|
3174 uint32_t value) |
|
3175 { |
|
3176 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
|
3177 int offset = addr & OMAP_MPUI_REG_MASK; |
|
3178 |
|
3179 switch (offset) { |
|
3180 case 0x00: /* PWL_LEVEL */ |
|
3181 s->pwl.level = value; |
|
3182 omap_pwl_update(s); |
|
3183 break; |
|
3184 case 0x04: /* PWL_CTRL */ |
|
3185 s->pwl.enable = value & 1; |
|
3186 omap_pwl_update(s); |
|
3187 break; |
|
3188 default: |
|
3189 OMAP_BAD_REG(addr); |
|
3190 return; |
|
3191 } |
|
3192 } |
|
3193 |
|
3194 static CPUReadMemoryFunc *omap_pwl_readfn[] = { |
|
3195 omap_pwl_read, |
|
3196 omap_badwidth_read8, |
|
3197 omap_badwidth_read8, |
|
3198 }; |
|
3199 |
|
3200 static CPUWriteMemoryFunc *omap_pwl_writefn[] = { |
|
3201 omap_pwl_write, |
|
3202 omap_badwidth_write8, |
|
3203 omap_badwidth_write8, |
|
3204 }; |
|
3205 |
|
3206 static void omap_pwl_reset(struct omap_mpu_state_s *s) |
|
3207 { |
|
3208 s->pwl.output = 0; |
|
3209 s->pwl.level = 0; |
|
3210 s->pwl.enable = 0; |
|
3211 s->pwl.clk = 1; |
|
3212 omap_pwl_update(s); |
|
3213 } |
|
3214 |
|
3215 static void omap_pwl_clk_update(void *opaque, int line, int on) |
|
3216 { |
|
3217 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
|
3218 |
|
3219 s->pwl.clk = on; |
|
3220 omap_pwl_update(s); |
|
3221 } |
|
3222 |
|
3223 static void omap_pwl_init(target_phys_addr_t base, struct omap_mpu_state_s *s, |
|
3224 omap_clk clk) |
|
3225 { |
|
3226 int iomemtype; |
|
3227 |
|
3228 omap_pwl_reset(s); |
|
3229 |
|
3230 iomemtype = cpu_register_io_memory(0, omap_pwl_readfn, |
|
3231 omap_pwl_writefn, s); |
|
3232 cpu_register_physical_memory(base, 0x800, iomemtype); |
|
3233 |
|
3234 omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]); |
|
3235 } |
|
3236 |
|
3237 /* Pulse-Width Tone module */ |
|
3238 static uint32_t omap_pwt_read(void *opaque, target_phys_addr_t addr) |
|
3239 { |
|
3240 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
|
3241 int offset = addr & OMAP_MPUI_REG_MASK; |
|
3242 |
|
3243 switch (offset) { |
|
3244 case 0x00: /* FRC */ |
|
3245 return s->pwt.frc; |
|
3246 case 0x04: /* VCR */ |
|
3247 return s->pwt.vrc; |
|
3248 case 0x08: /* GCR */ |
|
3249 return s->pwt.gcr; |
|
3250 } |
|
3251 OMAP_BAD_REG(addr); |
|
3252 return 0; |
|
3253 } |
|
3254 |
|
3255 static void omap_pwt_write(void *opaque, target_phys_addr_t addr, |
|
3256 uint32_t value) |
|
3257 { |
|
3258 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; |
|
3259 int offset = addr & OMAP_MPUI_REG_MASK; |
|
3260 |
|
3261 switch (offset) { |
|
3262 case 0x00: /* FRC */ |
|
3263 s->pwt.frc = value & 0x3f; |
|
3264 break; |
|
3265 case 0x04: /* VRC */ |
|
3266 if ((value ^ s->pwt.vrc) & 1) { |
|
3267 if (value & 1) |
|
3268 printf("%s: %iHz buzz on\n", __FUNCTION__, (int) |
|
3269 /* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */ |
|
3270 ((omap_clk_getrate(s->pwt.clk) >> 3) / |
|
3271 /* Pre-multiplexer divider */ |
|
3272 ((s->pwt.gcr & 2) ? 1 : 154) / |
|
3273 /* Octave multiplexer */ |
|
3274 (2 << (value & 3)) * |
|
3275 /* 101/107 divider */ |
|
3276 ((value & (1 << 2)) ? 101 : 107) * |
|
3277 /* 49/55 divider */ |
|
3278 ((value & (1 << 3)) ? 49 : 55) * |
|
3279 /* 50/63 divider */ |
|
3280 ((value & (1 << 4)) ? 50 : 63) * |
|
3281 /* 80/127 divider */ |
|
3282 ((value & (1 << 5)) ? 80 : 127) / |
|
3283 (107 * 55 * 63 * 127))); |
|
3284 else |
|
3285 printf("%s: silence!\n", __FUNCTION__); |
|
3286 } |
|
3287 s->pwt.vrc = value & 0x7f; |
|
3288 break; |
|
3289 case 0x08: /* GCR */ |
|
3290 s->pwt.gcr = value & 3; |
|
3291 break; |
|
3292 default: |
|
3293 OMAP_BAD_REG(addr); |
|
3294 return; |
|
3295 } |
|
3296 } |
|
3297 |
|
3298 static CPUReadMemoryFunc *omap_pwt_readfn[] = { |
|
3299 omap_pwt_read, |
|
3300 omap_badwidth_read8, |
|
3301 omap_badwidth_read8, |
|
3302 }; |
|
3303 |
|
3304 static CPUWriteMemoryFunc *omap_pwt_writefn[] = { |
|
3305 omap_pwt_write, |
|
3306 omap_badwidth_write8, |
|
3307 omap_badwidth_write8, |
|
3308 }; |
|
3309 |
|
3310 static void omap_pwt_reset(struct omap_mpu_state_s *s) |
|
3311 { |
|
3312 s->pwt.frc = 0; |
|
3313 s->pwt.vrc = 0; |
|
3314 s->pwt.gcr = 0; |
|
3315 } |
|
3316 |
|
3317 static void omap_pwt_init(target_phys_addr_t base, struct omap_mpu_state_s *s, |
|
3318 omap_clk clk) |
|
3319 { |
|
3320 int iomemtype; |
|
3321 |
|
3322 s->pwt.clk = clk; |
|
3323 omap_pwt_reset(s); |
|
3324 |
|
3325 iomemtype = cpu_register_io_memory(0, omap_pwt_readfn, |
|
3326 omap_pwt_writefn, s); |
|
3327 cpu_register_physical_memory(base, 0x800, iomemtype); |
|
3328 } |
|
3329 |
|
3330 /* Real-time Clock module */ |
|
3331 struct omap_rtc_s { |
|
3332 qemu_irq irq; |
|
3333 qemu_irq alarm; |
|
3334 QEMUTimer *clk; |
|
3335 |
|
3336 uint8_t interrupts; |
|
3337 uint8_t status; |
|
3338 int16_t comp_reg; |
|
3339 int running; |
|
3340 int pm_am; |
|
3341 int auto_comp; |
|
3342 int round; |
|
3343 struct tm alarm_tm; |
|
3344 time_t alarm_ti; |
|
3345 |
|
3346 struct tm current_tm; |
|
3347 time_t ti; |
|
3348 uint64_t tick; |
|
3349 }; |
|
3350 |
|
3351 static void omap_rtc_interrupts_update(struct omap_rtc_s *s) |
|
3352 { |
|
3353 /* s->alarm is level-triggered */ |
|
3354 qemu_set_irq(s->alarm, (s->status >> 6) & 1); |
|
3355 } |
|
3356 |
|
3357 static void omap_rtc_alarm_update(struct omap_rtc_s *s) |
|
3358 { |
|
3359 s->alarm_ti = mktimegm(&s->alarm_tm); |
|
3360 if (s->alarm_ti == -1) |
|
3361 printf("%s: conversion failed\n", __FUNCTION__); |
|
3362 } |
|
3363 |
|
3364 static inline uint8_t omap_rtc_bcd(int num) |
|
3365 { |
|
3366 return ((num / 10) << 4) | (num % 10); |
|
3367 } |
|
3368 |
|
3369 static inline int omap_rtc_bin(uint8_t num) |
|
3370 { |
|
3371 return (num & 15) + 10 * (num >> 4); |
|
3372 } |
|
3373 |
|
3374 static uint32_t omap_rtc_read(void *opaque, target_phys_addr_t addr) |
|
3375 { |
|
3376 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; |
|
3377 int offset = addr & OMAP_MPUI_REG_MASK; |
|
3378 uint8_t i; |
|
3379 |
|
3380 switch (offset) { |
|
3381 case 0x00: /* SECONDS_REG */ |
|
3382 return omap_rtc_bcd(s->current_tm.tm_sec); |
|
3383 |
|
3384 case 0x04: /* MINUTES_REG */ |
|
3385 return omap_rtc_bcd(s->current_tm.tm_min); |
|
3386 |
|
3387 case 0x08: /* HOURS_REG */ |
|
3388 if (s->pm_am) |
|
3389 return ((s->current_tm.tm_hour > 11) << 7) | |
|
3390 omap_rtc_bcd(((s->current_tm.tm_hour - 1) % 12) + 1); |
|
3391 else |
|
3392 return omap_rtc_bcd(s->current_tm.tm_hour); |
|
3393 |
|
3394 case 0x0c: /* DAYS_REG */ |
|
3395 return omap_rtc_bcd(s->current_tm.tm_mday); |
|
3396 |
|
3397 case 0x10: /* MONTHS_REG */ |
|
3398 return omap_rtc_bcd(s->current_tm.tm_mon + 1); |
|
3399 |
|
3400 case 0x14: /* YEARS_REG */ |
|
3401 return omap_rtc_bcd(s->current_tm.tm_year % 100); |
|
3402 |
|
3403 case 0x18: /* WEEK_REG */ |
|
3404 return s->current_tm.tm_wday; |
|
3405 |
|
3406 case 0x20: /* ALARM_SECONDS_REG */ |
|
3407 return omap_rtc_bcd(s->alarm_tm.tm_sec); |
|
3408 |
|
3409 case 0x24: /* ALARM_MINUTES_REG */ |
|
3410 return omap_rtc_bcd(s->alarm_tm.tm_min); |
|
3411 |
|
3412 case 0x28: /* ALARM_HOURS_REG */ |
|
3413 if (s->pm_am) |
|
3414 return ((s->alarm_tm.tm_hour > 11) << 7) | |
|
3415 omap_rtc_bcd(((s->alarm_tm.tm_hour - 1) % 12) + 1); |
|
3416 else |
|
3417 return omap_rtc_bcd(s->alarm_tm.tm_hour); |
|
3418 |
|
3419 case 0x2c: /* ALARM_DAYS_REG */ |
|
3420 return omap_rtc_bcd(s->alarm_tm.tm_mday); |
|
3421 |
|
3422 case 0x30: /* ALARM_MONTHS_REG */ |
|
3423 return omap_rtc_bcd(s->alarm_tm.tm_mon + 1); |
|
3424 |
|
3425 case 0x34: /* ALARM_YEARS_REG */ |
|
3426 return omap_rtc_bcd(s->alarm_tm.tm_year % 100); |
|
3427 |
|
3428 case 0x40: /* RTC_CTRL_REG */ |
|
3429 return (s->pm_am << 3) | (s->auto_comp << 2) | |
|
3430 (s->round << 1) | s->running; |
|
3431 |
|
3432 case 0x44: /* RTC_STATUS_REG */ |
|
3433 i = s->status; |
|
3434 s->status &= ~0x3d; |
|
3435 return i; |
|
3436 |
|
3437 case 0x48: /* RTC_INTERRUPTS_REG */ |
|
3438 return s->interrupts; |
|
3439 |
|
3440 case 0x4c: /* RTC_COMP_LSB_REG */ |
|
3441 return ((uint16_t) s->comp_reg) & 0xff; |
|
3442 |
|
3443 case 0x50: /* RTC_COMP_MSB_REG */ |
|
3444 return ((uint16_t) s->comp_reg) >> 8; |
|
3445 } |
|
3446 |
|
3447 OMAP_BAD_REG(addr); |
|
3448 return 0; |
|
3449 } |
|
3450 |
|
3451 static void omap_rtc_write(void *opaque, target_phys_addr_t addr, |
|
3452 uint32_t value) |
|
3453 { |
|
3454 struct omap_rtc_s *s = (struct omap_rtc_s *) opaque; |
|
3455 int offset = addr & OMAP_MPUI_REG_MASK; |
|
3456 struct tm new_tm; |
|
3457 time_t ti[2]; |
|
3458 |
|
3459 switch (offset) { |
|
3460 case 0x00: /* SECONDS_REG */ |
|
3461 #ifdef ALMDEBUG |
|
3462 printf("RTC SEC_REG <-- %02x\n", value); |
|
3463 #endif |
|
3464 s->ti -= s->current_tm.tm_sec; |
|
3465 s->ti += omap_rtc_bin(value); |
|
3466 return; |
|
3467 |
|
3468 case 0x04: /* MINUTES_REG */ |
|
3469 #ifdef ALMDEBUG |
|
3470 printf("RTC MIN_REG <-- %02x\n", value); |
|
3471 #endif |
|
3472 s->ti -= s->current_tm.tm_min * 60; |
|
3473 s->ti += omap_rtc_bin(value) * 60; |
|
3474 return; |
|
3475 |
|
3476 case 0x08: /* HOURS_REG */ |
|
3477 #ifdef ALMDEBUG |
|
3478 printf("RTC HRS_REG <-- %02x\n", value); |
|
3479 #endif |
|
3480 s->ti -= s->current_tm.tm_hour * 3600; |
|
3481 if (s->pm_am) { |
|
3482 s->ti += (omap_rtc_bin(value & 0x3f) & 12) * 3600; |
|
3483 s->ti += ((value >> 7) & 1) * 43200; |
|
3484 } else |
|
3485 s->ti += omap_rtc_bin(value & 0x3f) * 3600; |
|
3486 return; |
|
3487 |
|
3488 case 0x0c: /* DAYS_REG */ |
|
3489 #ifdef ALMDEBUG |
|
3490 printf("RTC DAY_REG <-- %02x\n", value); |
|
3491 #endif |
|
3492 s->ti -= s->current_tm.tm_mday * 86400; |
|
3493 s->ti += omap_rtc_bin(value) * 86400; |
|
3494 return; |
|
3495 |
|
3496 case 0x10: /* MONTHS_REG */ |
|
3497 #ifdef ALMDEBUG |
|
3498 printf("RTC MTH_REG <-- %02x\n", value); |
|
3499 #endif |
|
3500 memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); |
|
3501 new_tm.tm_mon = omap_rtc_bin(value); |
|
3502 ti[0] = mktimegm(&s->current_tm); |
|
3503 ti[1] = mktimegm(&new_tm); |
|
3504 |
|
3505 if (ti[0] != -1 && ti[1] != -1) { |
|
3506 s->ti -= ti[0]; |
|
3507 s->ti += ti[1]; |
|
3508 } else { |
|
3509 /* A less accurate version */ |
|
3510 s->ti -= s->current_tm.tm_mon * 2592000; |
|
3511 s->ti += omap_rtc_bin(value) * 2592000; |
|
3512 } |
|
3513 return; |
|
3514 |
|
3515 case 0x14: /* YEARS_REG */ |
|
3516 #ifdef ALMDEBUG |
|
3517 printf("RTC YRS_REG <-- %02x\n", value); |
|
3518 #endif |
|
3519 memcpy(&new_tm, &s->current_tm, sizeof(new_tm)); |
|
3520 new_tm.tm_year += omap_rtc_bin(value) - (new_tm.tm_year % 100); |
|
3521 ti[0] = mktimegm(&s->current_tm); |
|
3522 ti[1] = mktimegm(&new_tm); |
|
3523 |
|
3524 if (ti[0] != -1 && ti[1] != -1) { |
|
3525 s->ti -= ti[0]; |
|
3526 s->ti += ti[1]; |
|
3527 } else { |
|
3528 /* A less accurate version */ |
|
3529 s->ti -= (s->current_tm.tm_year % 100) * 31536000; |
|
3530 s->ti += omap_rtc_bin(value) * 31536000; |
|
3531 } |
|
3532 return; |
|
3533 |
|
3534 case 0x18: /* WEEK_REG */ |
|
3535 return; /* Ignored */ |
|
3536 |
|
3537 case 0x20: /* ALARM_SECONDS_REG */ |
|
3538 #ifdef ALMDEBUG |
|
3539 printf("ALM SEC_REG <-- %02x\n", value); |
|
3540 #endif |
|
3541 s->alarm_tm.tm_sec = omap_rtc_bin(value); |
|
3542 omap_rtc_alarm_update(s); |
|
3543 return; |
|
3544 |
|
3545 case 0x24: /* ALARM_MINUTES_REG */ |
|
3546 #ifdef ALMDEBUG |
|
3547 printf("ALM MIN_REG <-- %02x\n", value); |
|
3548 #endif |
|
3549 s->alarm_tm.tm_min = omap_rtc_bin(value); |
|
3550 omap_rtc_alarm_update(s); |
|
3551 return; |
|
3552 |
|
3553 case 0x28: /* ALARM_HOURS_REG */ |
|
3554 #ifdef ALMDEBUG |
|
3555 printf("ALM HRS_REG <-- %02x\n", value); |
|
3556 #endif |
|
3557 if (s->pm_am) |
|
3558 s->alarm_tm.tm_hour = |
|
3559 ((omap_rtc_bin(value & 0x3f)) % 12) + |
|
3560 ((value >> 7) & 1) * 12; |
|
3561 else |
|
3562 s->alarm_tm.tm_hour = omap_rtc_bin(value); |
|
3563 omap_rtc_alarm_update(s); |
|
3564 return; |
|
3565 |
|
3566 case 0x2c: /* ALARM_DAYS_REG */ |
|
3567 #ifdef ALMDEBUG |
|
3568 printf("ALM DAY_REG <-- %02x\n", value); |
|
3569 #endif |
|
3570 s->alarm_tm.tm_mday = omap_rtc_bin(value); |
|
3571 omap_rtc_alarm_update(s); |
|
3572 return; |
|
3573 |
|
3574 case 0x30: /* ALARM_MONTHS_REG */ |
|
3575 #ifdef ALMDEBUG |
|
3576 printf("ALM MON_REG <-- %02x\n", value); |
|
3577 #endif |
|
3578 s->alarm_tm.tm_mon = omap_rtc_bin(value); |
|
3579 omap_rtc_alarm_update(s); |
|
3580 return; |
|
3581 |
|
3582 case 0x34: /* ALARM_YEARS_REG */ |
|
3583 #ifdef ALMDEBUG |
|
3584 printf("ALM YRS_REG <-- %02x\n", value); |
|
3585 #endif |
|
3586 s->alarm_tm.tm_year = omap_rtc_bin(value); |
|
3587 omap_rtc_alarm_update(s); |
|
3588 return; |
|
3589 |
|
3590 case 0x40: /* RTC_CTRL_REG */ |
|
3591 #ifdef ALMDEBUG |
|
3592 printf("RTC CONTROL <-- %02x\n", value); |
|
3593 #endif |
|
3594 s->pm_am = (value >> 3) & 1; |
|
3595 s->auto_comp = (value >> 2) & 1; |
|
3596 s->round = (value >> 1) & 1; |
|
3597 s->running = value & 1; |
|
3598 s->status &= 0xfd; |
|
3599 s->status |= s->running << 1; |
|
3600 return; |
|
3601 |
|
3602 case 0x44: /* RTC_STATUS_REG */ |
|
3603 #ifdef ALMDEBUG |
|
3604 printf("RTC STATUSL <-- %02x\n", value); |
|
3605 #endif |
|
3606 s->status &= ~((value & 0xc0) ^ 0x80); |
|
3607 omap_rtc_interrupts_update(s); |
|
3608 return; |
|
3609 |
|
3610 case 0x48: /* RTC_INTERRUPTS_REG */ |
|
3611 #ifdef ALMDEBUG |
|
3612 printf("RTC INTRS <-- %02x\n", value); |
|
3613 #endif |
|
3614 s->interrupts = value; |
|
3615 return; |
|
3616 |
|
3617 case 0x4c: /* RTC_COMP_LSB_REG */ |
|
3618 #ifdef ALMDEBUG |
|
3619 printf("RTC COMPLSB <-- %02x\n", value); |
|
3620 #endif |
|
3621 s->comp_reg &= 0xff00; |
|
3622 s->comp_reg |= 0x00ff & value; |
|
3623 return; |
|
3624 |
|
3625 case 0x50: /* RTC_COMP_MSB_REG */ |
|
3626 #ifdef ALMDEBUG |
|
3627 printf("RTC COMPMSB <-- %02x\n", value); |
|
3628 #endif |
|
3629 s->comp_reg &= 0x00ff; |
|
3630 s->comp_reg |= 0xff00 & (value << 8); |
|
3631 return; |
|
3632 |
|
3633 default: |
|
3634 OMAP_BAD_REG(addr); |
|
3635 return; |
|
3636 } |
|
3637 } |
|
3638 |
|
3639 static CPUReadMemoryFunc *omap_rtc_readfn[] = { |
|
3640 omap_rtc_read, |
|
3641 omap_badwidth_read8, |
|
3642 omap_badwidth_read8, |
|
3643 }; |
|
3644 |
|
3645 static CPUWriteMemoryFunc *omap_rtc_writefn[] = { |
|
3646 omap_rtc_write, |
|
3647 omap_badwidth_write8, |
|
3648 omap_badwidth_write8, |
|
3649 }; |
|
3650 |
|
3651 static void omap_rtc_tick(void *opaque) |
|
3652 { |
|
3653 struct omap_rtc_s *s = opaque; |
|
3654 |
|
3655 if (s->round) { |
|
3656 /* Round to nearest full minute. */ |
|
3657 if (s->current_tm.tm_sec < 30) |
|
3658 s->ti -= s->current_tm.tm_sec; |
|
3659 else |
|
3660 s->ti += 60 - s->current_tm.tm_sec; |
|
3661 |
|
3662 s->round = 0; |
|
3663 } |
|
3664 |
|
3665 memcpy(&s->current_tm, localtime(&s->ti), sizeof(s->current_tm)); |
|
3666 |
|
3667 if ((s->interrupts & 0x08) && s->ti == s->alarm_ti) { |
|
3668 s->status |= 0x40; |
|
3669 omap_rtc_interrupts_update(s); |
|
3670 } |
|
3671 |
|
3672 if (s->interrupts & 0x04) |
|
3673 switch (s->interrupts & 3) { |
|
3674 case 0: |
|
3675 s->status |= 0x04; |
|
3676 qemu_irq_pulse(s->irq); |
|
3677 break; |
|
3678 case 1: |
|
3679 if (s->current_tm.tm_sec) |
|
3680 break; |
|
3681 s->status |= 0x08; |
|
3682 qemu_irq_pulse(s->irq); |
|
3683 break; |
|
3684 case 2: |
|
3685 if (s->current_tm.tm_sec || s->current_tm.tm_min) |
|
3686 break; |
|
3687 s->status |= 0x10; |
|
3688 qemu_irq_pulse(s->irq); |
|
3689 break; |
|
3690 case 3: |
|
3691 if (s->current_tm.tm_sec || |
|
3692 s->current_tm.tm_min || s->current_tm.tm_hour) |
|
3693 break; |
|
3694 s->status |= 0x20; |
|
3695 qemu_irq_pulse(s->irq); |
|
3696 break; |
|
3697 } |
|
3698 |
|
3699 /* Move on */ |
|
3700 if (s->running) |
|
3701 s->ti ++; |
|
3702 s->tick += 1000; |
|
3703 |
|
3704 /* |
|
3705 * Every full hour add a rough approximation of the compensation |
|
3706 * register to the 32kHz Timer (which drives the RTC) value. |
|
3707 */ |
|
3708 if (s->auto_comp && !s->current_tm.tm_sec && !s->current_tm.tm_min) |
|
3709 s->tick += s->comp_reg * 1000 / 32768; |
|
3710 |
|
3711 qemu_mod_timer(s->clk, s->tick); |
|
3712 } |
|
3713 |
|
3714 static void omap_rtc_reset(struct omap_rtc_s *s) |
|
3715 { |
|
3716 struct tm tm; |
|
3717 |
|
3718 s->interrupts = 0; |
|
3719 s->comp_reg = 0; |
|
3720 s->running = 0; |
|
3721 s->pm_am = 0; |
|
3722 s->auto_comp = 0; |
|
3723 s->round = 0; |
|
3724 s->tick = qemu_get_clock(rt_clock); |
|
3725 memset(&s->alarm_tm, 0, sizeof(s->alarm_tm)); |
|
3726 s->alarm_tm.tm_mday = 0x01; |
|
3727 s->status = 1 << 7; |
|
3728 qemu_get_timedate(&tm, 0); |
|
3729 s->ti = mktimegm(&tm); |
|
3730 |
|
3731 omap_rtc_alarm_update(s); |
|
3732 omap_rtc_tick(s); |
|
3733 } |
|
3734 |
|
3735 struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base, |
|
3736 qemu_irq *irq, omap_clk clk) |
|
3737 { |
|
3738 int iomemtype; |
|
3739 struct omap_rtc_s *s = (struct omap_rtc_s *) |
|
3740 qemu_mallocz(sizeof(struct omap_rtc_s)); |
|
3741 |
|
3742 s->irq = irq[0]; |
|
3743 s->alarm = irq[1]; |
|
3744 s->clk = qemu_new_timer(rt_clock, omap_rtc_tick, s); |
|
3745 |
|
3746 omap_rtc_reset(s); |
|
3747 |
|
3748 iomemtype = cpu_register_io_memory(0, omap_rtc_readfn, |
|
3749 omap_rtc_writefn, s); |
|
3750 cpu_register_physical_memory(base, 0x800, iomemtype); |
|
3751 |
|
3752 return s; |
|
3753 } |
|
3754 |
|
3755 /* Multi-channel Buffered Serial Port interfaces */ |
|
3756 struct omap_mcbsp_s { |
|
3757 qemu_irq txirq; |
|
3758 qemu_irq rxirq; |
|
3759 qemu_irq txdrq; |
|
3760 qemu_irq rxdrq; |
|
3761 |
|
3762 uint16_t spcr[2]; |
|
3763 uint16_t rcr[2]; |
|
3764 uint16_t xcr[2]; |
|
3765 uint16_t srgr[2]; |
|
3766 uint16_t mcr[2]; |
|
3767 uint16_t pcr; |
|
3768 uint16_t rcer[8]; |
|
3769 uint16_t xcer[8]; |
|
3770 int tx_rate; |
|
3771 int rx_rate; |
|
3772 int tx_req; |
|
3773 int rx_req; |
|
3774 |
|
3775 struct i2s_codec_s *codec; |
|
3776 QEMUTimer *source_timer; |
|
3777 QEMUTimer *sink_timer; |
|
3778 }; |
|
3779 |
|
3780 static void omap_mcbsp_intr_update(struct omap_mcbsp_s *s) |
|
3781 { |
|
3782 int irq; |
|
3783 |
|
3784 switch ((s->spcr[0] >> 4) & 3) { /* RINTM */ |
|
3785 case 0: |
|
3786 irq = (s->spcr[0] >> 1) & 1; /* RRDY */ |
|
3787 break; |
|
3788 case 3: |
|
3789 irq = (s->spcr[0] >> 3) & 1; /* RSYNCERR */ |
|
3790 break; |
|
3791 default: |
|
3792 irq = 0; |
|
3793 break; |
|
3794 } |
|
3795 |
|
3796 if (irq) |
|
3797 qemu_irq_pulse(s->rxirq); |
|
3798 |
|
3799 switch ((s->spcr[1] >> 4) & 3) { /* XINTM */ |
|
3800 case 0: |
|
3801 irq = (s->spcr[1] >> 1) & 1; /* XRDY */ |
|
3802 break; |
|
3803 case 3: |
|
3804 irq = (s->spcr[1] >> 3) & 1; /* XSYNCERR */ |
|
3805 break; |
|
3806 default: |
|
3807 irq = 0; |
|
3808 break; |
|
3809 } |
|
3810 |
|
3811 if (irq) |
|
3812 qemu_irq_pulse(s->txirq); |
|
3813 } |
|
3814 |
|
3815 static void omap_mcbsp_rx_newdata(struct omap_mcbsp_s *s) |
|
3816 { |
|
3817 if ((s->spcr[0] >> 1) & 1) /* RRDY */ |
|
3818 s->spcr[0] |= 1 << 2; /* RFULL */ |
|
3819 s->spcr[0] |= 1 << 1; /* RRDY */ |
|
3820 qemu_irq_raise(s->rxdrq); |
|
3821 omap_mcbsp_intr_update(s); |
|
3822 } |
|
3823 |
|
3824 static void omap_mcbsp_source_tick(void *opaque) |
|
3825 { |
|
3826 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
|
3827 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; |
|
3828 |
|
3829 if (!s->rx_rate) |
|
3830 return; |
|
3831 if (s->rx_req) |
|
3832 printf("%s: Rx FIFO overrun\n", __FUNCTION__); |
|
3833 |
|
3834 s->rx_req = s->rx_rate << bps[(s->rcr[0] >> 5) & 7]; |
|
3835 |
|
3836 omap_mcbsp_rx_newdata(s); |
|
3837 qemu_mod_timer(s->source_timer, qemu_get_clock(vm_clock) + ticks_per_sec); |
|
3838 } |
|
3839 |
|
3840 static void omap_mcbsp_rx_start(struct omap_mcbsp_s *s) |
|
3841 { |
|
3842 if (!s->codec || !s->codec->rts) |
|
3843 omap_mcbsp_source_tick(s); |
|
3844 else if (s->codec->in.len) { |
|
3845 s->rx_req = s->codec->in.len; |
|
3846 omap_mcbsp_rx_newdata(s); |
|
3847 } |
|
3848 } |
|
3849 |
|
3850 static void omap_mcbsp_rx_stop(struct omap_mcbsp_s *s) |
|
3851 { |
|
3852 qemu_del_timer(s->source_timer); |
|
3853 } |
|
3854 |
|
3855 static void omap_mcbsp_rx_done(struct omap_mcbsp_s *s) |
|
3856 { |
|
3857 s->spcr[0] &= ~(1 << 1); /* RRDY */ |
|
3858 qemu_irq_lower(s->rxdrq); |
|
3859 omap_mcbsp_intr_update(s); |
|
3860 } |
|
3861 |
|
3862 static void omap_mcbsp_tx_newdata(struct omap_mcbsp_s *s) |
|
3863 { |
|
3864 s->spcr[1] |= 1 << 1; /* XRDY */ |
|
3865 qemu_irq_raise(s->txdrq); |
|
3866 omap_mcbsp_intr_update(s); |
|
3867 } |
|
3868 |
|
3869 static void omap_mcbsp_sink_tick(void *opaque) |
|
3870 { |
|
3871 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
|
3872 static const int bps[8] = { 0, 1, 1, 2, 2, 2, -255, -255 }; |
|
3873 |
|
3874 if (!s->tx_rate) |
|
3875 return; |
|
3876 if (s->tx_req) |
|
3877 printf("%s: Tx FIFO underrun\n", __FUNCTION__); |
|
3878 |
|
3879 s->tx_req = s->tx_rate << bps[(s->xcr[0] >> 5) & 7]; |
|
3880 |
|
3881 omap_mcbsp_tx_newdata(s); |
|
3882 qemu_mod_timer(s->sink_timer, qemu_get_clock(vm_clock) + ticks_per_sec); |
|
3883 } |
|
3884 |
|
3885 static void omap_mcbsp_tx_start(struct omap_mcbsp_s *s) |
|
3886 { |
|
3887 if (!s->codec || !s->codec->cts) |
|
3888 omap_mcbsp_sink_tick(s); |
|
3889 else if (s->codec->out.size) { |
|
3890 s->tx_req = s->codec->out.size; |
|
3891 omap_mcbsp_tx_newdata(s); |
|
3892 } |
|
3893 } |
|
3894 |
|
3895 static void omap_mcbsp_tx_done(struct omap_mcbsp_s *s) |
|
3896 { |
|
3897 s->spcr[1] &= ~(1 << 1); /* XRDY */ |
|
3898 qemu_irq_lower(s->txdrq); |
|
3899 omap_mcbsp_intr_update(s); |
|
3900 if (s->codec && s->codec->cts) |
|
3901 s->codec->tx_swallow(s->codec->opaque); |
|
3902 } |
|
3903 |
|
3904 static void omap_mcbsp_tx_stop(struct omap_mcbsp_s *s) |
|
3905 { |
|
3906 s->tx_req = 0; |
|
3907 omap_mcbsp_tx_done(s); |
|
3908 qemu_del_timer(s->sink_timer); |
|
3909 } |
|
3910 |
|
3911 static void omap_mcbsp_req_update(struct omap_mcbsp_s *s) |
|
3912 { |
|
3913 int prev_rx_rate, prev_tx_rate; |
|
3914 int rx_rate = 0, tx_rate = 0; |
|
3915 int cpu_rate = 1500000; /* XXX */ |
|
3916 |
|
3917 /* TODO: check CLKSTP bit */ |
|
3918 if (s->spcr[1] & (1 << 6)) { /* GRST */ |
|
3919 if (s->spcr[0] & (1 << 0)) { /* RRST */ |
|
3920 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ |
|
3921 (s->pcr & (1 << 8))) { /* CLKRM */ |
|
3922 if (~s->pcr & (1 << 7)) /* SCLKME */ |
|
3923 rx_rate = cpu_rate / |
|
3924 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ |
|
3925 } else |
|
3926 if (s->codec) |
|
3927 rx_rate = s->codec->rx_rate; |
|
3928 } |
|
3929 |
|
3930 if (s->spcr[1] & (1 << 0)) { /* XRST */ |
|
3931 if ((s->srgr[1] & (1 << 13)) && /* CLKSM */ |
|
3932 (s->pcr & (1 << 9))) { /* CLKXM */ |
|
3933 if (~s->pcr & (1 << 7)) /* SCLKME */ |
|
3934 tx_rate = cpu_rate / |
|
3935 ((s->srgr[0] & 0xff) + 1); /* CLKGDV */ |
|
3936 } else |
|
3937 if (s->codec) |
|
3938 tx_rate = s->codec->tx_rate; |
|
3939 } |
|
3940 } |
|
3941 prev_tx_rate = s->tx_rate; |
|
3942 prev_rx_rate = s->rx_rate; |
|
3943 s->tx_rate = tx_rate; |
|
3944 s->rx_rate = rx_rate; |
|
3945 |
|
3946 if (s->codec) |
|
3947 s->codec->set_rate(s->codec->opaque, rx_rate, tx_rate); |
|
3948 |
|
3949 if (!prev_tx_rate && tx_rate) |
|
3950 omap_mcbsp_tx_start(s); |
|
3951 else if (s->tx_rate && !tx_rate) |
|
3952 omap_mcbsp_tx_stop(s); |
|
3953 |
|
3954 if (!prev_rx_rate && rx_rate) |
|
3955 omap_mcbsp_rx_start(s); |
|
3956 else if (prev_tx_rate && !tx_rate) |
|
3957 omap_mcbsp_rx_stop(s); |
|
3958 } |
|
3959 |
|
3960 static uint32_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr) |
|
3961 { |
|
3962 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
|
3963 int offset = addr & OMAP_MPUI_REG_MASK; |
|
3964 uint16_t ret; |
|
3965 |
|
3966 switch (offset) { |
|
3967 case 0x00: /* DRR2 */ |
|
3968 if (((s->rcr[0] >> 5) & 7) < 3) /* RWDLEN1 */ |
|
3969 return 0x0000; |
|
3970 /* Fall through. */ |
|
3971 case 0x02: /* DRR1 */ |
|
3972 if (s->rx_req < 2) { |
|
3973 printf("%s: Rx FIFO underrun\n", __FUNCTION__); |
|
3974 omap_mcbsp_rx_done(s); |
|
3975 } else { |
|
3976 s->tx_req -= 2; |
|
3977 if (s->codec && s->codec->in.len >= 2) { |
|
3978 ret = s->codec->in.fifo[s->codec->in.start ++] << 8; |
|
3979 ret |= s->codec->in.fifo[s->codec->in.start ++]; |
|
3980 s->codec->in.len -= 2; |
|
3981 } else |
|
3982 ret = 0x0000; |
|
3983 if (!s->tx_req) |
|
3984 omap_mcbsp_rx_done(s); |
|
3985 return ret; |
|
3986 } |
|
3987 return 0x0000; |
|
3988 |
|
3989 case 0x04: /* DXR2 */ |
|
3990 case 0x06: /* DXR1 */ |
|
3991 return 0x0000; |
|
3992 |
|
3993 case 0x08: /* SPCR2 */ |
|
3994 return s->spcr[1]; |
|
3995 case 0x0a: /* SPCR1 */ |
|
3996 return s->spcr[0]; |
|
3997 case 0x0c: /* RCR2 */ |
|
3998 return s->rcr[1]; |
|
3999 case 0x0e: /* RCR1 */ |
|
4000 return s->rcr[0]; |
|
4001 case 0x10: /* XCR2 */ |
|
4002 return s->xcr[1]; |
|
4003 case 0x12: /* XCR1 */ |
|
4004 return s->xcr[0]; |
|
4005 case 0x14: /* SRGR2 */ |
|
4006 return s->srgr[1]; |
|
4007 case 0x16: /* SRGR1 */ |
|
4008 return s->srgr[0]; |
|
4009 case 0x18: /* MCR2 */ |
|
4010 return s->mcr[1]; |
|
4011 case 0x1a: /* MCR1 */ |
|
4012 return s->mcr[0]; |
|
4013 case 0x1c: /* RCERA */ |
|
4014 return s->rcer[0]; |
|
4015 case 0x1e: /* RCERB */ |
|
4016 return s->rcer[1]; |
|
4017 case 0x20: /* XCERA */ |
|
4018 return s->xcer[0]; |
|
4019 case 0x22: /* XCERB */ |
|
4020 return s->xcer[1]; |
|
4021 case 0x24: /* PCR0 */ |
|
4022 return s->pcr; |
|
4023 case 0x26: /* RCERC */ |
|
4024 return s->rcer[2]; |
|
4025 case 0x28: /* RCERD */ |
|
4026 return s->rcer[3]; |
|
4027 case 0x2a: /* XCERC */ |
|
4028 return s->xcer[2]; |
|
4029 case 0x2c: /* XCERD */ |
|
4030 return s->xcer[3]; |
|
4031 case 0x2e: /* RCERE */ |
|
4032 return s->rcer[4]; |
|
4033 case 0x30: /* RCERF */ |
|
4034 return s->rcer[5]; |
|
4035 case 0x32: /* XCERE */ |
|
4036 return s->xcer[4]; |
|
4037 case 0x34: /* XCERF */ |
|
4038 return s->xcer[5]; |
|
4039 case 0x36: /* RCERG */ |
|
4040 return s->rcer[6]; |
|
4041 case 0x38: /* RCERH */ |
|
4042 return s->rcer[7]; |
|
4043 case 0x3a: /* XCERG */ |
|
4044 return s->xcer[6]; |
|
4045 case 0x3c: /* XCERH */ |
|
4046 return s->xcer[7]; |
|
4047 } |
|
4048 |
|
4049 OMAP_BAD_REG(addr); |
|
4050 return 0; |
|
4051 } |
|
4052 |
|
4053 static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr, |
|
4054 uint32_t value) |
|
4055 { |
|
4056 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
|
4057 int offset = addr & OMAP_MPUI_REG_MASK; |
|
4058 |
|
4059 switch (offset) { |
|
4060 case 0x00: /* DRR2 */ |
|
4061 case 0x02: /* DRR1 */ |
|
4062 OMAP_RO_REG(addr); |
|
4063 return; |
|
4064 |
|
4065 case 0x04: /* DXR2 */ |
|
4066 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ |
|
4067 return; |
|
4068 /* Fall through. */ |
|
4069 case 0x06: /* DXR1 */ |
|
4070 if (s->tx_req > 1) { |
|
4071 s->tx_req -= 2; |
|
4072 if (s->codec && s->codec->cts) { |
|
4073 s->codec->out.fifo[s->codec->out.len ++] = (value >> 8) & 0xff; |
|
4074 s->codec->out.fifo[s->codec->out.len ++] = (value >> 0) & 0xff; |
|
4075 } |
|
4076 if (s->tx_req < 2) |
|
4077 omap_mcbsp_tx_done(s); |
|
4078 } else |
|
4079 printf("%s: Tx FIFO overrun\n", __FUNCTION__); |
|
4080 return; |
|
4081 |
|
4082 case 0x08: /* SPCR2 */ |
|
4083 s->spcr[1] &= 0x0002; |
|
4084 s->spcr[1] |= 0x03f9 & value; |
|
4085 s->spcr[1] |= 0x0004 & (value << 2); /* XEMPTY := XRST */ |
|
4086 if (~value & 1) /* XRST */ |
|
4087 s->spcr[1] &= ~6; |
|
4088 omap_mcbsp_req_update(s); |
|
4089 return; |
|
4090 case 0x0a: /* SPCR1 */ |
|
4091 s->spcr[0] &= 0x0006; |
|
4092 s->spcr[0] |= 0xf8f9 & value; |
|
4093 if (value & (1 << 15)) /* DLB */ |
|
4094 printf("%s: Digital Loopback mode enable attempt\n", __FUNCTION__); |
|
4095 if (~value & 1) { /* RRST */ |
|
4096 s->spcr[0] &= ~6; |
|
4097 s->rx_req = 0; |
|
4098 omap_mcbsp_rx_done(s); |
|
4099 } |
|
4100 omap_mcbsp_req_update(s); |
|
4101 return; |
|
4102 |
|
4103 case 0x0c: /* RCR2 */ |
|
4104 s->rcr[1] = value & 0xffff; |
|
4105 return; |
|
4106 case 0x0e: /* RCR1 */ |
|
4107 s->rcr[0] = value & 0x7fe0; |
|
4108 return; |
|
4109 case 0x10: /* XCR2 */ |
|
4110 s->xcr[1] = value & 0xffff; |
|
4111 return; |
|
4112 case 0x12: /* XCR1 */ |
|
4113 s->xcr[0] = value & 0x7fe0; |
|
4114 return; |
|
4115 case 0x14: /* SRGR2 */ |
|
4116 s->srgr[1] = value & 0xffff; |
|
4117 omap_mcbsp_req_update(s); |
|
4118 return; |
|
4119 case 0x16: /* SRGR1 */ |
|
4120 s->srgr[0] = value & 0xffff; |
|
4121 omap_mcbsp_req_update(s); |
|
4122 return; |
|
4123 case 0x18: /* MCR2 */ |
|
4124 s->mcr[1] = value & 0x03e3; |
|
4125 if (value & 3) /* XMCM */ |
|
4126 printf("%s: Tx channel selection mode enable attempt\n", |
|
4127 __FUNCTION__); |
|
4128 return; |
|
4129 case 0x1a: /* MCR1 */ |
|
4130 s->mcr[0] = value & 0x03e1; |
|
4131 if (value & 1) /* RMCM */ |
|
4132 printf("%s: Rx channel selection mode enable attempt\n", |
|
4133 __FUNCTION__); |
|
4134 return; |
|
4135 case 0x1c: /* RCERA */ |
|
4136 s->rcer[0] = value & 0xffff; |
|
4137 return; |
|
4138 case 0x1e: /* RCERB */ |
|
4139 s->rcer[1] = value & 0xffff; |
|
4140 return; |
|
4141 case 0x20: /* XCERA */ |
|
4142 s->xcer[0] = value & 0xffff; |
|
4143 return; |
|
4144 case 0x22: /* XCERB */ |
|
4145 s->xcer[1] = value & 0xffff; |
|
4146 return; |
|
4147 case 0x24: /* PCR0 */ |
|
4148 s->pcr = value & 0x7faf; |
|
4149 return; |
|
4150 case 0x26: /* RCERC */ |
|
4151 s->rcer[2] = value & 0xffff; |
|
4152 return; |
|
4153 case 0x28: /* RCERD */ |
|
4154 s->rcer[3] = value & 0xffff; |
|
4155 return; |
|
4156 case 0x2a: /* XCERC */ |
|
4157 s->xcer[2] = value & 0xffff; |
|
4158 return; |
|
4159 case 0x2c: /* XCERD */ |
|
4160 s->xcer[3] = value & 0xffff; |
|
4161 return; |
|
4162 case 0x2e: /* RCERE */ |
|
4163 s->rcer[4] = value & 0xffff; |
|
4164 return; |
|
4165 case 0x30: /* RCERF */ |
|
4166 s->rcer[5] = value & 0xffff; |
|
4167 return; |
|
4168 case 0x32: /* XCERE */ |
|
4169 s->xcer[4] = value & 0xffff; |
|
4170 return; |
|
4171 case 0x34: /* XCERF */ |
|
4172 s->xcer[5] = value & 0xffff; |
|
4173 return; |
|
4174 case 0x36: /* RCERG */ |
|
4175 s->rcer[6] = value & 0xffff; |
|
4176 return; |
|
4177 case 0x38: /* RCERH */ |
|
4178 s->rcer[7] = value & 0xffff; |
|
4179 return; |
|
4180 case 0x3a: /* XCERG */ |
|
4181 s->xcer[6] = value & 0xffff; |
|
4182 return; |
|
4183 case 0x3c: /* XCERH */ |
|
4184 s->xcer[7] = value & 0xffff; |
|
4185 return; |
|
4186 } |
|
4187 |
|
4188 OMAP_BAD_REG(addr); |
|
4189 } |
|
4190 |
|
4191 static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr, |
|
4192 uint32_t value) |
|
4193 { |
|
4194 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
|
4195 int offset = addr & OMAP_MPUI_REG_MASK; |
|
4196 |
|
4197 if (offset == 0x04) { /* DXR */ |
|
4198 if (((s->xcr[0] >> 5) & 7) < 3) /* XWDLEN1 */ |
|
4199 return; |
|
4200 if (s->tx_req > 3) { |
|
4201 s->tx_req -= 4; |
|
4202 if (s->codec && s->codec->cts) { |
|
4203 s->codec->out.fifo[s->codec->out.len ++] = |
|
4204 (value >> 24) & 0xff; |
|
4205 s->codec->out.fifo[s->codec->out.len ++] = |
|
4206 (value >> 16) & 0xff; |
|
4207 s->codec->out.fifo[s->codec->out.len ++] = |
|
4208 (value >> 8) & 0xff; |
|
4209 s->codec->out.fifo[s->codec->out.len ++] = |
|
4210 (value >> 0) & 0xff; |
|
4211 } |
|
4212 if (s->tx_req < 4) |
|
4213 omap_mcbsp_tx_done(s); |
|
4214 } else |
|
4215 printf("%s: Tx FIFO overrun\n", __FUNCTION__); |
|
4216 return; |
|
4217 } |
|
4218 |
|
4219 omap_badwidth_write16(opaque, addr, value); |
|
4220 } |
|
4221 |
|
4222 static CPUReadMemoryFunc *omap_mcbsp_readfn[] = { |
|
4223 omap_badwidth_read16, |
|
4224 omap_mcbsp_read, |
|
4225 omap_badwidth_read16, |
|
4226 }; |
|
4227 |
|
4228 static CPUWriteMemoryFunc *omap_mcbsp_writefn[] = { |
|
4229 omap_badwidth_write16, |
|
4230 omap_mcbsp_writeh, |
|
4231 omap_mcbsp_writew, |
|
4232 }; |
|
4233 |
|
4234 static void omap_mcbsp_reset(struct omap_mcbsp_s *s) |
|
4235 { |
|
4236 memset(&s->spcr, 0, sizeof(s->spcr)); |
|
4237 memset(&s->rcr, 0, sizeof(s->rcr)); |
|
4238 memset(&s->xcr, 0, sizeof(s->xcr)); |
|
4239 s->srgr[0] = 0x0001; |
|
4240 s->srgr[1] = 0x2000; |
|
4241 memset(&s->mcr, 0, sizeof(s->mcr)); |
|
4242 memset(&s->pcr, 0, sizeof(s->pcr)); |
|
4243 memset(&s->rcer, 0, sizeof(s->rcer)); |
|
4244 memset(&s->xcer, 0, sizeof(s->xcer)); |
|
4245 s->tx_req = 0; |
|
4246 s->rx_req = 0; |
|
4247 s->tx_rate = 0; |
|
4248 s->rx_rate = 0; |
|
4249 qemu_del_timer(s->source_timer); |
|
4250 qemu_del_timer(s->sink_timer); |
|
4251 } |
|
4252 |
|
4253 struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base, |
|
4254 qemu_irq *irq, qemu_irq *dma, omap_clk clk) |
|
4255 { |
|
4256 int iomemtype; |
|
4257 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) |
|
4258 qemu_mallocz(sizeof(struct omap_mcbsp_s)); |
|
4259 |
|
4260 s->txirq = irq[0]; |
|
4261 s->rxirq = irq[1]; |
|
4262 s->txdrq = dma[0]; |
|
4263 s->rxdrq = dma[1]; |
|
4264 s->sink_timer = qemu_new_timer(vm_clock, omap_mcbsp_sink_tick, s); |
|
4265 s->source_timer = qemu_new_timer(vm_clock, omap_mcbsp_source_tick, s); |
|
4266 omap_mcbsp_reset(s); |
|
4267 |
|
4268 iomemtype = cpu_register_io_memory(0, omap_mcbsp_readfn, |
|
4269 omap_mcbsp_writefn, s); |
|
4270 cpu_register_physical_memory(base, 0x800, iomemtype); |
|
4271 |
|
4272 return s; |
|
4273 } |
|
4274 |
|
4275 static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level) |
|
4276 { |
|
4277 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
|
4278 |
|
4279 if (s->rx_rate) { |
|
4280 s->rx_req = s->codec->in.len; |
|
4281 omap_mcbsp_rx_newdata(s); |
|
4282 } |
|
4283 } |
|
4284 |
|
4285 static void omap_mcbsp_i2s_start(void *opaque, int line, int level) |
|
4286 { |
|
4287 struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque; |
|
4288 |
|
4289 if (s->tx_rate) { |
|
4290 s->tx_req = s->codec->out.size; |
|
4291 omap_mcbsp_tx_newdata(s); |
|
4292 } |
|
4293 } |
|
4294 |
|
4295 void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave) |
|
4296 { |
|
4297 s->codec = slave; |
|
4298 slave->rx_swallow = qemu_allocate_irqs(omap_mcbsp_i2s_swallow, s, 1)[0]; |
|
4299 slave->tx_start = qemu_allocate_irqs(omap_mcbsp_i2s_start, s, 1)[0]; |
|
4300 } |
|
4301 |
|
4302 /* LED Pulse Generators */ |
|
4303 struct omap_lpg_s { |
|
4304 QEMUTimer *tm; |
|
4305 |
|
4306 uint8_t control; |
|
4307 uint8_t power; |
|
4308 int64_t on; |
|
4309 int64_t period; |
|
4310 int clk; |
|
4311 int cycle; |
|
4312 }; |
|
4313 |
|
4314 static void omap_lpg_tick(void *opaque) |
|
4315 { |
|
4316 struct omap_lpg_s *s = opaque; |
|
4317 |
|
4318 if (s->cycle) |
|
4319 qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->period - s->on); |
|
4320 else |
|
4321 qemu_mod_timer(s->tm, qemu_get_clock(rt_clock) + s->on); |
|
4322 |
|
4323 s->cycle = !s->cycle; |
|
4324 printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off"); |
|
4325 } |
|
4326 |
|
4327 static void omap_lpg_update(struct omap_lpg_s *s) |
|
4328 { |
|
4329 int64_t on, period = 1, ticks = 1000; |
|
4330 static const int per[8] = { 1, 2, 4, 8, 12, 16, 20, 24 }; |
|
4331 |
|
4332 if (~s->control & (1 << 6)) /* LPGRES */ |
|
4333 on = 0; |
|
4334 else if (s->control & (1 << 7)) /* PERM_ON */ |
|
4335 on = period; |
|
4336 else { |
|
4337 period = muldiv64(ticks, per[s->control & 7], /* PERCTRL */ |
|
4338 256 / 32); |
|
4339 on = (s->clk && s->power) ? muldiv64(ticks, |
|
4340 per[(s->control >> 3) & 7], 256) : 0; /* ONCTRL */ |
|
4341 } |
|
4342 |
|
4343 qemu_del_timer(s->tm); |
|
4344 if (on == period && s->on < s->period) |
|
4345 printf("%s: LED is on\n", __FUNCTION__); |
|
4346 else if (on == 0 && s->on) |
|
4347 printf("%s: LED is off\n", __FUNCTION__); |
|
4348 else if (on && (on != s->on || period != s->period)) { |
|
4349 s->cycle = 0; |
|
4350 s->on = on; |
|
4351 s->period = period; |
|
4352 omap_lpg_tick(s); |
|
4353 return; |
|
4354 } |
|
4355 |
|
4356 s->on = on; |
|
4357 s->period = period; |
|
4358 } |
|
4359 |
|
4360 static void omap_lpg_reset(struct omap_lpg_s *s) |
|
4361 { |
|
4362 s->control = 0x00; |
|
4363 s->power = 0x00; |
|
4364 s->clk = 1; |
|
4365 omap_lpg_update(s); |
|
4366 } |
|
4367 |
|
4368 static uint32_t omap_lpg_read(void *opaque, target_phys_addr_t addr) |
|
4369 { |
|
4370 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; |
|
4371 int offset = addr & OMAP_MPUI_REG_MASK; |
|
4372 |
|
4373 switch (offset) { |
|
4374 case 0x00: /* LCR */ |
|
4375 return s->control; |
|
4376 |
|
4377 case 0x04: /* PMR */ |
|
4378 return s->power; |
|
4379 } |
|
4380 |
|
4381 OMAP_BAD_REG(addr); |
|
4382 return 0; |
|
4383 } |
|
4384 |
|
4385 static void omap_lpg_write(void *opaque, target_phys_addr_t addr, |
|
4386 uint32_t value) |
|
4387 { |
|
4388 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; |
|
4389 int offset = addr & OMAP_MPUI_REG_MASK; |
|
4390 |
|
4391 switch (offset) { |
|
4392 case 0x00: /* LCR */ |
|
4393 if (~value & (1 << 6)) /* LPGRES */ |
|
4394 omap_lpg_reset(s); |
|
4395 s->control = value & 0xff; |
|
4396 omap_lpg_update(s); |
|
4397 return; |
|
4398 |
|
4399 case 0x04: /* PMR */ |
|
4400 s->power = value & 0x01; |
|
4401 omap_lpg_update(s); |
|
4402 return; |
|
4403 |
|
4404 default: |
|
4405 OMAP_BAD_REG(addr); |
|
4406 return; |
|
4407 } |
|
4408 } |
|
4409 |
|
4410 static CPUReadMemoryFunc *omap_lpg_readfn[] = { |
|
4411 omap_lpg_read, |
|
4412 omap_badwidth_read8, |
|
4413 omap_badwidth_read8, |
|
4414 }; |
|
4415 |
|
4416 static CPUWriteMemoryFunc *omap_lpg_writefn[] = { |
|
4417 omap_lpg_write, |
|
4418 omap_badwidth_write8, |
|
4419 omap_badwidth_write8, |
|
4420 }; |
|
4421 |
|
4422 static void omap_lpg_clk_update(void *opaque, int line, int on) |
|
4423 { |
|
4424 struct omap_lpg_s *s = (struct omap_lpg_s *) opaque; |
|
4425 |
|
4426 s->clk = on; |
|
4427 omap_lpg_update(s); |
|
4428 } |
|
4429 |
|
4430 struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk) |
|
4431 { |
|
4432 int iomemtype; |
|
4433 struct omap_lpg_s *s = (struct omap_lpg_s *) |
|
4434 qemu_mallocz(sizeof(struct omap_lpg_s)); |
|
4435 |
|
4436 s->tm = qemu_new_timer(rt_clock, omap_lpg_tick, s); |
|
4437 |
|
4438 omap_lpg_reset(s); |
|
4439 |
|
4440 iomemtype = cpu_register_io_memory(0, omap_lpg_readfn, |
|
4441 omap_lpg_writefn, s); |
|
4442 cpu_register_physical_memory(base, 0x800, iomemtype); |
|
4443 |
|
4444 omap_clk_adduser(clk, qemu_allocate_irqs(omap_lpg_clk_update, s, 1)[0]); |
|
4445 |
|
4446 return s; |
|
4447 } |
|
4448 |
|
4449 /* MPUI Peripheral Bridge configuration */ |
|
4450 static uint32_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr) |
|
4451 { |
|
4452 if (addr == OMAP_MPUI_BASE) /* CMR */ |
|
4453 return 0xfe4d; |
|
4454 |
|
4455 OMAP_BAD_REG(addr); |
|
4456 return 0; |
|
4457 } |
|
4458 |
|
4459 static CPUReadMemoryFunc *omap_mpui_io_readfn[] = { |
|
4460 omap_badwidth_read16, |
|
4461 omap_mpui_io_read, |
|
4462 omap_badwidth_read16, |
|
4463 }; |
|
4464 |
|
4465 static CPUWriteMemoryFunc *omap_mpui_io_writefn[] = { |
|
4466 omap_badwidth_write16, |
|
4467 omap_badwidth_write16, |
|
4468 omap_badwidth_write16, |
|
4469 }; |
|
4470 |
|
4471 static void omap_setup_mpui_io(struct omap_mpu_state_s *mpu) |
|
4472 { |
|
4473 int iomemtype = cpu_register_io_memory(0, omap_mpui_io_readfn, |
|
4474 omap_mpui_io_writefn, mpu); |
|
4475 cpu_register_physical_memory(OMAP_MPUI_BASE, 0x7fff, iomemtype); |
|
4476 } |
|
4477 |
|
4478 /* General chip reset */ |
|
4479 static void omap1_mpu_reset(void *opaque) |
|
4480 { |
|
4481 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; |
|
4482 |
|
4483 omap_inth_reset(mpu->ih[0]); |
|
4484 omap_inth_reset(mpu->ih[1]); |
|
4485 omap_dma_reset(mpu->dma); |
|
4486 omap_mpu_timer_reset(mpu->timer[0]); |
|
4487 omap_mpu_timer_reset(mpu->timer[1]); |
|
4488 omap_mpu_timer_reset(mpu->timer[2]); |
|
4489 omap_wd_timer_reset(mpu->wdt); |
|
4490 omap_os_timer_reset(mpu->os_timer); |
|
4491 omap_lcdc_reset(mpu->lcd); |
|
4492 omap_ulpd_pm_reset(mpu); |
|
4493 omap_pin_cfg_reset(mpu); |
|
4494 omap_mpui_reset(mpu); |
|
4495 omap_tipb_bridge_reset(mpu->private_tipb); |
|
4496 omap_tipb_bridge_reset(mpu->public_tipb); |
|
4497 omap_dpll_reset(&mpu->dpll[0]); |
|
4498 omap_dpll_reset(&mpu->dpll[1]); |
|
4499 omap_dpll_reset(&mpu->dpll[2]); |
|
4500 omap_uart_reset(mpu->uart[0]); |
|
4501 omap_uart_reset(mpu->uart[1]); |
|
4502 omap_uart_reset(mpu->uart[2]); |
|
4503 omap_mmc_reset(mpu->mmc); |
|
4504 omap_mpuio_reset(mpu->mpuio); |
|
4505 omap_gpio_reset(mpu->gpio); |
|
4506 omap_uwire_reset(mpu->microwire); |
|
4507 omap_pwl_reset(mpu); |
|
4508 omap_pwt_reset(mpu); |
|
4509 omap_i2c_reset(mpu->i2c[0]); |
|
4510 omap_rtc_reset(mpu->rtc); |
|
4511 omap_mcbsp_reset(mpu->mcbsp1); |
|
4512 omap_mcbsp_reset(mpu->mcbsp2); |
|
4513 omap_mcbsp_reset(mpu->mcbsp3); |
|
4514 omap_lpg_reset(mpu->led[0]); |
|
4515 omap_lpg_reset(mpu->led[1]); |
|
4516 omap_clkm_reset(mpu); |
|
4517 cpu_reset(mpu->env); |
|
4518 } |
|
4519 |
|
4520 static const struct omap_map_s { |
|
4521 target_phys_addr_t phys_dsp; |
|
4522 target_phys_addr_t phys_mpu; |
|
4523 uint32_t size; |
|
4524 const char *name; |
|
4525 } omap15xx_dsp_mm[] = { |
|
4526 /* Strobe 0 */ |
|
4527 { 0xe1010000, 0xfffb0000, 0x800, "UART1 BT" }, /* CS0 */ |
|
4528 { 0xe1010800, 0xfffb0800, 0x800, "UART2 COM" }, /* CS1 */ |
|
4529 { 0xe1011800, 0xfffb1800, 0x800, "McBSP1 audio" }, /* CS3 */ |
|
4530 { 0xe1012000, 0xfffb2000, 0x800, "MCSI2 communication" }, /* CS4 */ |
|
4531 { 0xe1012800, 0xfffb2800, 0x800, "MCSI1 BT u-Law" }, /* CS5 */ |
|
4532 { 0xe1013000, 0xfffb3000, 0x800, "uWire" }, /* CS6 */ |
|
4533 { 0xe1013800, 0xfffb3800, 0x800, "I^2C" }, /* CS7 */ |
|
4534 { 0xe1014000, 0xfffb4000, 0x800, "USB W2FC" }, /* CS8 */ |
|
4535 { 0xe1014800, 0xfffb4800, 0x800, "RTC" }, /* CS9 */ |
|
4536 { 0xe1015000, 0xfffb5000, 0x800, "MPUIO" }, /* CS10 */ |
|
4537 { 0xe1015800, 0xfffb5800, 0x800, "PWL" }, /* CS11 */ |
|
4538 { 0xe1016000, 0xfffb6000, 0x800, "PWT" }, /* CS12 */ |
|
4539 { 0xe1017000, 0xfffb7000, 0x800, "McBSP3" }, /* CS14 */ |
|
4540 { 0xe1017800, 0xfffb7800, 0x800, "MMC" }, /* CS15 */ |
|
4541 { 0xe1019000, 0xfffb9000, 0x800, "32-kHz timer" }, /* CS18 */ |
|
4542 { 0xe1019800, 0xfffb9800, 0x800, "UART3" }, /* CS19 */ |
|
4543 { 0xe101c800, 0xfffbc800, 0x800, "TIPB switches" }, /* CS25 */ |
|
4544 /* Strobe 1 */ |
|
4545 { 0xe101e000, 0xfffce000, 0x800, "GPIOs" }, /* CS28 */ |
|
4546 |
|
4547 { 0 } |
|
4548 }; |
|
4549 |
|
4550 static void omap_setup_dsp_mapping(const struct omap_map_s *map) |
|
4551 { |
|
4552 int io; |
|
4553 |
|
4554 for (; map->phys_dsp; map ++) { |
|
4555 io = cpu_get_physical_page_desc(map->phys_mpu); |
|
4556 |
|
4557 cpu_register_physical_memory(map->phys_dsp, map->size, io); |
|
4558 } |
|
4559 } |
|
4560 |
|
4561 void omap_mpu_wakeup(void *opaque, int irq, int req) |
|
4562 { |
|
4563 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; |
|
4564 |
|
4565 if (mpu->env->halted) |
|
4566 cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB); |
|
4567 } |
|
4568 |
|
4569 static const struct dma_irq_map omap1_dma_irq_map[] = { |
|
4570 { 0, OMAP_INT_DMA_CH0_6 }, |
|
4571 { 0, OMAP_INT_DMA_CH1_7 }, |
|
4572 { 0, OMAP_INT_DMA_CH2_8 }, |
|
4573 { 0, OMAP_INT_DMA_CH3 }, |
|
4574 { 0, OMAP_INT_DMA_CH4 }, |
|
4575 { 0, OMAP_INT_DMA_CH5 }, |
|
4576 { 1, OMAP_INT_1610_DMA_CH6 }, |
|
4577 { 1, OMAP_INT_1610_DMA_CH7 }, |
|
4578 { 1, OMAP_INT_1610_DMA_CH8 }, |
|
4579 { 1, OMAP_INT_1610_DMA_CH9 }, |
|
4580 { 1, OMAP_INT_1610_DMA_CH10 }, |
|
4581 { 1, OMAP_INT_1610_DMA_CH11 }, |
|
4582 { 1, OMAP_INT_1610_DMA_CH12 }, |
|
4583 { 1, OMAP_INT_1610_DMA_CH13 }, |
|
4584 { 1, OMAP_INT_1610_DMA_CH14 }, |
|
4585 { 1, OMAP_INT_1610_DMA_CH15 } |
|
4586 }; |
|
4587 |
|
4588 /* DMA ports for OMAP1 */ |
|
4589 static int omap_validate_emiff_addr(struct omap_mpu_state_s *s, |
|
4590 target_phys_addr_t addr) |
|
4591 { |
|
4592 return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size; |
|
4593 } |
|
4594 |
|
4595 static int omap_validate_emifs_addr(struct omap_mpu_state_s *s, |
|
4596 target_phys_addr_t addr) |
|
4597 { |
|
4598 return addr >= OMAP_EMIFS_BASE && addr < OMAP_EMIFF_BASE; |
|
4599 } |
|
4600 |
|
4601 static int omap_validate_imif_addr(struct omap_mpu_state_s *s, |
|
4602 target_phys_addr_t addr) |
|
4603 { |
|
4604 return addr >= OMAP_IMIF_BASE && addr < OMAP_IMIF_BASE + s->sram_size; |
|
4605 } |
|
4606 |
|
4607 static int omap_validate_tipb_addr(struct omap_mpu_state_s *s, |
|
4608 target_phys_addr_t addr) |
|
4609 { |
|
4610 return addr >= 0xfffb0000 && addr < 0xffff0000; |
|
4611 } |
|
4612 |
|
4613 static int omap_validate_local_addr(struct omap_mpu_state_s *s, |
|
4614 target_phys_addr_t addr) |
|
4615 { |
|
4616 return addr >= OMAP_LOCALBUS_BASE && addr < OMAP_LOCALBUS_BASE + 0x1000000; |
|
4617 } |
|
4618 |
|
4619 static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s, |
|
4620 target_phys_addr_t addr) |
|
4621 { |
|
4622 return addr >= 0xe1010000 && addr < 0xe1020004; |
|
4623 } |
|
4624 |
|
4625 struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size, |
|
4626 DisplayState *ds, const char *core) |
|
4627 { |
|
4628 int i; |
|
4629 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) |
|
4630 qemu_mallocz(sizeof(struct omap_mpu_state_s)); |
|
4631 ram_addr_t imif_base, emiff_base; |
|
4632 qemu_irq *cpu_irq; |
|
4633 qemu_irq dma_irqs[6]; |
|
4634 int sdindex; |
|
4635 |
|
4636 if (!core) |
|
4637 core = "ti925t"; |
|
4638 |
|
4639 /* Core */ |
|
4640 s->mpu_model = omap310; |
|
4641 s->env = cpu_init(core); |
|
4642 if (!s->env) { |
|
4643 fprintf(stderr, "Unable to find CPU definition\n"); |
|
4644 exit(1); |
|
4645 } |
|
4646 s->sdram_size = sdram_size; |
|
4647 s->sram_size = OMAP15XX_SRAM_SIZE; |
|
4648 |
|
4649 s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0]; |
|
4650 |
|
4651 /* Clocks */ |
|
4652 omap_clk_init(s); |
|
4653 |
|
4654 /* Memory-mapped stuff */ |
|
4655 cpu_register_physical_memory(OMAP_EMIFF_BASE, s->sdram_size, |
|
4656 (emiff_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM); |
|
4657 cpu_register_physical_memory(OMAP_IMIF_BASE, s->sram_size, |
|
4658 (imif_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM); |
|
4659 |
|
4660 omap_clkm_init(0xfffece00, 0xe1008000, s); |
|
4661 |
|
4662 cpu_irq = arm_pic_init_cpu(s->env); |
|
4663 s->ih[0] = omap_inth_init(0xfffecb00, 0x100, 1, &s->irq[0], |
|
4664 cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ], |
|
4665 omap_findclk(s, "arminth_ck")); |
|
4666 s->ih[1] = omap_inth_init(0xfffe0000, 0x800, 1, &s->irq[1], |
|
4667 s->ih[0]->pins[OMAP_INT_15XX_IH2_IRQ], NULL, |
|
4668 omap_findclk(s, "arminth_ck")); |
|
4669 |
|
4670 for (i = 0; i < 6; i ++) |
|
4671 dma_irqs[i] = |
|
4672 s->irq[omap1_dma_irq_map[i].ih][omap1_dma_irq_map[i].intr]; |
|
4673 s->dma = omap_dma_init(0xfffed800, dma_irqs, s->irq[0][OMAP_INT_DMA_LCD], |
|
4674 s, omap_findclk(s, "dma_ck"), omap_dma_3_1); |
|
4675 |
|
4676 s->port[emiff ].addr_valid = omap_validate_emiff_addr; |
|
4677 s->port[emifs ].addr_valid = omap_validate_emifs_addr; |
|
4678 s->port[imif ].addr_valid = omap_validate_imif_addr; |
|
4679 s->port[tipb ].addr_valid = omap_validate_tipb_addr; |
|
4680 s->port[local ].addr_valid = omap_validate_local_addr; |
|
4681 s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr; |
|
4682 |
|
4683 /* Register SDRAM and SRAM DMA ports for fast transfers. */ |
|
4684 soc_dma_port_add_mem_ram(s->dma, |
|
4685 emiff_base, OMAP_EMIFF_BASE, s->sdram_size); |
|
4686 soc_dma_port_add_mem_ram(s->dma, |
|
4687 imif_base, OMAP_IMIF_BASE, s->sram_size); |
|
4688 |
|
4689 s->timer[0] = omap_mpu_timer_init(0xfffec500, |
|
4690 s->irq[0][OMAP_INT_TIMER1], |
|
4691 omap_findclk(s, "mputim_ck")); |
|
4692 s->timer[1] = omap_mpu_timer_init(0xfffec600, |
|
4693 s->irq[0][OMAP_INT_TIMER2], |
|
4694 omap_findclk(s, "mputim_ck")); |
|
4695 s->timer[2] = omap_mpu_timer_init(0xfffec700, |
|
4696 s->irq[0][OMAP_INT_TIMER3], |
|
4697 omap_findclk(s, "mputim_ck")); |
|
4698 |
|
4699 s->wdt = omap_wd_timer_init(0xfffec800, |
|
4700 s->irq[0][OMAP_INT_WD_TIMER], |
|
4701 omap_findclk(s, "armwdt_ck")); |
|
4702 |
|
4703 s->os_timer = omap_os_timer_init(0xfffb9000, |
|
4704 s->irq[1][OMAP_INT_OS_TIMER], |
|
4705 omap_findclk(s, "clk32-kHz")); |
|
4706 |
|
4707 s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL], |
|
4708 omap_dma_get_lcdch(s->dma), ds, imif_base, emiff_base, |
|
4709 omap_findclk(s, "lcd_ck")); |
|
4710 |
|
4711 omap_ulpd_pm_init(0xfffe0800, s); |
|
4712 omap_pin_cfg_init(0xfffe1000, s); |
|
4713 omap_id_init(s); |
|
4714 |
|
4715 omap_mpui_init(0xfffec900, s); |
|
4716 |
|
4717 s->private_tipb = omap_tipb_bridge_init(0xfffeca00, |
|
4718 s->irq[0][OMAP_INT_BRIDGE_PRIV], |
|
4719 omap_findclk(s, "tipb_ck")); |
|
4720 s->public_tipb = omap_tipb_bridge_init(0xfffed300, |
|
4721 s->irq[0][OMAP_INT_BRIDGE_PUB], |
|
4722 omap_findclk(s, "tipb_ck")); |
|
4723 |
|
4724 omap_tcmi_init(0xfffecc00, s); |
|
4725 |
|
4726 s->uart[0] = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1], |
|
4727 omap_findclk(s, "uart1_ck"), |
|
4728 omap_findclk(s, "uart1_ck"), |
|
4729 s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX], |
|
4730 serial_hds[0]); |
|
4731 s->uart[1] = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2], |
|
4732 omap_findclk(s, "uart2_ck"), |
|
4733 omap_findclk(s, "uart2_ck"), |
|
4734 s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX], |
|
4735 serial_hds[0] ? serial_hds[1] : 0); |
|
4736 s->uart[2] = omap_uart_init(0xfffb9800, s->irq[0][OMAP_INT_UART3], |
|
4737 omap_findclk(s, "uart3_ck"), |
|
4738 omap_findclk(s, "uart3_ck"), |
|
4739 s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX], |
|
4740 serial_hds[0] && serial_hds[1] ? serial_hds[2] : 0); |
|
4741 |
|
4742 omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1")); |
|
4743 omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2")); |
|
4744 omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3")); |
|
4745 |
|
4746 sdindex = drive_get_index(IF_SD, 0, 0); |
|
4747 if (sdindex == -1) { |
|
4748 fprintf(stderr, "qemu: missing SecureDigital device\n"); |
|
4749 exit(1); |
|
4750 } |
|
4751 s->mmc = omap_mmc_init(0xfffb7800, drives_table[sdindex].bdrv, |
|
4752 s->irq[1][OMAP_INT_OQN], &s->drq[OMAP_DMA_MMC_TX], |
|
4753 omap_findclk(s, "mmc_ck")); |
|
4754 |
|
4755 s->mpuio = omap_mpuio_init(0xfffb5000, |
|
4756 s->irq[1][OMAP_INT_KEYBOARD], s->irq[1][OMAP_INT_MPUIO], |
|
4757 s->wakeup, omap_findclk(s, "clk32-kHz")); |
|
4758 |
|
4759 s->gpio = omap_gpio_init(0xfffce000, s->irq[0][OMAP_INT_GPIO_BANK1], |
|
4760 omap_findclk(s, "arm_gpio_ck")); |
|
4761 |
|
4762 s->microwire = omap_uwire_init(0xfffb3000, &s->irq[1][OMAP_INT_uWireTX], |
|
4763 s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck")); |
|
4764 |
|
4765 omap_pwl_init(0xfffb5800, s, omap_findclk(s, "armxor_ck")); |
|
4766 omap_pwt_init(0xfffb6000, s, omap_findclk(s, "armxor_ck")); |
|
4767 |
|
4768 s->i2c[0] = omap_i2c_init(0xfffb3800, s->irq[1][OMAP_INT_I2C], |
|
4769 &s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck")); |
|
4770 |
|
4771 s->rtc = omap_rtc_init(0xfffb4800, &s->irq[1][OMAP_INT_RTC_TIMER], |
|
4772 omap_findclk(s, "clk32-kHz")); |
|
4773 |
|
4774 s->mcbsp1 = omap_mcbsp_init(0xfffb1800, &s->irq[1][OMAP_INT_McBSP1TX], |
|
4775 &s->drq[OMAP_DMA_MCBSP1_TX], omap_findclk(s, "dspxor_ck")); |
|
4776 s->mcbsp2 = omap_mcbsp_init(0xfffb1000, &s->irq[0][OMAP_INT_310_McBSP2_TX], |
|
4777 &s->drq[OMAP_DMA_MCBSP2_TX], omap_findclk(s, "mpuper_ck")); |
|
4778 s->mcbsp3 = omap_mcbsp_init(0xfffb7000, &s->irq[1][OMAP_INT_McBSP3TX], |
|
4779 &s->drq[OMAP_DMA_MCBSP3_TX], omap_findclk(s, "dspxor_ck")); |
|
4780 |
|
4781 s->led[0] = omap_lpg_init(0xfffbd000, omap_findclk(s, "clk32-kHz")); |
|
4782 s->led[1] = omap_lpg_init(0xfffbd800, omap_findclk(s, "clk32-kHz")); |
|
4783 |
|
4784 /* Register mappings not currenlty implemented: |
|
4785 * MCSI2 Comm fffb2000 - fffb27ff (not mapped on OMAP310) |
|
4786 * MCSI1 Bluetooth fffb2800 - fffb2fff (not mapped on OMAP310) |
|
4787 * USB W2FC fffb4000 - fffb47ff |
|
4788 * Camera Interface fffb6800 - fffb6fff |
|
4789 * USB Host fffba000 - fffba7ff |
|
4790 * FAC fffba800 - fffbafff |
|
4791 * HDQ/1-Wire fffbc000 - fffbc7ff |
|
4792 * TIPB switches fffbc800 - fffbcfff |
|
4793 * Mailbox fffcf000 - fffcf7ff |
|
4794 * Local bus IF fffec100 - fffec1ff |
|
4795 * Local bus MMU fffec200 - fffec2ff |
|
4796 * DSP MMU fffed200 - fffed2ff |
|
4797 */ |
|
4798 |
|
4799 omap_setup_dsp_mapping(omap15xx_dsp_mm); |
|
4800 omap_setup_mpui_io(s); |
|
4801 |
|
4802 qemu_register_reset(omap1_mpu_reset, s); |
|
4803 |
|
4804 return s; |
|
4805 } |