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1 /* omap_sx1.c Support for the Siemens SX1 smartphone emulation. |
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2 * |
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3 * Copyright (C) 2008 |
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4 * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
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5 * Copyright (C) 2007 Vladimir Ananiev <vovan888@gmail.com> |
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6 * |
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7 * based on PalmOne's (TM) PDAs support (palm.c) |
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8 */ |
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9 |
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10 /* |
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11 * PalmOne's (TM) PDAs. |
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12 * |
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13 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org> |
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14 * |
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15 * This program is free software; you can redistribute it and/or |
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16 * modify it under the terms of the GNU General Public License as |
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17 * published by the Free Software Foundation; either version 2 of |
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18 * the License, or (at your option) any later version. |
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19 * |
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20 * This program is distributed in the hope that it will be useful, |
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21 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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23 * GNU General Public License for more details. |
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24 * |
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25 * You should have received a copy of the GNU General Public License |
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26 * along with this program; if not, write to the Free Software |
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27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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28 * MA 02111-1307 USA |
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29 */ |
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30 #include "hw.h" |
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31 #include "sysemu.h" |
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32 #include "console.h" |
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33 #include "omap.h" |
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34 #include "boards.h" |
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35 #include "arm-misc.h" |
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36 #include "flash.h" |
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37 |
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38 /*****************************************************************************/ |
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39 /* Siemens SX1 Cellphone V1 */ |
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40 /* - ARM OMAP310 processor |
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41 * - SRAM 192 kB |
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42 * - SDRAM 32 MB at 0x10000000 |
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43 * - Boot flash 16 MB at 0x00000000 |
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44 * - Application flash 8 MB at 0x04000000 |
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45 * - 3 serial ports |
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46 * - 1 SecureDigital |
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47 * - 1 LCD display |
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48 * - 1 RTC |
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49 */ |
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50 |
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51 /*****************************************************************************/ |
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52 /* Siemens SX1 Cellphone V2 */ |
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53 /* - ARM OMAP310 processor |
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54 * - SRAM 192 kB |
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55 * - SDRAM 32 MB at 0x10000000 |
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56 * - Boot flash 32 MB at 0x00000000 |
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57 * - 3 serial ports |
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58 * - 1 SecureDigital |
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59 * - 1 LCD display |
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60 * - 1 RTC |
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61 */ |
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62 |
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63 static uint32_t static_readb(void *opaque, target_phys_addr_t offset) |
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64 { |
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65 uint32_t *val = (uint32_t *) opaque; |
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66 |
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67 return *val >> ((offset & 3) << 3); |
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68 } |
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69 |
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70 static uint32_t static_readh(void *opaque, target_phys_addr_t offset) |
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71 { |
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72 uint32_t *val = (uint32_t *) opaque; |
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73 |
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74 return *val >> ((offset & 1) << 3); |
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75 } |
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76 |
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77 static uint32_t static_readw(void *opaque, target_phys_addr_t offset) |
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78 { |
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79 uint32_t *val = (uint32_t *) opaque; |
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80 |
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81 return *val >> ((offset & 0) << 3); |
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82 } |
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83 |
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84 static void static_write(void *opaque, target_phys_addr_t offset, |
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85 uint32_t value) |
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86 { |
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87 #ifdef SPY |
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88 printf("%s: value %08lx written at " PA_FMT "\n", |
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89 __FUNCTION__, value, offset); |
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90 #endif |
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91 } |
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92 |
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93 static CPUReadMemoryFunc *static_readfn[] = { |
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94 static_readb, |
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95 static_readh, |
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96 static_readw, |
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97 }; |
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98 |
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99 static CPUWriteMemoryFunc *static_writefn[] = { |
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100 static_write, |
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101 static_write, |
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102 static_write, |
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103 }; |
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104 |
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105 #define sdram_size 0x02000000 |
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106 #define sector_size (128 * 1024) |
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107 #define flash0_size (16 * 1024 * 1024) |
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108 #define flash1_size ( 8 * 1024 * 1024) |
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109 #define flash2_size (32 * 1024 * 1024) |
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110 #define total_ram_v1 (sdram_size + flash0_size + flash1_size + OMAP15XX_SRAM_SIZE) |
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111 #define total_ram_v2 (sdram_size + flash2_size + OMAP15XX_SRAM_SIZE) |
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112 |
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113 static struct arm_boot_info sx1_binfo = { |
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114 .loader_start = OMAP_EMIFF_BASE, |
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115 .ram_size = sdram_size, |
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116 .board_id = 0x265, |
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117 }; |
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118 |
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119 static void sx1_init(ram_addr_t ram_size, int vga_ram_size, |
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120 const char *boot_device, DisplayState *ds, |
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121 const char *kernel_filename, const char *kernel_cmdline, |
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122 const char *initrd_filename, const char *cpu_model, |
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123 const int version) |
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124 { |
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125 struct omap_mpu_state_s *cpu; |
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126 int io; |
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127 static uint32_t cs0val = 0x00213090; |
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128 static uint32_t cs1val = 0x00215070; |
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129 static uint32_t cs2val = 0x00001139; |
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130 static uint32_t cs3val = 0x00001139; |
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131 ram_addr_t phys_flash; |
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132 int index; |
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133 int fl_idx; |
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134 uint32_t flash_size = flash0_size; |
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135 |
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136 if (version == 2) { |
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137 flash_size = flash2_size; |
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138 } |
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139 |
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140 cpu = omap310_mpu_init(sx1_binfo.ram_size, ds, cpu_model); |
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141 |
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142 /* External Flash (EMIFS) */ |
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143 cpu_register_physical_memory(OMAP_CS0_BASE, flash_size, |
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144 (phys_flash = qemu_ram_alloc(flash_size)) | IO_MEM_ROM); |
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145 |
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146 io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs0val); |
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147 cpu_register_physical_memory(OMAP_CS0_BASE + flash_size, |
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148 OMAP_CS0_SIZE - flash_size, io); |
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149 io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs2val); |
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150 cpu_register_physical_memory(OMAP_CS2_BASE, OMAP_CS2_SIZE, io); |
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151 io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs3val); |
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152 cpu_register_physical_memory(OMAP_CS3_BASE, OMAP_CS3_SIZE, io); |
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153 |
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154 fl_idx = 0; |
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155 |
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156 if ((index = drive_get_index(IF_PFLASH, 0, fl_idx)) > -1) { |
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157 if (!pflash_cfi01_register(OMAP_CS0_BASE, qemu_ram_alloc(flash_size), |
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158 drives_table[index].bdrv, sector_size, flash_size / sector_size, |
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159 4, 0, 0, 0, 0)) { |
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160 fprintf(stderr, "qemu: Error registering flash memory %d.\n", |
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161 fl_idx); |
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162 } |
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163 fl_idx++; |
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164 } |
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165 |
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166 if ((version == 1) && |
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167 (index = drive_get_index(IF_PFLASH, 0, fl_idx)) > -1) { |
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168 cpu_register_physical_memory(OMAP_CS1_BASE, flash1_size, |
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169 (phys_flash = qemu_ram_alloc(flash1_size)) | |
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170 IO_MEM_ROM); |
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171 io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs1val); |
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172 cpu_register_physical_memory(OMAP_CS1_BASE + flash1_size, |
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173 OMAP_CS1_SIZE - flash1_size, io); |
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174 |
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175 if (!pflash_cfi01_register(OMAP_CS1_BASE, qemu_ram_alloc(flash1_size), |
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176 drives_table[index].bdrv, sector_size, flash1_size / sector_size, |
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177 4, 0, 0, 0, 0)) { |
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178 fprintf(stderr, "qemu: Error registering flash memory %d.\n", |
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179 fl_idx); |
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180 } |
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181 fl_idx++; |
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182 } else { |
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183 io = cpu_register_io_memory(0, static_readfn, static_writefn, &cs1val); |
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184 cpu_register_physical_memory(OMAP_CS1_BASE, OMAP_CS1_SIZE, io); |
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185 } |
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186 |
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187 if (!kernel_filename && !fl_idx) { |
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188 fprintf(stderr, "Kernel or Flash image must be specified\n"); |
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189 exit(1); |
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190 } |
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191 |
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192 /* Load the kernel. */ |
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193 if (kernel_filename) { |
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194 /* Start at bootloader. */ |
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195 cpu->env->regs[15] = sx1_binfo.loader_start; |
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196 |
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197 sx1_binfo.kernel_filename = kernel_filename; |
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198 sx1_binfo.kernel_cmdline = kernel_cmdline; |
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199 sx1_binfo.initrd_filename = initrd_filename; |
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200 arm_load_kernel(cpu->env, &sx1_binfo); |
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201 } else { |
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202 cpu->env->regs[15] = 0x00000000; |
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203 } |
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204 |
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205 #if 0 |
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206 DFG: TODO CHECK if this is still needed. |
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207 dpy_resize(ds, 640, 480); |
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208 #endif |
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209 } |
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210 |
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211 static void sx1_init_v1(ram_addr_t ram_size, int vga_ram_size, |
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212 const char *boot_device, DisplayState *ds, |
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213 const char *kernel_filename, const char *kernel_cmdline, |
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214 const char *initrd_filename, const char *cpu_model) |
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215 { |
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216 sx1_init(ram_size, vga_ram_size, boot_device, ds, kernel_filename, |
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217 kernel_cmdline, initrd_filename, cpu_model, 1); |
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218 } |
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219 |
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220 static void sx1_init_v2(ram_addr_t ram_size, int vga_ram_size, |
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221 const char *boot_device, DisplayState *ds, |
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222 const char *kernel_filename, const char *kernel_cmdline, |
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223 const char *initrd_filename, const char *cpu_model) |
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224 { |
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225 sx1_init(ram_size, vga_ram_size, boot_device, ds, kernel_filename, |
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226 kernel_cmdline, initrd_filename, cpu_model, 2); |
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227 } |
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228 |
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229 QEMUMachine sx1_machine_v2 = { |
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230 .name = "sx1", |
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231 .desc = "Siemens SX1 (OMAP310) V2", |
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232 .init = sx1_init_v2, |
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233 .ram_require = total_ram_v2 | RAMSIZE_FIXED, |
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234 }; |
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235 |
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236 QEMUMachine sx1_machine_v1 = { |
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237 .name = "sx1-v1", |
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238 .desc = "Siemens SX1 (OMAP310) V1", |
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239 .init = sx1_init_v1, |
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240 .ram_require = total_ram_v1 | RAMSIZE_FIXED, |
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241 }; |