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1 /* |
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2 * OpenPIC emulation |
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3 * |
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4 * Copyright (c) 2004 Jocelyn Mayer |
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5 * |
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6 * Permission is hereby granted, free of charge, to any person obtaining a copy |
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7 * of this software and associated documentation files (the "Software"), to deal |
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8 * in the Software without restriction, including without limitation the rights |
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9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
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10 * copies of the Software, and to permit persons to whom the Software is |
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11 * furnished to do so, subject to the following conditions: |
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12 * |
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13 * The above copyright notice and this permission notice shall be included in |
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14 * all copies or substantial portions of the Software. |
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15 * |
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
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22 * THE SOFTWARE. |
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23 */ |
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24 /* |
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25 * |
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26 * Based on OpenPic implementations: |
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27 * - Intel GW80314 I/O compagnion chip developper's manual |
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28 * - Motorola MPC8245 & MPC8540 user manuals. |
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29 * - Motorola MCP750 (aka Raven) programmer manual. |
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30 * - Motorola Harrier programmer manuel |
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31 * |
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32 * Serial interrupts, as implemented in Raven chipset are not supported yet. |
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33 * |
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34 */ |
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35 #include "hw.h" |
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36 #include "ppc_mac.h" |
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37 #include "pci.h" |
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38 |
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39 //#define DEBUG_OPENPIC |
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40 |
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41 #ifdef DEBUG_OPENPIC |
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42 #define DPRINTF(fmt, args...) do { printf(fmt , ##args); } while (0) |
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43 #else |
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44 #define DPRINTF(fmt, args...) do { } while (0) |
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45 #endif |
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46 #define ERROR(fmr, args...) do { printf("ERROR: " fmr , ##args); } while (0) |
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47 |
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48 #define USE_MPCxxx /* Intel model is broken, for now */ |
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49 |
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50 #if defined (USE_INTEL_GW80314) |
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51 /* Intel GW80314 I/O Companion chip */ |
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52 |
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53 #define MAX_CPU 4 |
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54 #define MAX_IRQ 32 |
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55 #define MAX_DBL 4 |
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56 #define MAX_MBX 4 |
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57 #define MAX_TMR 4 |
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58 #define VECTOR_BITS 8 |
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59 #define MAX_IPI 0 |
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60 |
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61 #define VID (0x00000000) |
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62 |
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63 #define OPENPIC_LITTLE_ENDIAN 1 |
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64 #define OPENPIC_BIG_ENDIAN 0 |
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65 |
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66 #elif defined(USE_MPCxxx) |
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67 |
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68 #define MAX_CPU 2 |
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69 #define MAX_IRQ 64 |
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70 #define EXT_IRQ 48 |
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71 #define MAX_DBL 0 |
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72 #define MAX_MBX 0 |
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73 #define MAX_TMR 4 |
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74 #define VECTOR_BITS 8 |
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75 #define MAX_IPI 4 |
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76 #define VID 0x03 /* MPIC version ID */ |
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77 #define VENI 0x00000000 /* Vendor ID */ |
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78 |
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79 enum { |
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80 IRQ_IPVP = 0, |
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81 IRQ_IDE, |
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82 }; |
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83 |
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84 #define OPENPIC_LITTLE_ENDIAN 1 |
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85 #define OPENPIC_BIG_ENDIAN 0 |
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86 |
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87 #else |
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88 #error "Please select which OpenPic implementation is to be emulated" |
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89 #endif |
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90 |
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91 #if (OPENPIC_BIG_ENDIAN && !TARGET_WORDS_BIGENDIAN) || \ |
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92 (OPENPIC_LITTLE_ENDIAN && TARGET_WORDS_BIGENDIAN) |
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93 #define OPENPIC_SWAP |
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94 #endif |
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95 |
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96 /* Interrupt definitions */ |
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97 #define IRQ_FE (EXT_IRQ) /* Internal functional IRQ */ |
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98 #define IRQ_ERR (EXT_IRQ + 1) /* Error IRQ */ |
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99 #define IRQ_TIM0 (EXT_IRQ + 2) /* First timer IRQ */ |
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100 #if MAX_IPI > 0 |
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101 #define IRQ_IPI0 (IRQ_TIM0 + MAX_TMR) /* First IPI IRQ */ |
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102 #define IRQ_DBL0 (IRQ_IPI0 + (MAX_CPU * MAX_IPI)) /* First doorbell IRQ */ |
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103 #else |
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104 #define IRQ_DBL0 (IRQ_TIM0 + MAX_TMR) /* First doorbell IRQ */ |
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105 #define IRQ_MBX0 (IRQ_DBL0 + MAX_DBL) /* First mailbox IRQ */ |
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106 #endif |
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107 |
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108 #define BF_WIDTH(_bits_) \ |
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109 (((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8)) |
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110 |
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111 static inline void set_bit (uint32_t *field, int bit) |
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112 { |
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113 field[bit >> 5] |= 1 << (bit & 0x1F); |
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114 } |
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115 |
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116 static inline void reset_bit (uint32_t *field, int bit) |
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117 { |
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118 field[bit >> 5] &= ~(1 << (bit & 0x1F)); |
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119 } |
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120 |
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121 static inline int test_bit (uint32_t *field, int bit) |
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122 { |
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123 return (field[bit >> 5] & 1 << (bit & 0x1F)) != 0; |
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124 } |
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125 |
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126 enum { |
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127 IRQ_EXTERNAL = 0x01, |
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128 IRQ_INTERNAL = 0x02, |
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129 IRQ_TIMER = 0x04, |
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130 IRQ_SPECIAL = 0x08, |
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131 }; |
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132 |
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133 typedef struct IRQ_queue_t { |
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134 uint32_t queue[BF_WIDTH(MAX_IRQ)]; |
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135 int next; |
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136 int priority; |
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137 } IRQ_queue_t; |
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138 |
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139 typedef struct IRQ_src_t { |
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140 uint32_t ipvp; /* IRQ vector/priority register */ |
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141 uint32_t ide; /* IRQ destination register */ |
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142 int type; |
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143 int last_cpu; |
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144 int pending; /* TRUE if IRQ is pending */ |
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145 } IRQ_src_t; |
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146 |
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147 enum IPVP_bits { |
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148 IPVP_MASK = 31, |
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149 IPVP_ACTIVITY = 30, |
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150 IPVP_MODE = 29, |
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151 IPVP_POLARITY = 23, |
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152 IPVP_SENSE = 22, |
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153 }; |
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154 #define IPVP_PRIORITY_MASK (0x1F << 16) |
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155 #define IPVP_PRIORITY(_ipvpr_) ((int)(((_ipvpr_) & IPVP_PRIORITY_MASK) >> 16)) |
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156 #define IPVP_VECTOR_MASK ((1 << VECTOR_BITS) - 1) |
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157 #define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) & IPVP_VECTOR_MASK) |
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158 |
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159 typedef struct IRQ_dst_t { |
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160 uint32_t pctp; /* CPU current task priority */ |
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161 uint32_t pcsr; /* CPU sensitivity register */ |
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162 IRQ_queue_t raised; |
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163 IRQ_queue_t servicing; |
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164 qemu_irq *irqs; |
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165 } IRQ_dst_t; |
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166 |
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167 typedef struct openpic_t { |
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168 PCIDevice pci_dev; |
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169 int mem_index; |
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170 /* Global registers */ |
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171 uint32_t frep; /* Feature reporting register */ |
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172 uint32_t glbc; /* Global configuration register */ |
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173 uint32_t micr; /* MPIC interrupt configuration register */ |
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174 uint32_t veni; /* Vendor identification register */ |
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175 uint32_t pint; /* Processor initialization register */ |
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176 uint32_t spve; /* Spurious vector register */ |
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177 uint32_t tifr; /* Timer frequency reporting register */ |
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178 /* Source registers */ |
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179 IRQ_src_t src[MAX_IRQ]; |
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180 /* Local registers per output pin */ |
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181 IRQ_dst_t dst[MAX_CPU]; |
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182 int nb_cpus; |
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183 /* Timer registers */ |
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184 struct { |
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185 uint32_t ticc; /* Global timer current count register */ |
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186 uint32_t tibc; /* Global timer base count register */ |
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187 } timers[MAX_TMR]; |
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188 #if MAX_DBL > 0 |
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189 /* Doorbell registers */ |
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190 uint32_t dar; /* Doorbell activate register */ |
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191 struct { |
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192 uint32_t dmr; /* Doorbell messaging register */ |
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193 } doorbells[MAX_DBL]; |
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194 #endif |
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195 #if MAX_MBX > 0 |
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196 /* Mailbox registers */ |
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197 struct { |
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198 uint32_t mbr; /* Mailbox register */ |
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199 } mailboxes[MAX_MAILBOXES]; |
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200 #endif |
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201 /* IRQ out is used when in bypass mode (not implemented) */ |
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202 qemu_irq irq_out; |
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203 } openpic_t; |
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204 |
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205 static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ) |
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206 { |
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207 set_bit(q->queue, n_IRQ); |
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208 } |
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209 |
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210 static inline void IRQ_resetbit (IRQ_queue_t *q, int n_IRQ) |
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211 { |
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212 reset_bit(q->queue, n_IRQ); |
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213 } |
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214 |
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215 static inline int IRQ_testbit (IRQ_queue_t *q, int n_IRQ) |
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216 { |
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217 return test_bit(q->queue, n_IRQ); |
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218 } |
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219 |
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220 static void IRQ_check (openpic_t *opp, IRQ_queue_t *q) |
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221 { |
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222 int next, i; |
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223 int priority; |
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224 |
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225 next = -1; |
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226 priority = -1; |
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227 for (i = 0; i < MAX_IRQ; i++) { |
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228 if (IRQ_testbit(q, i)) { |
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229 DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n", |
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230 i, IPVP_PRIORITY(opp->src[i].ipvp), priority); |
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231 if (IPVP_PRIORITY(opp->src[i].ipvp) > priority) { |
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232 next = i; |
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233 priority = IPVP_PRIORITY(opp->src[i].ipvp); |
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234 } |
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235 } |
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236 } |
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237 q->next = next; |
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238 q->priority = priority; |
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239 } |
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240 |
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241 static int IRQ_get_next (openpic_t *opp, IRQ_queue_t *q) |
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242 { |
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243 if (q->next == -1) { |
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244 /* XXX: optimize */ |
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245 IRQ_check(opp, q); |
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246 } |
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247 |
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248 return q->next; |
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249 } |
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250 |
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251 static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int n_IRQ) |
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252 { |
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253 IRQ_dst_t *dst; |
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254 IRQ_src_t *src; |
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255 int priority; |
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256 |
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257 dst = &opp->dst[n_CPU]; |
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258 src = &opp->src[n_IRQ]; |
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259 priority = IPVP_PRIORITY(src->ipvp); |
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260 if (priority <= dst->pctp) { |
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261 /* Too low priority */ |
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262 DPRINTF("%s: IRQ %d has too low priority on CPU %d\n", |
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263 __func__, n_IRQ, n_CPU); |
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264 return; |
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265 } |
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266 if (IRQ_testbit(&dst->raised, n_IRQ)) { |
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267 /* Interrupt miss */ |
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268 DPRINTF("%s: IRQ %d was missed on CPU %d\n", |
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269 __func__, n_IRQ, n_CPU); |
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270 return; |
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271 } |
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272 set_bit(&src->ipvp, IPVP_ACTIVITY); |
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273 IRQ_setbit(&dst->raised, n_IRQ); |
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274 if (priority < dst->raised.priority) { |
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275 /* An higher priority IRQ is already raised */ |
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276 DPRINTF("%s: IRQ %d is hidden by raised IRQ %d on CPU %d\n", |
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277 __func__, n_IRQ, dst->raised.next, n_CPU); |
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278 return; |
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279 } |
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280 IRQ_get_next(opp, &dst->raised); |
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281 if (IRQ_get_next(opp, &dst->servicing) != -1 && |
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282 priority < dst->servicing.priority) { |
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283 DPRINTF("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n", |
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284 __func__, n_IRQ, dst->servicing.next, n_CPU); |
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285 /* Already servicing a higher priority IRQ */ |
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286 return; |
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287 } |
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288 DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", n_CPU, n_IRQ); |
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289 qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_INT]); |
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290 } |
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291 |
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292 /* update pic state because registers for n_IRQ have changed value */ |
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293 static void openpic_update_irq(openpic_t *opp, int n_IRQ) |
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294 { |
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295 IRQ_src_t *src; |
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296 int i; |
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297 |
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298 src = &opp->src[n_IRQ]; |
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299 |
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300 if (!src->pending) { |
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301 /* no irq pending */ |
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302 DPRINTF("%s: IRQ %d is not pending\n", __func__, n_IRQ); |
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303 return; |
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304 } |
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305 if (test_bit(&src->ipvp, IPVP_MASK)) { |
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306 /* Interrupt source is disabled */ |
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307 DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ); |
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308 return; |
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309 } |
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310 if (IPVP_PRIORITY(src->ipvp) == 0) { |
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311 /* Priority set to zero */ |
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312 DPRINTF("%s: IRQ %d has 0 priority\n", __func__, n_IRQ); |
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313 return; |
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314 } |
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315 if (test_bit(&src->ipvp, IPVP_ACTIVITY)) { |
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316 /* IRQ already active */ |
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317 DPRINTF("%s: IRQ %d is already active\n", __func__, n_IRQ); |
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318 return; |
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319 } |
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320 if (src->ide == 0x00000000) { |
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321 /* No target */ |
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322 DPRINTF("%s: IRQ %d has no target\n", __func__, n_IRQ); |
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323 return; |
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324 } |
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325 |
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326 if (src->ide == (1 << src->last_cpu)) { |
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327 /* Only one CPU is allowed to receive this IRQ */ |
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328 IRQ_local_pipe(opp, src->last_cpu, n_IRQ); |
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329 } else if (!test_bit(&src->ipvp, IPVP_MODE)) { |
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330 /* Directed delivery mode */ |
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331 for (i = 0; i < opp->nb_cpus; i++) { |
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332 if (test_bit(&src->ide, i)) |
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333 IRQ_local_pipe(opp, i, n_IRQ); |
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334 } |
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335 } else { |
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336 /* Distributed delivery mode */ |
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337 for (i = src->last_cpu + 1; i != src->last_cpu; i++) { |
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338 if (i == opp->nb_cpus) |
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339 i = 0; |
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340 if (test_bit(&src->ide, i)) { |
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341 IRQ_local_pipe(opp, i, n_IRQ); |
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342 src->last_cpu = i; |
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343 break; |
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344 } |
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345 } |
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346 } |
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347 } |
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348 |
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349 static void openpic_set_irq(void *opaque, int n_IRQ, int level) |
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350 { |
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351 openpic_t *opp = opaque; |
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352 IRQ_src_t *src; |
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353 |
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354 src = &opp->src[n_IRQ]; |
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355 DPRINTF("openpic: set irq %d = %d ipvp=%08x\n", |
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356 n_IRQ, level, src->ipvp); |
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357 if (test_bit(&src->ipvp, IPVP_SENSE)) { |
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358 /* level-sensitive irq */ |
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359 src->pending = level; |
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360 if (!level) |
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361 reset_bit(&src->ipvp, IPVP_ACTIVITY); |
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362 } else { |
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363 /* edge-sensitive irq */ |
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364 if (level) |
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365 src->pending = 1; |
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366 } |
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367 openpic_update_irq(opp, n_IRQ); |
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368 } |
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369 |
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370 static void openpic_reset (openpic_t *opp) |
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371 { |
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372 int i; |
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373 |
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374 opp->glbc = 0x80000000; |
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375 /* Initialise controller registers */ |
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376 opp->frep = ((EXT_IRQ - 1) << 16) | ((MAX_CPU - 1) << 8) | VID; |
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377 opp->veni = VENI; |
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378 opp->pint = 0x00000000; |
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379 opp->spve = 0x000000FF; |
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380 opp->tifr = 0x003F7A00; |
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381 /* ? */ |
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382 opp->micr = 0x00000000; |
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383 /* Initialise IRQ sources */ |
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384 for (i = 0; i < MAX_IRQ; i++) { |
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385 opp->src[i].ipvp = 0xA0000000; |
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386 opp->src[i].ide = 0x00000000; |
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387 } |
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388 /* Initialise IRQ destinations */ |
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389 for (i = 0; i < MAX_CPU; i++) { |
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390 opp->dst[i].pctp = 0x0000000F; |
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391 opp->dst[i].pcsr = 0x00000000; |
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392 memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t)); |
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393 memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t)); |
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394 } |
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395 /* Initialise timers */ |
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396 for (i = 0; i < MAX_TMR; i++) { |
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397 opp->timers[i].ticc = 0x00000000; |
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398 opp->timers[i].tibc = 0x80000000; |
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399 } |
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400 /* Initialise doorbells */ |
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401 #if MAX_DBL > 0 |
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402 opp->dar = 0x00000000; |
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403 for (i = 0; i < MAX_DBL; i++) { |
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404 opp->doorbells[i].dmr = 0x00000000; |
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405 } |
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406 #endif |
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407 /* Initialise mailboxes */ |
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408 #if MAX_MBX > 0 |
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409 for (i = 0; i < MAX_MBX; i++) { /* ? */ |
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410 opp->mailboxes[i].mbr = 0x00000000; |
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411 } |
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412 #endif |
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413 /* Go out of RESET state */ |
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414 opp->glbc = 0x00000000; |
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415 } |
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416 |
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417 static inline uint32_t read_IRQreg (openpic_t *opp, int n_IRQ, uint32_t reg) |
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418 { |
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419 uint32_t retval; |
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420 |
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421 switch (reg) { |
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422 case IRQ_IPVP: |
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423 retval = opp->src[n_IRQ].ipvp; |
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424 break; |
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425 case IRQ_IDE: |
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426 retval = opp->src[n_IRQ].ide; |
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427 break; |
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428 } |
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429 |
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430 return retval; |
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431 } |
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432 |
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433 static inline void write_IRQreg (openpic_t *opp, int n_IRQ, |
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434 uint32_t reg, uint32_t val) |
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435 { |
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436 uint32_t tmp; |
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437 |
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438 switch (reg) { |
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439 case IRQ_IPVP: |
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440 /* NOTE: not fully accurate for special IRQs, but simple and |
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441 sufficient */ |
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442 /* ACTIVITY bit is read-only */ |
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443 opp->src[n_IRQ].ipvp = |
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444 (opp->src[n_IRQ].ipvp & 0x40000000) | |
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445 (val & 0x800F00FF); |
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446 openpic_update_irq(opp, n_IRQ); |
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447 DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n", |
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448 n_IRQ, val, opp->src[n_IRQ].ipvp); |
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449 break; |
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450 case IRQ_IDE: |
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451 tmp = val & 0xC0000000; |
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452 tmp |= val & ((1 << MAX_CPU) - 1); |
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453 opp->src[n_IRQ].ide = tmp; |
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454 DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide); |
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455 break; |
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456 } |
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457 } |
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458 |
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459 #if 0 // Code provision for Intel model |
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460 #if MAX_DBL > 0 |
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461 static uint32_t read_doorbell_register (openpic_t *opp, |
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462 int n_dbl, uint32_t offset) |
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463 { |
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464 uint32_t retval; |
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465 |
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466 switch (offset) { |
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467 case DBL_IPVP_OFFSET: |
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468 retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP); |
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469 break; |
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470 case DBL_IDE_OFFSET: |
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471 retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE); |
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472 break; |
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473 case DBL_DMR_OFFSET: |
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474 retval = opp->doorbells[n_dbl].dmr; |
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475 break; |
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476 } |
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477 |
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478 return retval; |
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479 } |
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480 |
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481 static void write_doorbell_register (penpic_t *opp, int n_dbl, |
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482 uint32_t offset, uint32_t value) |
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483 { |
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484 switch (offset) { |
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485 case DBL_IVPR_OFFSET: |
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486 write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP, value); |
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487 break; |
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488 case DBL_IDE_OFFSET: |
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489 write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE, value); |
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490 break; |
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491 case DBL_DMR_OFFSET: |
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492 opp->doorbells[n_dbl].dmr = value; |
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493 break; |
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494 } |
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495 } |
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496 #endif |
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497 |
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498 #if MAX_MBX > 0 |
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499 static uint32_t read_mailbox_register (openpic_t *opp, |
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500 int n_mbx, uint32_t offset) |
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501 { |
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502 uint32_t retval; |
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503 |
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504 switch (offset) { |
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505 case MBX_MBR_OFFSET: |
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506 retval = opp->mailboxes[n_mbx].mbr; |
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507 break; |
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508 case MBX_IVPR_OFFSET: |
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509 retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP); |
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510 break; |
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511 case MBX_DMR_OFFSET: |
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512 retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE); |
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513 break; |
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514 } |
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515 |
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516 return retval; |
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517 } |
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518 |
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519 static void write_mailbox_register (openpic_t *opp, int n_mbx, |
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520 uint32_t address, uint32_t value) |
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521 { |
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522 switch (offset) { |
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523 case MBX_MBR_OFFSET: |
|
524 opp->mailboxes[n_mbx].mbr = value; |
|
525 break; |
|
526 case MBX_IVPR_OFFSET: |
|
527 write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP, value); |
|
528 break; |
|
529 case MBX_DMR_OFFSET: |
|
530 write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE, value); |
|
531 break; |
|
532 } |
|
533 } |
|
534 #endif |
|
535 #endif /* 0 : Code provision for Intel model */ |
|
536 |
|
537 static void openpic_gbl_write (void *opaque, uint32_t addr, uint32_t val) |
|
538 { |
|
539 openpic_t *opp = opaque; |
|
540 IRQ_dst_t *dst; |
|
541 int idx; |
|
542 |
|
543 DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val); |
|
544 if (addr & 0xF) |
|
545 return; |
|
546 #if defined OPENPIC_SWAP |
|
547 val = bswap32(val); |
|
548 #endif |
|
549 addr &= 0xFF; |
|
550 switch (addr) { |
|
551 case 0x00: /* FREP */ |
|
552 break; |
|
553 case 0x20: /* GLBC */ |
|
554 if (val & 0x80000000) |
|
555 openpic_reset(opp); |
|
556 opp->glbc = val & ~0x80000000; |
|
557 break; |
|
558 case 0x80: /* VENI */ |
|
559 break; |
|
560 case 0x90: /* PINT */ |
|
561 for (idx = 0; idx < opp->nb_cpus; idx++) { |
|
562 if ((val & (1 << idx)) && !(opp->pint & (1 << idx))) { |
|
563 DPRINTF("Raise OpenPIC RESET output for CPU %d\n", idx); |
|
564 dst = &opp->dst[idx]; |
|
565 qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_RESET]); |
|
566 } else if (!(val & (1 << idx)) && (opp->pint & (1 << idx))) { |
|
567 DPRINTF("Lower OpenPIC RESET output for CPU %d\n", idx); |
|
568 dst = &opp->dst[idx]; |
|
569 qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_RESET]); |
|
570 } |
|
571 } |
|
572 opp->pint = val; |
|
573 break; |
|
574 #if MAX_IPI > 0 |
|
575 case 0xA0: /* IPI_IPVP */ |
|
576 case 0xB0: |
|
577 case 0xC0: |
|
578 case 0xD0: |
|
579 { |
|
580 int idx; |
|
581 idx = (addr - 0xA0) >> 4; |
|
582 write_IRQreg(opp, IRQ_IPI0 + idx, IRQ_IPVP, val); |
|
583 } |
|
584 break; |
|
585 #endif |
|
586 case 0xE0: /* SPVE */ |
|
587 opp->spve = val & 0x000000FF; |
|
588 break; |
|
589 case 0xF0: /* TIFR */ |
|
590 opp->tifr = val; |
|
591 break; |
|
592 default: |
|
593 break; |
|
594 } |
|
595 } |
|
596 |
|
597 static uint32_t openpic_gbl_read (void *opaque, uint32_t addr) |
|
598 { |
|
599 openpic_t *opp = opaque; |
|
600 uint32_t retval; |
|
601 |
|
602 DPRINTF("%s: addr %08x\n", __func__, addr); |
|
603 retval = 0xFFFFFFFF; |
|
604 if (addr & 0xF) |
|
605 return retval; |
|
606 addr &= 0xFF; |
|
607 switch (addr) { |
|
608 case 0x00: /* FREP */ |
|
609 retval = opp->frep; |
|
610 break; |
|
611 case 0x20: /* GLBC */ |
|
612 retval = opp->glbc; |
|
613 break; |
|
614 case 0x80: /* VENI */ |
|
615 retval = opp->veni; |
|
616 break; |
|
617 case 0x90: /* PINT */ |
|
618 retval = 0x00000000; |
|
619 break; |
|
620 #if MAX_IPI > 0 |
|
621 case 0xA0: /* IPI_IPVP */ |
|
622 case 0xB0: |
|
623 case 0xC0: |
|
624 case 0xD0: |
|
625 { |
|
626 int idx; |
|
627 idx = (addr - 0xA0) >> 4; |
|
628 retval = read_IRQreg(opp, IRQ_IPI0 + idx, IRQ_IPVP); |
|
629 } |
|
630 break; |
|
631 #endif |
|
632 case 0xE0: /* SPVE */ |
|
633 retval = opp->spve; |
|
634 break; |
|
635 case 0xF0: /* TIFR */ |
|
636 retval = opp->tifr; |
|
637 break; |
|
638 default: |
|
639 break; |
|
640 } |
|
641 DPRINTF("%s: => %08x\n", __func__, retval); |
|
642 #if defined OPENPIC_SWAP |
|
643 retval = bswap32(retval); |
|
644 #endif |
|
645 |
|
646 return retval; |
|
647 } |
|
648 |
|
649 static void openpic_timer_write (void *opaque, uint32_t addr, uint32_t val) |
|
650 { |
|
651 openpic_t *opp = opaque; |
|
652 int idx; |
|
653 |
|
654 DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val); |
|
655 if (addr & 0xF) |
|
656 return; |
|
657 #if defined OPENPIC_SWAP |
|
658 val = bswap32(val); |
|
659 #endif |
|
660 addr -= 0x1100; |
|
661 addr &= 0xFFFF; |
|
662 idx = (addr & 0xFFF0) >> 6; |
|
663 addr = addr & 0x30; |
|
664 switch (addr) { |
|
665 case 0x00: /* TICC */ |
|
666 break; |
|
667 case 0x10: /* TIBC */ |
|
668 if ((opp->timers[idx].ticc & 0x80000000) != 0 && |
|
669 (val & 0x80000000) == 0 && |
|
670 (opp->timers[idx].tibc & 0x80000000) != 0) |
|
671 opp->timers[idx].ticc &= ~0x80000000; |
|
672 opp->timers[idx].tibc = val; |
|
673 break; |
|
674 case 0x20: /* TIVP */ |
|
675 write_IRQreg(opp, IRQ_TIM0 + idx, IRQ_IPVP, val); |
|
676 break; |
|
677 case 0x30: /* TIDE */ |
|
678 write_IRQreg(opp, IRQ_TIM0 + idx, IRQ_IDE, val); |
|
679 break; |
|
680 } |
|
681 } |
|
682 |
|
683 static uint32_t openpic_timer_read (void *opaque, uint32_t addr) |
|
684 { |
|
685 openpic_t *opp = opaque; |
|
686 uint32_t retval; |
|
687 int idx; |
|
688 |
|
689 DPRINTF("%s: addr %08x\n", __func__, addr); |
|
690 retval = 0xFFFFFFFF; |
|
691 if (addr & 0xF) |
|
692 return retval; |
|
693 addr -= 0x1100; |
|
694 addr &= 0xFFFF; |
|
695 idx = (addr & 0xFFF0) >> 6; |
|
696 addr = addr & 0x30; |
|
697 switch (addr) { |
|
698 case 0x00: /* TICC */ |
|
699 retval = opp->timers[idx].ticc; |
|
700 break; |
|
701 case 0x10: /* TIBC */ |
|
702 retval = opp->timers[idx].tibc; |
|
703 break; |
|
704 case 0x20: /* TIPV */ |
|
705 retval = read_IRQreg(opp, IRQ_TIM0 + idx, IRQ_IPVP); |
|
706 break; |
|
707 case 0x30: /* TIDE */ |
|
708 retval = read_IRQreg(opp, IRQ_TIM0 + idx, IRQ_IDE); |
|
709 break; |
|
710 } |
|
711 DPRINTF("%s: => %08x\n", __func__, retval); |
|
712 #if defined OPENPIC_SWAP |
|
713 retval = bswap32(retval); |
|
714 #endif |
|
715 |
|
716 return retval; |
|
717 } |
|
718 |
|
719 static void openpic_src_write (void *opaque, uint32_t addr, uint32_t val) |
|
720 { |
|
721 openpic_t *opp = opaque; |
|
722 int idx; |
|
723 |
|
724 DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val); |
|
725 if (addr & 0xF) |
|
726 return; |
|
727 #if defined OPENPIC_SWAP |
|
728 val = tswap32(val); |
|
729 #endif |
|
730 addr = addr & 0xFFF0; |
|
731 idx = addr >> 5; |
|
732 if (addr & 0x10) { |
|
733 /* EXDE / IFEDE / IEEDE */ |
|
734 write_IRQreg(opp, idx, IRQ_IDE, val); |
|
735 } else { |
|
736 /* EXVP / IFEVP / IEEVP */ |
|
737 write_IRQreg(opp, idx, IRQ_IPVP, val); |
|
738 } |
|
739 } |
|
740 |
|
741 static uint32_t openpic_src_read (void *opaque, uint32_t addr) |
|
742 { |
|
743 openpic_t *opp = opaque; |
|
744 uint32_t retval; |
|
745 int idx; |
|
746 |
|
747 DPRINTF("%s: addr %08x\n", __func__, addr); |
|
748 retval = 0xFFFFFFFF; |
|
749 if (addr & 0xF) |
|
750 return retval; |
|
751 addr = addr & 0xFFF0; |
|
752 idx = addr >> 5; |
|
753 if (addr & 0x10) { |
|
754 /* EXDE / IFEDE / IEEDE */ |
|
755 retval = read_IRQreg(opp, idx, IRQ_IDE); |
|
756 } else { |
|
757 /* EXVP / IFEVP / IEEVP */ |
|
758 retval = read_IRQreg(opp, idx, IRQ_IPVP); |
|
759 } |
|
760 DPRINTF("%s: => %08x\n", __func__, retval); |
|
761 #if defined OPENPIC_SWAP |
|
762 retval = tswap32(retval); |
|
763 #endif |
|
764 |
|
765 return retval; |
|
766 } |
|
767 |
|
768 static void openpic_cpu_write (void *opaque, uint32_t addr, uint32_t val) |
|
769 { |
|
770 openpic_t *opp = opaque; |
|
771 IRQ_src_t *src; |
|
772 IRQ_dst_t *dst; |
|
773 int idx, s_IRQ, n_IRQ; |
|
774 |
|
775 DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val); |
|
776 if (addr & 0xF) |
|
777 return; |
|
778 #if defined OPENPIC_SWAP |
|
779 val = bswap32(val); |
|
780 #endif |
|
781 addr &= 0x1FFF0; |
|
782 idx = addr / 0x1000; |
|
783 dst = &opp->dst[idx]; |
|
784 addr &= 0xFF0; |
|
785 switch (addr) { |
|
786 #if MAX_IPI > 0 |
|
787 case 0x40: /* PIPD */ |
|
788 case 0x50: |
|
789 case 0x60: |
|
790 case 0x70: |
|
791 idx = (addr - 0x40) >> 4; |
|
792 write_IRQreg(opp, IRQ_IPI0 + idx, IRQ_IDE, val); |
|
793 openpic_set_irq(opp, IRQ_IPI0 + idx, 1); |
|
794 openpic_set_irq(opp, IRQ_IPI0 + idx, 0); |
|
795 break; |
|
796 #endif |
|
797 case 0x80: /* PCTP */ |
|
798 dst->pctp = val & 0x0000000F; |
|
799 break; |
|
800 case 0x90: /* WHOAMI */ |
|
801 /* Read-only register */ |
|
802 break; |
|
803 case 0xA0: /* PIAC */ |
|
804 /* Read-only register */ |
|
805 break; |
|
806 case 0xB0: /* PEOI */ |
|
807 DPRINTF("PEOI\n"); |
|
808 s_IRQ = IRQ_get_next(opp, &dst->servicing); |
|
809 IRQ_resetbit(&dst->servicing, s_IRQ); |
|
810 dst->servicing.next = -1; |
|
811 /* Set up next servicing IRQ */ |
|
812 s_IRQ = IRQ_get_next(opp, &dst->servicing); |
|
813 /* Check queued interrupts. */ |
|
814 n_IRQ = IRQ_get_next(opp, &dst->raised); |
|
815 src = &opp->src[n_IRQ]; |
|
816 if (n_IRQ != -1 && |
|
817 (s_IRQ == -1 || |
|
818 IPVP_PRIORITY(src->ipvp) > dst->servicing.priority)) { |
|
819 DPRINTF("Raise OpenPIC INT output cpu %d irq %d\n", |
|
820 idx, n_IRQ); |
|
821 qemu_irq_raise(dst->irqs[OPENPIC_OUTPUT_INT]); |
|
822 } |
|
823 break; |
|
824 default: |
|
825 break; |
|
826 } |
|
827 } |
|
828 |
|
829 static uint32_t openpic_cpu_read (void *opaque, uint32_t addr) |
|
830 { |
|
831 openpic_t *opp = opaque; |
|
832 IRQ_src_t *src; |
|
833 IRQ_dst_t *dst; |
|
834 uint32_t retval; |
|
835 int idx, n_IRQ; |
|
836 |
|
837 DPRINTF("%s: addr %08x\n", __func__, addr); |
|
838 retval = 0xFFFFFFFF; |
|
839 if (addr & 0xF) |
|
840 return retval; |
|
841 addr &= 0x1FFF0; |
|
842 idx = addr / 0x1000; |
|
843 dst = &opp->dst[idx]; |
|
844 addr &= 0xFF0; |
|
845 switch (addr) { |
|
846 case 0x80: /* PCTP */ |
|
847 retval = dst->pctp; |
|
848 break; |
|
849 case 0x90: /* WHOAMI */ |
|
850 retval = idx; |
|
851 break; |
|
852 case 0xA0: /* PIAC */ |
|
853 DPRINTF("Lower OpenPIC INT output\n"); |
|
854 qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]); |
|
855 n_IRQ = IRQ_get_next(opp, &dst->raised); |
|
856 DPRINTF("PIAC: irq=%d\n", n_IRQ); |
|
857 if (n_IRQ == -1) { |
|
858 /* No more interrupt pending */ |
|
859 retval = IPVP_VECTOR(opp->spve); |
|
860 } else { |
|
861 src = &opp->src[n_IRQ]; |
|
862 if (!test_bit(&src->ipvp, IPVP_ACTIVITY) || |
|
863 !(IPVP_PRIORITY(src->ipvp) > dst->pctp)) { |
|
864 /* - Spurious level-sensitive IRQ |
|
865 * - Priorities has been changed |
|
866 * and the pending IRQ isn't allowed anymore |
|
867 */ |
|
868 reset_bit(&src->ipvp, IPVP_ACTIVITY); |
|
869 retval = IPVP_VECTOR(opp->spve); |
|
870 } else { |
|
871 /* IRQ enter servicing state */ |
|
872 IRQ_setbit(&dst->servicing, n_IRQ); |
|
873 retval = IPVP_VECTOR(src->ipvp); |
|
874 } |
|
875 IRQ_resetbit(&dst->raised, n_IRQ); |
|
876 dst->raised.next = -1; |
|
877 if (!test_bit(&src->ipvp, IPVP_SENSE)) { |
|
878 /* edge-sensitive IRQ */ |
|
879 reset_bit(&src->ipvp, IPVP_ACTIVITY); |
|
880 src->pending = 0; |
|
881 } |
|
882 } |
|
883 break; |
|
884 case 0xB0: /* PEOI */ |
|
885 retval = 0; |
|
886 break; |
|
887 #if MAX_IPI > 0 |
|
888 case 0x40: /* IDE */ |
|
889 case 0x50: |
|
890 idx = (addr - 0x40) >> 4; |
|
891 retval = read_IRQreg(opp, IRQ_IPI0 + idx, IRQ_IDE); |
|
892 break; |
|
893 #endif |
|
894 default: |
|
895 break; |
|
896 } |
|
897 DPRINTF("%s: => %08x\n", __func__, retval); |
|
898 #if defined OPENPIC_SWAP |
|
899 retval= bswap32(retval); |
|
900 #endif |
|
901 |
|
902 return retval; |
|
903 } |
|
904 |
|
905 static void openpic_buggy_write (void *opaque, |
|
906 target_phys_addr_t addr, uint32_t val) |
|
907 { |
|
908 printf("Invalid OPENPIC write access !\n"); |
|
909 } |
|
910 |
|
911 static uint32_t openpic_buggy_read (void *opaque, target_phys_addr_t addr) |
|
912 { |
|
913 printf("Invalid OPENPIC read access !\n"); |
|
914 |
|
915 return -1; |
|
916 } |
|
917 |
|
918 static void openpic_writel (void *opaque, |
|
919 target_phys_addr_t addr, uint32_t val) |
|
920 { |
|
921 openpic_t *opp = opaque; |
|
922 |
|
923 addr &= 0x3FFFF; |
|
924 DPRINTF("%s: offset %08x val: %08x\n", __func__, (int)addr, val); |
|
925 if (addr < 0x1100) { |
|
926 /* Global registers */ |
|
927 openpic_gbl_write(opp, addr, val); |
|
928 } else if (addr < 0x10000) { |
|
929 /* Timers registers */ |
|
930 openpic_timer_write(opp, addr, val); |
|
931 } else if (addr < 0x20000) { |
|
932 /* Source registers */ |
|
933 openpic_src_write(opp, addr, val); |
|
934 } else { |
|
935 /* CPU registers */ |
|
936 openpic_cpu_write(opp, addr, val); |
|
937 } |
|
938 } |
|
939 |
|
940 static uint32_t openpic_readl (void *opaque,target_phys_addr_t addr) |
|
941 { |
|
942 openpic_t *opp = opaque; |
|
943 uint32_t retval; |
|
944 |
|
945 addr &= 0x3FFFF; |
|
946 DPRINTF("%s: offset %08x\n", __func__, (int)addr); |
|
947 if (addr < 0x1100) { |
|
948 /* Global registers */ |
|
949 retval = openpic_gbl_read(opp, addr); |
|
950 } else if (addr < 0x10000) { |
|
951 /* Timers registers */ |
|
952 retval = openpic_timer_read(opp, addr); |
|
953 } else if (addr < 0x20000) { |
|
954 /* Source registers */ |
|
955 retval = openpic_src_read(opp, addr); |
|
956 } else { |
|
957 /* CPU registers */ |
|
958 retval = openpic_cpu_read(opp, addr); |
|
959 } |
|
960 |
|
961 return retval; |
|
962 } |
|
963 |
|
964 static CPUWriteMemoryFunc *openpic_write[] = { |
|
965 &openpic_buggy_write, |
|
966 &openpic_buggy_write, |
|
967 &openpic_writel, |
|
968 }; |
|
969 |
|
970 static CPUReadMemoryFunc *openpic_read[] = { |
|
971 &openpic_buggy_read, |
|
972 &openpic_buggy_read, |
|
973 &openpic_readl, |
|
974 }; |
|
975 |
|
976 static void openpic_map(PCIDevice *pci_dev, int region_num, |
|
977 uint32_t addr, uint32_t size, int type) |
|
978 { |
|
979 openpic_t *opp; |
|
980 |
|
981 DPRINTF("Map OpenPIC\n"); |
|
982 opp = (openpic_t *)pci_dev; |
|
983 /* Global registers */ |
|
984 DPRINTF("Register OPENPIC gbl %08x => %08x\n", |
|
985 addr + 0x1000, addr + 0x1000 + 0x100); |
|
986 /* Timer registers */ |
|
987 DPRINTF("Register OPENPIC timer %08x => %08x\n", |
|
988 addr + 0x1100, addr + 0x1100 + 0x40 * MAX_TMR); |
|
989 /* Interrupt source registers */ |
|
990 DPRINTF("Register OPENPIC src %08x => %08x\n", |
|
991 addr + 0x10000, addr + 0x10000 + 0x20 * (EXT_IRQ + 2)); |
|
992 /* Per CPU registers */ |
|
993 DPRINTF("Register OPENPIC dst %08x => %08x\n", |
|
994 addr + 0x20000, addr + 0x20000 + 0x1000 * MAX_CPU); |
|
995 cpu_register_physical_memory(addr, 0x40000, opp->mem_index); |
|
996 #if 0 // Don't implement ISU for now |
|
997 opp_io_memory = cpu_register_io_memory(0, openpic_src_read, |
|
998 openpic_src_write); |
|
999 cpu_register_physical_memory(isu_base, 0x20 * (EXT_IRQ + 2), |
|
1000 opp_io_memory); |
|
1001 #endif |
|
1002 } |
|
1003 |
|
1004 qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus, |
|
1005 qemu_irq **irqs, qemu_irq irq_out) |
|
1006 { |
|
1007 openpic_t *opp; |
|
1008 uint8_t *pci_conf; |
|
1009 int i, m; |
|
1010 |
|
1011 /* XXX: for now, only one CPU is supported */ |
|
1012 if (nb_cpus != 1) |
|
1013 return NULL; |
|
1014 if (bus) { |
|
1015 opp = (openpic_t *)pci_register_device(bus, "OpenPIC", sizeof(openpic_t), |
|
1016 -1, NULL, NULL); |
|
1017 if (opp == NULL) |
|
1018 return NULL; |
|
1019 pci_conf = opp->pci_dev.config; |
|
1020 pci_conf[0x00] = 0x14; // IBM MPIC2 |
|
1021 pci_conf[0x01] = 0x10; |
|
1022 pci_conf[0x02] = 0xFF; |
|
1023 pci_conf[0x03] = 0xFF; |
|
1024 pci_conf[0x0a] = 0x80; // PIC |
|
1025 pci_conf[0x0b] = 0x08; |
|
1026 pci_conf[0x0e] = 0x00; // header_type |
|
1027 pci_conf[0x3d] = 0x00; // no interrupt pin |
|
1028 |
|
1029 /* Register I/O spaces */ |
|
1030 pci_register_io_region((PCIDevice *)opp, 0, 0x40000, |
|
1031 PCI_ADDRESS_SPACE_MEM, &openpic_map); |
|
1032 } else { |
|
1033 opp = qemu_mallocz(sizeof(openpic_t)); |
|
1034 } |
|
1035 opp->mem_index = cpu_register_io_memory(0, openpic_read, |
|
1036 openpic_write, opp); |
|
1037 |
|
1038 // isu_base &= 0xFFFC0000; |
|
1039 opp->nb_cpus = nb_cpus; |
|
1040 /* Set IRQ types */ |
|
1041 for (i = 0; i < EXT_IRQ; i++) { |
|
1042 opp->src[i].type = IRQ_EXTERNAL; |
|
1043 } |
|
1044 for (; i < IRQ_TIM0; i++) { |
|
1045 opp->src[i].type = IRQ_SPECIAL; |
|
1046 } |
|
1047 #if MAX_IPI > 0 |
|
1048 m = IRQ_IPI0; |
|
1049 #else |
|
1050 m = IRQ_DBL0; |
|
1051 #endif |
|
1052 for (; i < m; i++) { |
|
1053 opp->src[i].type = IRQ_TIMER; |
|
1054 } |
|
1055 for (; i < MAX_IRQ; i++) { |
|
1056 opp->src[i].type = IRQ_INTERNAL; |
|
1057 } |
|
1058 for (i = 0; i < nb_cpus; i++) |
|
1059 opp->dst[i].irqs = irqs[i]; |
|
1060 opp->irq_out = irq_out; |
|
1061 openpic_reset(opp); |
|
1062 if (pmem_index) |
|
1063 *pmem_index = opp->mem_index; |
|
1064 |
|
1065 return qemu_allocate_irqs(openpic_set_irq, opp, MAX_IRQ); |
|
1066 } |