1 /*

     2  * QEMU i440FX/PIIX3 PCI Bridge Emulation

     3  *

     4  * Copyright (c) 2006 Fabrice Bellard

     5  *

     6  * Permission is hereby granted, free of charge, to any person obtaining a copy

     7  * of this software and associated documentation files (the "Software"), to deal

     8  * in the Software without restriction, including without limitation the rights

     9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

    10  * copies of the Software, and to permit persons to whom the Software is

    11  * furnished to do so, subject to the following conditions:

    12  *

    13  * The above copyright notice and this permission notice shall be included in

    14  * all copies or substantial portions of the Software.

    15  *

    16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

    17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

    18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

    19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

    20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

    21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

    22  * THE SOFTWARE.

    23  */

    24 

    25 #include "hw.h"

    26 #include "pc.h"

    27 #include "pci.h"

    28 

    29 typedef uint32_t pci_addr_t;

    30 #include "pci_host.h"

    31 

    32 typedef PCIHostState I440FXState;

    33 

    34 static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)

    35 {

    36     I440FXState *s = opaque;

    37     s->config_reg = val;

    38 }

    39 

    40 static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)

    41 {

    42     I440FXState *s = opaque;

    43     return s->config_reg;

    44 }

    45 

    46 static void piix3_set_irq(qemu_irq *pic, int irq_num, int level);

    47 

    48 /* return the global irq number corresponding to a given device irq

    49    pin. We could also use the bus number to have a more precise

    50    mapping. */

    51 static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)

    52 {

    53     int slot_addend;

    54     slot_addend = (pci_dev->devfn >> 3) - 1;

    55     return (irq_num + slot_addend) & 3;

    56 }

    57 

    58 static target_phys_addr_t isa_page_descs[384 / 4];

    59 static uint8_t smm_enabled;

    60 static int pci_irq_levels[4];

    61 

    62 static void update_pam(PCIDevice *d, uint32_t start, uint32_t end, int r)

    63 {

    64     uint32_t addr;

    65 

    66     //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);

    67     switch(r) {

    68     case 3:

    69         /* RAM */

    70         cpu_register_physical_memory(start, end - start,

    71                                      start);

    72         break;

    73     case 1:

    74         /* ROM (XXX: not quite correct) */

    75         cpu_register_physical_memory(start, end - start,

    76                                      start | IO_MEM_ROM);

    77         break;

    78     case 2:

    79     case 0:

    80         /* XXX: should distinguish read/write cases */

    81         for(addr = start; addr < end; addr += 4096) {

    82             cpu_register_physical_memory(addr, 4096,

    83                                          isa_page_descs[(addr - 0xa0000) >> 12]);

    84         }

    85         break;

    86     }

    87 }

    88 

    89 static void i440fx_update_memory_mappings(PCIDevice *d)

    90 {

    91     int i, r;

    92     uint32_t smram, addr;

    93 

    94     update_pam(d, 0xf0000, 0x100000, (d->config[0x59] >> 4) & 3);

    95     for(i = 0; i < 12; i++) {

    96         r = (d->config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3;

    97         update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);

    98     }

    99     smram = d->config[0x72];

   100     if ((smm_enabled && (smram & 0x08)) || (smram & 0x40)) {

   101         cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);

   102     } else {

   103         for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {

   104             cpu_register_physical_memory(addr, 4096,

   105                                          isa_page_descs[(addr - 0xa0000) >> 12]);

   106         }

   107     }

   108 }

   109 

   110 void i440fx_set_smm(PCIDevice *d, int val)

   111 {

   112     val = (val != 0);

   113     if (smm_enabled != val) {

   114         smm_enabled = val;

   115         i440fx_update_memory_mappings(d);

   116     }

   117 }

   118 

   119 

   120 /* XXX: suppress when better memory API. We make the assumption that

   121    no device (in particular the VGA) changes the memory mappings in

   122    the 0xa0000-0x100000 range */

   123 void i440fx_init_memory_mappings(PCIDevice *d)

   124 {

   125     int i;

   126     for(i = 0; i < 96; i++) {

   127         isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);

   128     }

   129 }

   130 

   131 static void i440fx_write_config(PCIDevice *d,

   132                                 uint32_t address, uint32_t val, int len)

   133 {

   134     /* XXX: implement SMRAM.D_LOCK */

   135     pci_default_write_config(d, address, val, len);

   136     if ((address >= 0x59 && address <= 0x5f) || address == 0x72)

   137         i440fx_update_memory_mappings(d);

   138 }

   139 

   140 static void i440fx_save(QEMUFile* f, void *opaque)

   141 {

   142     PCIDevice *d = opaque;

   143     int i;

   144 

   145     pci_device_save(d, f);

   146     qemu_put_8s(f, &smm_enabled);

   147 

   148     for (i = 0; i < 4; i++)

   149         qemu_put_be32(f, pci_irq_levels[i]);

   150 }

   151 

   152 static int i440fx_load(QEMUFile* f, void *opaque, int version_id)

   153 {

   154     PCIDevice *d = opaque;

   155     int ret, i;

   156 

   157     if (version_id > 2)

   158         return -EINVAL;

   159     ret = pci_device_load(d, f);

   160     if (ret < 0)

   161         return ret;

   162     i440fx_update_memory_mappings(d);

   163     qemu_get_8s(f, &smm_enabled);

   164 

   165     if (version_id >= 2)

   166         for (i = 0; i < 4; i++)

   167             pci_irq_levels[i] = qemu_get_be32(f);

   168 

   169     return 0;

   170 }

   171 

   172 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic)

   173 {

   174     PCIBus *b;

   175     PCIDevice *d;

   176     I440FXState *s;

   177 

   178     s = qemu_mallocz(sizeof(I440FXState));

   179     b = pci_register_bus(piix3_set_irq, pci_slot_get_pirq, pic, 0, 4);

   180     s->bus = b;

   181 

   182     register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);

   183     register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s);

   184 

   185     register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);

   186     register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);

   187     register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);

   188     register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);

   189     register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);

   190     register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);

   191 

   192     d = pci_register_device(b, "i440FX", sizeof(PCIDevice), 0,

   193                             NULL, i440fx_write_config);

   194 

   195     d->config[0x00] = 0x86; // vendor_id

   196     d->config[0x01] = 0x80;

   197     d->config[0x02] = 0x37; // device_id

   198     d->config[0x03] = 0x12;

   199     d->config[0x08] = 0x02; // revision

   200     d->config[0x0a] = 0x00; // class_sub = host2pci

   201     d->config[0x0b] = 0x06; // class_base = PCI_bridge

   202     d->config[0x0e] = 0x00; // header_type

   203 

   204     d->config[0x72] = 0x02; /* SMRAM */

   205 

   206     register_savevm("I440FX", 0, 2, i440fx_save, i440fx_load, d);

   207     *pi440fx_state = d;

   208     return b;

   209 }

   210 

   211 /* PIIX3 PCI to ISA bridge */

   212 

   213 static PCIDevice *piix3_dev;

   214 PCIDevice *piix4_dev;

   215 

   216 /* just used for simpler irq handling. */

   217 #define PCI_IRQ_WORDS   ((PCI_DEVICES_MAX + 31) / 32)

   218 

   219 static void piix3_set_irq(qemu_irq *pic, int irq_num, int level)

   220 {

   221     int i, pic_irq, pic_level;

   222 

   223     pci_irq_levels[irq_num] = level;

   224 

   225     /* now we change the pic irq level according to the piix irq mappings */

   226     /* XXX: optimize */

   227     pic_irq = piix3_dev->config[0x60 + irq_num];

   228     if (pic_irq < 16) {

   229         /* The pic level is the logical OR of all the PCI irqs mapped

   230            to it */

   231         pic_level = 0;

   232         for (i = 0; i < 4; i++) {

   233             if (pic_irq == piix3_dev->config[0x60 + i])

   234                 pic_level |= pci_irq_levels[i];

   235         }

   236         qemu_set_irq(pic[pic_irq], pic_level);

   237     }

   238 }

   239 

   240 static void piix3_reset(PCIDevice *d)

   241 {

   242     uint8_t *pci_conf = d->config;

   243 

   244     pci_conf[0x04] = 0x07; // master, memory and I/O

   245     pci_conf[0x05] = 0x00;

   246     pci_conf[0x06] = 0x00;

   247     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium

   248     pci_conf[0x4c] = 0x4d;

   249     pci_conf[0x4e] = 0x03;

   250     pci_conf[0x4f] = 0x00;

   251     pci_conf[0x60] = 0x80;

   252     pci_conf[0x61] = 0x80;

   253     pci_conf[0x62] = 0x80;

   254     pci_conf[0x63] = 0x80;

   255     pci_conf[0x69] = 0x02;

   256     pci_conf[0x70] = 0x80;

   257     pci_conf[0x76] = 0x0c;

   258     pci_conf[0x77] = 0x0c;

   259     pci_conf[0x78] = 0x02;

   260     pci_conf[0x79] = 0x00;

   261     pci_conf[0x80] = 0x00;

   262     pci_conf[0x82] = 0x00;

   263     pci_conf[0xa0] = 0x08;

   264     pci_conf[0xa2] = 0x00;

   265     pci_conf[0xa3] = 0x00;

   266     pci_conf[0xa4] = 0x00;

   267     pci_conf[0xa5] = 0x00;

   268     pci_conf[0xa6] = 0x00;

   269     pci_conf[0xa7] = 0x00;

   270     pci_conf[0xa8] = 0x0f;

   271     pci_conf[0xaa] = 0x00;

   272     pci_conf[0xab] = 0x00;

   273     pci_conf[0xac] = 0x00;

   274     pci_conf[0xae] = 0x00;

   275 }

   276 

   277 static void piix4_reset(PCIDevice *d)

   278 {

   279     uint8_t *pci_conf = d->config;

   280 

   281     pci_conf[0x04] = 0x07; // master, memory and I/O

   282     pci_conf[0x05] = 0x00;

   283     pci_conf[0x06] = 0x00;

   284     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium

   285     pci_conf[0x4c] = 0x4d;

   286     pci_conf[0x4e] = 0x03;

   287     pci_conf[0x4f] = 0x00;

   288     pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10

   289     pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10

   290     pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11

   291     pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11

   292     pci_conf[0x69] = 0x02;

   293     pci_conf[0x70] = 0x80;

   294     pci_conf[0x76] = 0x0c;

   295     pci_conf[0x77] = 0x0c;

   296     pci_conf[0x78] = 0x02;

   297     pci_conf[0x79] = 0x00;

   298     pci_conf[0x80] = 0x00;

   299     pci_conf[0x82] = 0x00;

   300     pci_conf[0xa0] = 0x08;

   301     pci_conf[0xa2] = 0x00;

   302     pci_conf[0xa3] = 0x00;

   303     pci_conf[0xa4] = 0x00;

   304     pci_conf[0xa5] = 0x00;

   305     pci_conf[0xa6] = 0x00;

   306     pci_conf[0xa7] = 0x00;

   307     pci_conf[0xa8] = 0x0f;

   308     pci_conf[0xaa] = 0x00;

   309     pci_conf[0xab] = 0x00;

   310     pci_conf[0xac] = 0x00;

   311     pci_conf[0xae] = 0x00;

   312 }

   313 

   314 static void piix_save(QEMUFile* f, void *opaque)

   315 {

   316     PCIDevice *d = opaque;

   317     pci_device_save(d, f);

   318 }

   319 

   320 static int piix_load(QEMUFile* f, void *opaque, int version_id)

   321 {

   322     PCIDevice *d = opaque;

   323     if (version_id != 2)

   324         return -EINVAL;

   325     return pci_device_load(d, f);

   326 }

   327 

   328 int piix3_init(PCIBus *bus, int devfn)

   329 {

   330     PCIDevice *d;

   331     uint8_t *pci_conf;

   332 

   333     d = pci_register_device(bus, "PIIX3", sizeof(PCIDevice),

   334                                     devfn, NULL, NULL);

   335     register_savevm("PIIX3", 0, 2, piix_save, piix_load, d);

   336 

   337     piix3_dev = d;

   338     pci_conf = d->config;

   339 

   340     pci_conf[0x00] = 0x86; // Intel

   341     pci_conf[0x01] = 0x80;

   342     pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)

   343     pci_conf[0x03] = 0x70;

   344     pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA

   345     pci_conf[0x0b] = 0x06; // class_base = PCI_bridge

   346     pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic

   347 

   348     piix3_reset(d);

   349     return d->devfn;

   350 }

   351 

   352 int piix4_init(PCIBus *bus, int devfn)

   353 {

   354     PCIDevice *d;

   355     uint8_t *pci_conf;

   356 

   357     d = pci_register_device(bus, "PIIX4", sizeof(PCIDevice),

   358                                     devfn, NULL, NULL);

   359     register_savevm("PIIX4", 0, 2, piix_save, piix_load, d);

   360 

   361     piix4_dev = d;

   362     pci_conf = d->config;

   363 

   364     pci_conf[0x00] = 0x86; // Intel

   365     pci_conf[0x01] = 0x80;

   366     pci_conf[0x02] = 0x10; // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge

   367     pci_conf[0x03] = 0x71;

   368     pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA

   369     pci_conf[0x0b] = 0x06; // class_base = PCI_bridge

   370     pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic

   371 

   372     piix4_reset(d);

   373     return d->devfn;

   374 }