1 /*

     2  * QEMU PowerPC 405 embedded processors emulation

     3  *

     4  * Copyright (c) 2007 Jocelyn Mayer

     5  *

     6  * Permission is hereby granted, free of charge, to any person obtaining a copy

     7  * of this software and associated documentation files (the "Software"), to deal

     8  * in the Software without restriction, including without limitation the rights

     9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

    10  * copies of the Software, and to permit persons to whom the Software is

    11  * furnished to do so, subject to the following conditions:

    12  *

    13  * The above copyright notice and this permission notice shall be included in

    14  * all copies or substantial portions of the Software.

    15  *

    16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

    17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

    18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

    19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

    20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

    21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

    22  * THE SOFTWARE.

    23  */

    24 #include "hw.h"

    25 #include "ppc.h"

    26 #include "ppc405.h"

    27 #include "pc.h"

    28 #include "qemu-timer.h"

    29 #include "sysemu.h"

    30 #include "qemu-log.h"

    31 

    32 #define DEBUG_OPBA

    33 #define DEBUG_SDRAM

    34 #define DEBUG_GPIO

    35 #define DEBUG_SERIAL

    36 #define DEBUG_OCM

    37 //#define DEBUG_I2C

    38 #define DEBUG_GPT

    39 #define DEBUG_MAL

    40 #define DEBUG_CLOCKS

    41 //#define DEBUG_CLOCKS_LL

    42 

    43 ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,

    44                                 uint32_t flags)

    45 {

    46     ram_addr_t bdloc;

    47     int i, n;

    48 

    49     /* We put the bd structure at the top of memory */

    50     if (bd->bi_memsize >= 0x01000000UL)

    51         bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);

    52     else

    53         bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);

    54     stl_raw(phys_ram_base + bdloc + 0x00, bd->bi_memstart);

    55     stl_raw(phys_ram_base + bdloc + 0x04, bd->bi_memsize);

    56     stl_raw(phys_ram_base + bdloc + 0x08, bd->bi_flashstart);

    57     stl_raw(phys_ram_base + bdloc + 0x0C, bd->bi_flashsize);

    58     stl_raw(phys_ram_base + bdloc + 0x10, bd->bi_flashoffset);

    59     stl_raw(phys_ram_base + bdloc + 0x14, bd->bi_sramstart);

    60     stl_raw(phys_ram_base + bdloc + 0x18, bd->bi_sramsize);

    61     stl_raw(phys_ram_base + bdloc + 0x1C, bd->bi_bootflags);

    62     stl_raw(phys_ram_base + bdloc + 0x20, bd->bi_ipaddr);

    63     for (i = 0; i < 6; i++)

    64         stb_raw(phys_ram_base + bdloc + 0x24 + i, bd->bi_enetaddr[i]);

    65     stw_raw(phys_ram_base + bdloc + 0x2A, bd->bi_ethspeed);

    66     stl_raw(phys_ram_base + bdloc + 0x2C, bd->bi_intfreq);

    67     stl_raw(phys_ram_base + bdloc + 0x30, bd->bi_busfreq);

    68     stl_raw(phys_ram_base + bdloc + 0x34, bd->bi_baudrate);

    69     for (i = 0; i < 4; i++)

    70         stb_raw(phys_ram_base + bdloc + 0x38 + i, bd->bi_s_version[i]);

    71     for (i = 0; i < 32; i++)

    72         stb_raw(phys_ram_base + bdloc + 0x3C + i, bd->bi_s_version[i]);

    73     stl_raw(phys_ram_base + bdloc + 0x5C, bd->bi_plb_busfreq);

    74     stl_raw(phys_ram_base + bdloc + 0x60, bd->bi_pci_busfreq);

    75     for (i = 0; i < 6; i++)

    76         stb_raw(phys_ram_base + bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);

    77     n = 0x6A;

    78     if (flags & 0x00000001) {

    79         for (i = 0; i < 6; i++)

    80             stb_raw(phys_ram_base + bdloc + n++, bd->bi_pci_enetaddr2[i]);

    81     }

    82     stl_raw(phys_ram_base + bdloc + n, bd->bi_opbfreq);

    83     n += 4;

    84     for (i = 0; i < 2; i++) {

    85         stl_raw(phys_ram_base + bdloc + n, bd->bi_iic_fast[i]);

    86         n += 4;

    87     }

    88 

    89     return bdloc;

    90 }

    91 

    92 /*****************************************************************************/

    93 /* Shared peripherals */

    94 

    95 /*****************************************************************************/

    96 /* Peripheral local bus arbitrer */

    97 enum {

    98     PLB0_BESR = 0x084,

    99     PLB0_BEAR = 0x086,

   100     PLB0_ACR  = 0x087,

   101 };

   102 

   103 typedef struct ppc4xx_plb_t ppc4xx_plb_t;

   104 struct ppc4xx_plb_t {

   105     uint32_t acr;

   106     uint32_t bear;

   107     uint32_t besr;

   108 };

   109 

   110 static target_ulong dcr_read_plb (void *opaque, int dcrn)

   111 {

   112     ppc4xx_plb_t *plb;

   113     target_ulong ret;

   114 

   115     plb = opaque;

   116     switch (dcrn) {

   117     case PLB0_ACR:

   118         ret = plb->acr;

   119         break;

   120     case PLB0_BEAR:

   121         ret = plb->bear;

   122         break;

   123     case PLB0_BESR:

   124         ret = plb->besr;

   125         break;

   126     default:

   127         /* Avoid gcc warning */

   128         ret = 0;

   129         break;

   130     }

   131 

   132     return ret;

   133 }

   134 

   135 static void dcr_write_plb (void *opaque, int dcrn, target_ulong val)

   136 {

   137     ppc4xx_plb_t *plb;

   138 

   139     plb = opaque;

   140     switch (dcrn) {

   141     case PLB0_ACR:

   142         /* We don't care about the actual parameters written as

   143          * we don't manage any priorities on the bus

   144          */

   145         plb->acr = val & 0xF8000000;

   146         break;

   147     case PLB0_BEAR:

   148         /* Read only */

   149         break;

   150     case PLB0_BESR:

   151         /* Write-clear */

   152         plb->besr &= ~val;

   153         break;

   154     }

   155 }

   156 

   157 static void ppc4xx_plb_reset (void *opaque)

   158 {

   159     ppc4xx_plb_t *plb;

   160 

   161     plb = opaque;

   162     plb->acr = 0x00000000;

   163     plb->bear = 0x00000000;

   164     plb->besr = 0x00000000;

   165 }

   166 

   167 void ppc4xx_plb_init (CPUState *env)

   168 {

   169     ppc4xx_plb_t *plb;

   170 

   171     plb = qemu_mallocz(sizeof(ppc4xx_plb_t));

   172     if (plb != NULL) {

   173         ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);

   174         ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);

   175         ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);

   176         ppc4xx_plb_reset(plb);

   177         qemu_register_reset(ppc4xx_plb_reset, plb);

   178     }

   179 }

   180 

   181 /*****************************************************************************/

   182 /* PLB to OPB bridge */

   183 enum {

   184     POB0_BESR0 = 0x0A0,

   185     POB0_BESR1 = 0x0A2,

   186     POB0_BEAR  = 0x0A4,

   187 };

   188 

   189 typedef struct ppc4xx_pob_t ppc4xx_pob_t;

   190 struct ppc4xx_pob_t {

   191     uint32_t bear;

   192     uint32_t besr[2];

   193 };

   194 

   195 static target_ulong dcr_read_pob (void *opaque, int dcrn)

   196 {

   197     ppc4xx_pob_t *pob;

   198     target_ulong ret;

   199 

   200     pob = opaque;

   201     switch (dcrn) {

   202     case POB0_BEAR:

   203         ret = pob->bear;

   204         break;

   205     case POB0_BESR0:

   206     case POB0_BESR1:

   207         ret = pob->besr[dcrn - POB0_BESR0];

   208         break;

   209     default:

   210         /* Avoid gcc warning */

   211         ret = 0;

   212         break;

   213     }

   214 

   215     return ret;

   216 }

   217 

   218 static void dcr_write_pob (void *opaque, int dcrn, target_ulong val)

   219 {

   220     ppc4xx_pob_t *pob;

   221 

   222     pob = opaque;

   223     switch (dcrn) {

   224     case POB0_BEAR:

   225         /* Read only */

   226         break;

   227     case POB0_BESR0:

   228     case POB0_BESR1:

   229         /* Write-clear */

   230         pob->besr[dcrn - POB0_BESR0] &= ~val;

   231         break;

   232     }

   233 }

   234 

   235 static void ppc4xx_pob_reset (void *opaque)

   236 {

   237     ppc4xx_pob_t *pob;

   238 

   239     pob = opaque;

   240     /* No error */

   241     pob->bear = 0x00000000;

   242     pob->besr[0] = 0x0000000;

   243     pob->besr[1] = 0x0000000;

   244 }

   245 

   246 void ppc4xx_pob_init (CPUState *env)

   247 {

   248     ppc4xx_pob_t *pob;

   249 

   250     pob = qemu_mallocz(sizeof(ppc4xx_pob_t));

   251     if (pob != NULL) {

   252         ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);

   253         ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);

   254         ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);

   255         qemu_register_reset(ppc4xx_pob_reset, pob);

   256         ppc4xx_pob_reset(env);

   257     }

   258 }

   259 

   260 /*****************************************************************************/

   261 /* OPB arbitrer */

   262 typedef struct ppc4xx_opba_t ppc4xx_opba_t;

   263 struct ppc4xx_opba_t {

   264     target_phys_addr_t base;

   265     uint8_t cr;

   266     uint8_t pr;

   267 };

   268 

   269 static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)

   270 {

   271     ppc4xx_opba_t *opba;

   272     uint32_t ret;

   273 

   274 #ifdef DEBUG_OPBA

   275     printf("%s: addr " PADDRX "\n", __func__, addr);

   276 #endif

   277     opba = opaque;

   278     switch (addr - opba->base) {

   279     case 0x00:

   280         ret = opba->cr;

   281         break;

   282     case 0x01:

   283         ret = opba->pr;

   284         break;

   285     default:

   286         ret = 0x00;

   287         break;

   288     }

   289 

   290     return ret;

   291 }

   292 

   293 static void opba_writeb (void *opaque,

   294                          target_phys_addr_t addr, uint32_t value)

   295 {

   296     ppc4xx_opba_t *opba;

   297 

   298 #ifdef DEBUG_OPBA

   299     printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);

   300 #endif

   301     opba = opaque;

   302     switch (addr - opba->base) {

   303     case 0x00:

   304         opba->cr = value & 0xF8;

   305         break;

   306     case 0x01:

   307         opba->pr = value & 0xFF;

   308         break;

   309     default:

   310         break;

   311     }

   312 }

   313 

   314 static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)

   315 {

   316     uint32_t ret;

   317 

   318 #ifdef DEBUG_OPBA

   319     printf("%s: addr " PADDRX "\n", __func__, addr);

   320 #endif

   321     ret = opba_readb(opaque, addr) << 8;

   322     ret |= opba_readb(opaque, addr + 1);

   323 

   324     return ret;

   325 }

   326 

   327 static void opba_writew (void *opaque,

   328                          target_phys_addr_t addr, uint32_t value)

   329 {

   330 #ifdef DEBUG_OPBA

   331     printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);

   332 #endif

   333     opba_writeb(opaque, addr, value >> 8);

   334     opba_writeb(opaque, addr + 1, value);

   335 }

   336 

   337 static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)

   338 {

   339     uint32_t ret;

   340 

   341 #ifdef DEBUG_OPBA

   342     printf("%s: addr " PADDRX "\n", __func__, addr);

   343 #endif

   344     ret = opba_readb(opaque, addr) << 24;

   345     ret |= opba_readb(opaque, addr + 1) << 16;

   346 

   347     return ret;

   348 }

   349 

   350 static void opba_writel (void *opaque,

   351                          target_phys_addr_t addr, uint32_t value)

   352 {

   353 #ifdef DEBUG_OPBA

   354     printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);

   355 #endif

   356     opba_writeb(opaque, addr, value >> 24);

   357     opba_writeb(opaque, addr + 1, value >> 16);

   358 }

   359 

   360 static CPUReadMemoryFunc *opba_read[] = {

   361     &opba_readb,

   362     &opba_readw,

   363     &opba_readl,

   364 };

   365 

   366 static CPUWriteMemoryFunc *opba_write[] = {

   367     &opba_writeb,

   368     &opba_writew,

   369     &opba_writel,

   370 };

   371 

   372 static void ppc4xx_opba_reset (void *opaque)

   373 {

   374     ppc4xx_opba_t *opba;

   375 

   376     opba = opaque;

   377     opba->cr = 0x00; /* No dynamic priorities - park disabled */

   378     opba->pr = 0x11;

   379 }

   380 

   381 void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,

   382                        target_phys_addr_t offset)

   383 {

   384     ppc4xx_opba_t *opba;

   385 

   386     opba = qemu_mallocz(sizeof(ppc4xx_opba_t));

   387     if (opba != NULL) {

   388         opba->base = offset;

   389 #ifdef DEBUG_OPBA

   390         printf("%s: offset " PADDRX "\n", __func__, offset);

   391 #endif

   392         ppc4xx_mmio_register(env, mmio, offset, 0x002,

   393                              opba_read, opba_write, opba);

   394         qemu_register_reset(ppc4xx_opba_reset, opba);

   395         ppc4xx_opba_reset(opba);

   396     }

   397 }

   398 

   399 /*****************************************************************************/

   400 /* Code decompression controller */

   401 /* XXX: TODO */

   402 

   403 /*****************************************************************************/

   404 /* Peripheral controller */

   405 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;

   406 struct ppc4xx_ebc_t {

   407     uint32_t addr;

   408     uint32_t bcr[8];

   409     uint32_t bap[8];

   410     uint32_t bear;

   411     uint32_t besr0;

   412     uint32_t besr1;

   413     uint32_t cfg;

   414 };

   415 

   416 enum {

   417     EBC0_CFGADDR = 0x012,

   418     EBC0_CFGDATA = 0x013,

   419 };

   420 

   421 static target_ulong dcr_read_ebc (void *opaque, int dcrn)

   422 {

   423     ppc4xx_ebc_t *ebc;

   424     target_ulong ret;

   425 

   426     ebc = opaque;

   427     switch (dcrn) {

   428     case EBC0_CFGADDR:

   429         ret = ebc->addr;

   430         break;

   431     case EBC0_CFGDATA:

   432         switch (ebc->addr) {

   433         case 0x00: /* B0CR */

   434             ret = ebc->bcr[0];

   435             break;

   436         case 0x01: /* B1CR */

   437             ret = ebc->bcr[1];

   438             break;

   439         case 0x02: /* B2CR */

   440             ret = ebc->bcr[2];

   441             break;

   442         case 0x03: /* B3CR */

   443             ret = ebc->bcr[3];

   444             break;

   445         case 0x04: /* B4CR */

   446             ret = ebc->bcr[4];

   447             break;

   448         case 0x05: /* B5CR */

   449             ret = ebc->bcr[5];

   450             break;

   451         case 0x06: /* B6CR */

   452             ret = ebc->bcr[6];

   453             break;

   454         case 0x07: /* B7CR */

   455             ret = ebc->bcr[7];

   456             break;

   457         case 0x10: /* B0AP */

   458             ret = ebc->bap[0];

   459             break;

   460         case 0x11: /* B1AP */

   461             ret = ebc->bap[1];

   462             break;

   463         case 0x12: /* B2AP */

   464             ret = ebc->bap[2];

   465             break;

   466         case 0x13: /* B3AP */

   467             ret = ebc->bap[3];

   468             break;

   469         case 0x14: /* B4AP */

   470             ret = ebc->bap[4];

   471             break;

   472         case 0x15: /* B5AP */

   473             ret = ebc->bap[5];

   474             break;

   475         case 0x16: /* B6AP */

   476             ret = ebc->bap[6];

   477             break;

   478         case 0x17: /* B7AP */

   479             ret = ebc->bap[7];

   480             break;

   481         case 0x20: /* BEAR */

   482             ret = ebc->bear;

   483             break;

   484         case 0x21: /* BESR0 */

   485             ret = ebc->besr0;

   486             break;

   487         case 0x22: /* BESR1 */

   488             ret = ebc->besr1;

   489             break;

   490         case 0x23: /* CFG */

   491             ret = ebc->cfg;

   492             break;

   493         default:

   494             ret = 0x00000000;

   495             break;

   496         }

   497     default:

   498         ret = 0x00000000;

   499         break;

   500     }

   501 

   502     return ret;

   503 }

   504 

   505 static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val)

   506 {

   507     ppc4xx_ebc_t *ebc;

   508 

   509     ebc = opaque;

   510     switch (dcrn) {

   511     case EBC0_CFGADDR:

   512         ebc->addr = val;

   513         break;

   514     case EBC0_CFGDATA:

   515         switch (ebc->addr) {

   516         case 0x00: /* B0CR */

   517             break;

   518         case 0x01: /* B1CR */

   519             break;

   520         case 0x02: /* B2CR */

   521             break;

   522         case 0x03: /* B3CR */

   523             break;

   524         case 0x04: /* B4CR */

   525             break;

   526         case 0x05: /* B5CR */

   527             break;

   528         case 0x06: /* B6CR */

   529             break;

   530         case 0x07: /* B7CR */

   531             break;

   532         case 0x10: /* B0AP */

   533             break;

   534         case 0x11: /* B1AP */

   535             break;

   536         case 0x12: /* B2AP */

   537             break;

   538         case 0x13: /* B3AP */

   539             break;

   540         case 0x14: /* B4AP */

   541             break;

   542         case 0x15: /* B5AP */

   543             break;

   544         case 0x16: /* B6AP */

   545             break;

   546         case 0x17: /* B7AP */

   547             break;

   548         case 0x20: /* BEAR */

   549             break;

   550         case 0x21: /* BESR0 */

   551             break;

   552         case 0x22: /* BESR1 */

   553             break;

   554         case 0x23: /* CFG */

   555             break;

   556         default:

   557             break;

   558         }

   559         break;

   560     default:

   561         break;

   562     }

   563 }

   564 

   565 static void ebc_reset (void *opaque)

   566 {

   567     ppc4xx_ebc_t *ebc;

   568     int i;

   569 

   570     ebc = opaque;

   571     ebc->addr = 0x00000000;

   572     ebc->bap[0] = 0x7F8FFE80;

   573     ebc->bcr[0] = 0xFFE28000;

   574     for (i = 0; i < 8; i++) {

   575         ebc->bap[i] = 0x00000000;

   576         ebc->bcr[i] = 0x00000000;

   577     }

   578     ebc->besr0 = 0x00000000;

   579     ebc->besr1 = 0x00000000;

   580     ebc->cfg = 0x80400000;

   581 }

   582 

   583 void ppc405_ebc_init (CPUState *env)

   584 {

   585     ppc4xx_ebc_t *ebc;

   586 

   587     ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t));

   588     if (ebc != NULL) {

   589         ebc_reset(ebc);

   590         qemu_register_reset(&ebc_reset, ebc);

   591         ppc_dcr_register(env, EBC0_CFGADDR,

   592                          ebc, &dcr_read_ebc, &dcr_write_ebc);

   593         ppc_dcr_register(env, EBC0_CFGDATA,

   594                          ebc, &dcr_read_ebc, &dcr_write_ebc);

   595     }

   596 }

   597 

   598 /*****************************************************************************/

   599 /* DMA controller */

   600 enum {

   601     DMA0_CR0 = 0x100,

   602     DMA0_CT0 = 0x101,

   603     DMA0_DA0 = 0x102,

   604     DMA0_SA0 = 0x103,

   605     DMA0_SG0 = 0x104,

   606     DMA0_CR1 = 0x108,

   607     DMA0_CT1 = 0x109,

   608     DMA0_DA1 = 0x10A,

   609     DMA0_SA1 = 0x10B,

   610     DMA0_SG1 = 0x10C,

   611     DMA0_CR2 = 0x110,

   612     DMA0_CT2 = 0x111,

   613     DMA0_DA2 = 0x112,

   614     DMA0_SA2 = 0x113,

   615     DMA0_SG2 = 0x114,

   616     DMA0_CR3 = 0x118,

   617     DMA0_CT3 = 0x119,

   618     DMA0_DA3 = 0x11A,

   619     DMA0_SA3 = 0x11B,

   620     DMA0_SG3 = 0x11C,

   621     DMA0_SR  = 0x120,

   622     DMA0_SGC = 0x123,

   623     DMA0_SLP = 0x125,

   624     DMA0_POL = 0x126,

   625 };

   626 

   627 typedef struct ppc405_dma_t ppc405_dma_t;

   628 struct ppc405_dma_t {

   629     qemu_irq irqs[4];

   630     uint32_t cr[4];

   631     uint32_t ct[4];

   632     uint32_t da[4];

   633     uint32_t sa[4];

   634     uint32_t sg[4];

   635     uint32_t sr;

   636     uint32_t sgc;

   637     uint32_t slp;

   638     uint32_t pol;

   639 };

   640 

   641 static target_ulong dcr_read_dma (void *opaque, int dcrn)

   642 {

   643     ppc405_dma_t *dma;

   644 

   645     dma = opaque;

   646 

   647     return 0;

   648 }

   649 

   650 static void dcr_write_dma (void *opaque, int dcrn, target_ulong val)

   651 {

   652     ppc405_dma_t *dma;

   653 

   654     dma = opaque;

   655 }

   656 

   657 static void ppc405_dma_reset (void *opaque)

   658 {

   659     ppc405_dma_t *dma;

   660     int i;

   661 

   662     dma = opaque;

   663     for (i = 0; i < 4; i++) {

   664         dma->cr[i] = 0x00000000;

   665         dma->ct[i] = 0x00000000;

   666         dma->da[i] = 0x00000000;

   667         dma->sa[i] = 0x00000000;

   668         dma->sg[i] = 0x00000000;

   669     }

   670     dma->sr = 0x00000000;

   671     dma->sgc = 0x00000000;

   672     dma->slp = 0x7C000000;

   673     dma->pol = 0x00000000;

   674 }

   675 

   676 void ppc405_dma_init (CPUState *env, qemu_irq irqs[4])

   677 {

   678     ppc405_dma_t *dma;

   679 

   680     dma = qemu_mallocz(sizeof(ppc405_dma_t));

   681     if (dma != NULL) {

   682         memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));

   683         ppc405_dma_reset(dma);

   684         qemu_register_reset(&ppc405_dma_reset, dma);

   685         ppc_dcr_register(env, DMA0_CR0,

   686                          dma, &dcr_read_dma, &dcr_write_dma);

   687         ppc_dcr_register(env, DMA0_CT0,

   688                          dma, &dcr_read_dma, &dcr_write_dma);

   689         ppc_dcr_register(env, DMA0_DA0,

   690                          dma, &dcr_read_dma, &dcr_write_dma);

   691         ppc_dcr_register(env, DMA0_SA0,

   692                          dma, &dcr_read_dma, &dcr_write_dma);

   693         ppc_dcr_register(env, DMA0_SG0,

   694                          dma, &dcr_read_dma, &dcr_write_dma);

   695         ppc_dcr_register(env, DMA0_CR1,

   696                          dma, &dcr_read_dma, &dcr_write_dma);

   697         ppc_dcr_register(env, DMA0_CT1,

   698                          dma, &dcr_read_dma, &dcr_write_dma);

   699         ppc_dcr_register(env, DMA0_DA1,

   700                          dma, &dcr_read_dma, &dcr_write_dma);

   701         ppc_dcr_register(env, DMA0_SA1,

   702                          dma, &dcr_read_dma, &dcr_write_dma);

   703         ppc_dcr_register(env, DMA0_SG1,

   704                          dma, &dcr_read_dma, &dcr_write_dma);

   705         ppc_dcr_register(env, DMA0_CR2,

   706                          dma, &dcr_read_dma, &dcr_write_dma);

   707         ppc_dcr_register(env, DMA0_CT2,

   708                          dma, &dcr_read_dma, &dcr_write_dma);

   709         ppc_dcr_register(env, DMA0_DA2,

   710                          dma, &dcr_read_dma, &dcr_write_dma);

   711         ppc_dcr_register(env, DMA0_SA2,

   712                          dma, &dcr_read_dma, &dcr_write_dma);

   713         ppc_dcr_register(env, DMA0_SG2,

   714                          dma, &dcr_read_dma, &dcr_write_dma);

   715         ppc_dcr_register(env, DMA0_CR3,

   716                          dma, &dcr_read_dma, &dcr_write_dma);

   717         ppc_dcr_register(env, DMA0_CT3,

   718                          dma, &dcr_read_dma, &dcr_write_dma);

   719         ppc_dcr_register(env, DMA0_DA3,

   720                          dma, &dcr_read_dma, &dcr_write_dma);

   721         ppc_dcr_register(env, DMA0_SA3,

   722                          dma, &dcr_read_dma, &dcr_write_dma);

   723         ppc_dcr_register(env, DMA0_SG3,

   724                          dma, &dcr_read_dma, &dcr_write_dma);

   725         ppc_dcr_register(env, DMA0_SR,

   726                          dma, &dcr_read_dma, &dcr_write_dma);

   727         ppc_dcr_register(env, DMA0_SGC,

   728                          dma, &dcr_read_dma, &dcr_write_dma);

   729         ppc_dcr_register(env, DMA0_SLP,

   730                          dma, &dcr_read_dma, &dcr_write_dma);

   731         ppc_dcr_register(env, DMA0_POL,

   732                          dma, &dcr_read_dma, &dcr_write_dma);

   733     }

   734 }

   735 

   736 /*****************************************************************************/

   737 /* GPIO */

   738 typedef struct ppc405_gpio_t ppc405_gpio_t;

   739 struct ppc405_gpio_t {

   740     target_phys_addr_t base;

   741     uint32_t or;

   742     uint32_t tcr;

   743     uint32_t osrh;

   744     uint32_t osrl;

   745     uint32_t tsrh;

   746     uint32_t tsrl;

   747     uint32_t odr;

   748     uint32_t ir;

   749     uint32_t rr1;

   750     uint32_t isr1h;

   751     uint32_t isr1l;

   752 };

   753 

   754 static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr)

   755 {

   756     ppc405_gpio_t *gpio;

   757 

   758     gpio = opaque;

   759 #ifdef DEBUG_GPIO

   760     printf("%s: addr " PADDRX "\n", __func__, addr);

   761 #endif

   762 

   763     return 0;

   764 }

   765 

   766 static void ppc405_gpio_writeb (void *opaque,

   767                                 target_phys_addr_t addr, uint32_t value)

   768 {

   769     ppc405_gpio_t *gpio;

   770 

   771     gpio = opaque;

   772 #ifdef DEBUG_GPIO

   773     printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);

   774 #endif

   775 }

   776 

   777 static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr)

   778 {

   779     ppc405_gpio_t *gpio;

   780 

   781     gpio = opaque;

   782 #ifdef DEBUG_GPIO

   783     printf("%s: addr " PADDRX "\n", __func__, addr);

   784 #endif

   785 

   786     return 0;

   787 }

   788 

   789 static void ppc405_gpio_writew (void *opaque,

   790                                 target_phys_addr_t addr, uint32_t value)

   791 {

   792     ppc405_gpio_t *gpio;

   793 

   794     gpio = opaque;

   795 #ifdef DEBUG_GPIO

   796     printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);

   797 #endif

   798 }

   799 

   800 static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr)

   801 {

   802     ppc405_gpio_t *gpio;

   803 

   804     gpio = opaque;

   805 #ifdef DEBUG_GPIO

   806     printf("%s: addr " PADDRX "\n", __func__, addr);

   807 #endif

   808 

   809     return 0;

   810 }

   811 

   812 static void ppc405_gpio_writel (void *opaque,

   813                                 target_phys_addr_t addr, uint32_t value)

   814 {

   815     ppc405_gpio_t *gpio;

   816 

   817     gpio = opaque;

   818 #ifdef DEBUG_GPIO

   819     printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);

   820 #endif

   821 }

   822 

   823 static CPUReadMemoryFunc *ppc405_gpio_read[] = {

   824     &ppc405_gpio_readb,

   825     &ppc405_gpio_readw,

   826     &ppc405_gpio_readl,

   827 };

   828 

   829 static CPUWriteMemoryFunc *ppc405_gpio_write[] = {

   830     &ppc405_gpio_writeb,

   831     &ppc405_gpio_writew,

   832     &ppc405_gpio_writel,

   833 };

   834 

   835 static void ppc405_gpio_reset (void *opaque)

   836 {

   837     ppc405_gpio_t *gpio;

   838 

   839     gpio = opaque;

   840 }

   841 

   842 void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,

   843                        target_phys_addr_t offset)

   844 {

   845     ppc405_gpio_t *gpio;

   846 

   847     gpio = qemu_mallocz(sizeof(ppc405_gpio_t));

   848     if (gpio != NULL) {

   849         gpio->base = offset;

   850         ppc405_gpio_reset(gpio);

   851         qemu_register_reset(&ppc405_gpio_reset, gpio);

   852 #ifdef DEBUG_GPIO

   853         printf("%s: offset " PADDRX "\n", __func__, offset);

   854 #endif

   855         ppc4xx_mmio_register(env, mmio, offset, 0x038,

   856                              ppc405_gpio_read, ppc405_gpio_write, gpio);

   857     }

   858 }

   859 

   860 /*****************************************************************************/

   861 /* Serial ports */

   862 static CPUReadMemoryFunc *serial_mm_read[] = {

   863     &serial_mm_readb,

   864     &serial_mm_readw,

   865     &serial_mm_readl,

   866 };

   867 

   868 static CPUWriteMemoryFunc *serial_mm_write[] = {

   869     &serial_mm_writeb,

   870     &serial_mm_writew,

   871     &serial_mm_writel,

   872 };

   873 

   874 void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,

   875                          target_phys_addr_t offset, qemu_irq irq,

   876                          CharDriverState *chr)

   877 {

   878     void *serial;

   879 

   880 #ifdef DEBUG_SERIAL

   881     printf("%s: offset " PADDRX "\n", __func__, offset);

   882 #endif

   883     serial = serial_mm_init(offset, 0, irq, 399193, chr, 0);

   884     ppc4xx_mmio_register(env, mmio, offset, 0x008,

   885                          serial_mm_read, serial_mm_write, serial);

   886 }

   887 

   888 /*****************************************************************************/

   889 /* On Chip Memory */

   890 enum {

   891     OCM0_ISARC   = 0x018,

   892     OCM0_ISACNTL = 0x019,

   893     OCM0_DSARC   = 0x01A,

   894     OCM0_DSACNTL = 0x01B,

   895 };

   896 

   897 typedef struct ppc405_ocm_t ppc405_ocm_t;

   898 struct ppc405_ocm_t {

   899     target_ulong offset;

   900     uint32_t isarc;

   901     uint32_t isacntl;

   902     uint32_t dsarc;

   903     uint32_t dsacntl;

   904 };

   905 

   906 static void ocm_update_mappings (ppc405_ocm_t *ocm,

   907                                  uint32_t isarc, uint32_t isacntl,

   908                                  uint32_t dsarc, uint32_t dsacntl)

   909 {

   910 #ifdef DEBUG_OCM

   911     printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32

   912            " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32

   913            " (%08" PRIx32 " %08" PRIx32 ")\n",

   914            isarc, isacntl, dsarc, dsacntl,

   915            ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);

   916 #endif

   917     if (ocm->isarc != isarc ||

   918         (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {

   919         if (ocm->isacntl & 0x80000000) {

   920             /* Unmap previously assigned memory region */

   921             printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);

   922             cpu_register_physical_memory(ocm->isarc, 0x04000000,

   923                                          IO_MEM_UNASSIGNED);

   924         }

   925         if (isacntl & 0x80000000) {

   926             /* Map new instruction memory region */

   927 #ifdef DEBUG_OCM

   928             printf("OCM map ISA %08" PRIx32 "\n", isarc);

   929 #endif

   930             cpu_register_physical_memory(isarc, 0x04000000,

   931                                          ocm->offset | IO_MEM_RAM);

   932         }

   933     }

   934     if (ocm->dsarc != dsarc ||

   935         (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {

   936         if (ocm->dsacntl & 0x80000000) {

   937             /* Beware not to unmap the region we just mapped */

   938             if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {

   939                 /* Unmap previously assigned memory region */

   940 #ifdef DEBUG_OCM

   941                 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);

   942 #endif

   943                 cpu_register_physical_memory(ocm->dsarc, 0x04000000,

   944                                              IO_MEM_UNASSIGNED);

   945             }

   946         }

   947         if (dsacntl & 0x80000000) {

   948             /* Beware not to remap the region we just mapped */

   949             if (!(isacntl & 0x80000000) || dsarc != isarc) {

   950                 /* Map new data memory region */

   951 #ifdef DEBUG_OCM

   952                 printf("OCM map DSA %08" PRIx32 "\n", dsarc);

   953 #endif

   954                 cpu_register_physical_memory(dsarc, 0x04000000,

   955                                              ocm->offset | IO_MEM_RAM);

   956             }

   957         }

   958     }

   959 }

   960 

   961 static target_ulong dcr_read_ocm (void *opaque, int dcrn)

   962 {

   963     ppc405_ocm_t *ocm;

   964     target_ulong ret;

   965 

   966     ocm = opaque;

   967     switch (dcrn) {

   968     case OCM0_ISARC:

   969         ret = ocm->isarc;

   970         break;

   971     case OCM0_ISACNTL:

   972         ret = ocm->isacntl;

   973         break;

   974     case OCM0_DSARC:

   975         ret = ocm->dsarc;

   976         break;

   977     case OCM0_DSACNTL:

   978         ret = ocm->dsacntl;

   979         break;

   980     default:

   981         ret = 0;

   982         break;

   983     }

   984 

   985     return ret;

   986 }

   987 

   988 static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val)

   989 {

   990     ppc405_ocm_t *ocm;

   991     uint32_t isarc, dsarc, isacntl, dsacntl;

   992 

   993     ocm = opaque;

   994     isarc = ocm->isarc;

   995     dsarc = ocm->dsarc;

   996     isacntl = ocm->isacntl;

   997     dsacntl = ocm->dsacntl;

   998     switch (dcrn) {

   999     case OCM0_ISARC:

  1000         isarc = val & 0xFC000000;

  1001         break;

  1002     case OCM0_ISACNTL:

  1003         isacntl = val & 0xC0000000;

  1004         break;

  1005     case OCM0_DSARC:

  1006         isarc = val & 0xFC000000;

  1007         break;

  1008     case OCM0_DSACNTL:

  1009         isacntl = val & 0xC0000000;

  1010         break;

  1011     }

  1012     ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);

  1013     ocm->isarc = isarc;

  1014     ocm->dsarc = dsarc;

  1015     ocm->isacntl = isacntl;

  1016     ocm->dsacntl = dsacntl;

  1017 }

  1018 

  1019 static void ocm_reset (void *opaque)

  1020 {

  1021     ppc405_ocm_t *ocm;

  1022     uint32_t isarc, dsarc, isacntl, dsacntl;

  1023 

  1024     ocm = opaque;

  1025     isarc = 0x00000000;

  1026     isacntl = 0x00000000;

  1027     dsarc = 0x00000000;

  1028     dsacntl = 0x00000000;

  1029     ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);

  1030     ocm->isarc = isarc;

  1031     ocm->dsarc = dsarc;

  1032     ocm->isacntl = isacntl;

  1033     ocm->dsacntl = dsacntl;

  1034 }

  1035 

  1036 void ppc405_ocm_init (CPUState *env, unsigned long offset)

  1037 {

  1038     ppc405_ocm_t *ocm;

  1039 

  1040     ocm = qemu_mallocz(sizeof(ppc405_ocm_t));

  1041     if (ocm != NULL) {

  1042         ocm->offset = offset;

  1043         ocm_reset(ocm);

  1044         qemu_register_reset(&ocm_reset, ocm);

  1045         ppc_dcr_register(env, OCM0_ISARC,

  1046                          ocm, &dcr_read_ocm, &dcr_write_ocm);

  1047         ppc_dcr_register(env, OCM0_ISACNTL,

  1048                          ocm, &dcr_read_ocm, &dcr_write_ocm);

  1049         ppc_dcr_register(env, OCM0_DSARC,

  1050                          ocm, &dcr_read_ocm, &dcr_write_ocm);

  1051         ppc_dcr_register(env, OCM0_DSACNTL,

  1052                          ocm, &dcr_read_ocm, &dcr_write_ocm);

  1053     }

  1054 }

  1055 

  1056 /*****************************************************************************/

  1057 /* I2C controller */

  1058 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;

  1059 struct ppc4xx_i2c_t {

  1060     target_phys_addr_t base;

  1061     qemu_irq irq;

  1062     uint8_t mdata;

  1063     uint8_t lmadr;

  1064     uint8_t hmadr;

  1065     uint8_t cntl;

  1066     uint8_t mdcntl;

  1067     uint8_t sts;

  1068     uint8_t extsts;

  1069     uint8_t sdata;

  1070     uint8_t lsadr;

  1071     uint8_t hsadr;

  1072     uint8_t clkdiv;

  1073     uint8_t intrmsk;

  1074     uint8_t xfrcnt;

  1075     uint8_t xtcntlss;

  1076     uint8_t directcntl;

  1077 };

  1078 

  1079 static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr)

  1080 {

  1081     ppc4xx_i2c_t *i2c;

  1082     uint32_t ret;

  1083 

  1084 #ifdef DEBUG_I2C

  1085     printf("%s: addr " PADDRX "\n", __func__, addr);

  1086 #endif

  1087     i2c = opaque;

  1088     switch (addr - i2c->base) {

  1089     case 0x00:

  1090         //        i2c_readbyte(&i2c->mdata);

  1091         ret = i2c->mdata;

  1092         break;

  1093     case 0x02:

  1094         ret = i2c->sdata;

  1095         break;

  1096     case 0x04:

  1097         ret = i2c->lmadr;

  1098         break;

  1099     case 0x05:

  1100         ret = i2c->hmadr;

  1101         break;

  1102     case 0x06:

  1103         ret = i2c->cntl;

  1104         break;

  1105     case 0x07:

  1106         ret = i2c->mdcntl;

  1107         break;

  1108     case 0x08:

  1109         ret = i2c->sts;

  1110         break;

  1111     case 0x09:

  1112         ret = i2c->extsts;

  1113         break;

  1114     case 0x0A:

  1115         ret = i2c->lsadr;

  1116         break;

  1117     case 0x0B:

  1118         ret = i2c->hsadr;

  1119         break;

  1120     case 0x0C:

  1121         ret = i2c->clkdiv;

  1122         break;

  1123     case 0x0D:

  1124         ret = i2c->intrmsk;

  1125         break;

  1126     case 0x0E:

  1127         ret = i2c->xfrcnt;

  1128         break;

  1129     case 0x0F:

  1130         ret = i2c->xtcntlss;

  1131         break;

  1132     case 0x10:

  1133         ret = i2c->directcntl;

  1134         break;

  1135     default: