1 /*

     2  * QEMU PowerMac emulation shared definitions and prototypes

     3  *

     4  * Copyright (c) 2004-2007 Fabrice Bellard

     5  * Copyright (c) 2007 Jocelyn Mayer

     6  *

     7  * Permission is hereby granted, free of charge, to any person obtaining a copy

     8  * of this software and associated documentation files (the "Software"), to deal

     9  * in the Software without restriction, including without limitation the rights

    10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

    11  * copies of the Software, and to permit persons to whom the Software is

    12  * furnished to do so, subject to the following conditions:

    13  *

    14  * The above copyright notice and this permission notice shall be included in

    15  * all copies or substantial portions of the Software.

    16  *

    17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

    18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

    19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

    20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

    21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

    22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

    23  * THE SOFTWARE.

    24  */

    25 #if !defined(__PPC_MAC_H__)

    26 #define __PPC_MAC_H__

    27 

    28 /* SMP is not enabled, for now */

    29 #define MAX_CPUS 1

    30 

    31 #define BIOS_FILENAME "ppc_rom.bin"

    32 #define VGABIOS_FILENAME "video.x"

    33 #define NVRAM_SIZE        0x2000

    34 

    35 #define KERNEL_LOAD_ADDR 0x01000000

    36 #define INITRD_LOAD_ADDR 0x01800000

    37 

    38 /* DBDMA */

    39 void dbdma_init (int *dbdma_mem_index);

    40 

    41 /* Cuda */

    42 void cuda_init (int *cuda_mem_index, qemu_irq irq);

    43 

    44 /* MacIO */

    45 void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index,

    46                  int dbdma_mem_index, int cuda_mem_index, void *nvram,

    47                  int nb_ide, int *ide_mem_index);

    48 

    49 /* NewWorld PowerMac IDE */

    50 int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq);

    51 

    52 /* Heathrow PIC */

    53 qemu_irq *heathrow_pic_init(int *pmem_index,

    54                             int nb_cpus, qemu_irq **irqs);

    55 

    56 /* Grackle PCI */

    57 PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic);

    58 

    59 /* UniNorth PCI */

    60 PCIBus *pci_pmac_init(qemu_irq *pic);

    61 

    62 /* Mac NVRAM */

    63 typedef struct MacIONVRAMState MacIONVRAMState;

    64 

    65 MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size);

    66 void macio_nvram_map (void *opaque, target_phys_addr_t mem_base);

    67 void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len);

    68 uint32_t macio_nvram_read (void *opaque, uint32_t addr);

    69 void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val);

    70 

    71 /* adb.c */

    72 

    73 #define MAX_ADB_DEVICES 16

    74 

    75 #define ADB_MAX_OUT_LEN 16

    76 

    77 typedef struct ADBDevice ADBDevice;

    78 

    79 /* buf = NULL means polling */

    80 typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,

    81                               const uint8_t *buf, int len);

    82 typedef int ADBDeviceReset(ADBDevice *d);

    83 

    84 struct ADBDevice {

    85     struct ADBBusState *bus;

    86     int devaddr;

    87     int handler;

    88     ADBDeviceRequest *devreq;

    89     ADBDeviceReset *devreset;

    90     void *opaque;

    91 };

    92 

    93 typedef struct ADBBusState {

    94     ADBDevice devices[MAX_ADB_DEVICES];

    95     int nb_devices;

    96     int poll_index;

    97 } ADBBusState;

    98 

    99 int adb_request(ADBBusState *s, uint8_t *buf_out,

   100                 const uint8_t *buf, int len);

   101 int adb_poll(ADBBusState *s, uint8_t *buf_out);

   102 

   103 ADBDevice *adb_register_device(ADBBusState *s, int devaddr,

   104                                ADBDeviceRequest *devreq,

   105                                ADBDeviceReset *devreset,

   106                                void *opaque);

   107 void adb_kbd_init(ADBBusState *bus);

   108 void adb_mouse_init(ADBBusState *bus);

   109 

   110 extern ADBBusState adb_bus;

   111 

   112 /* openpic.c */

   113 /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */

   114 enum {

   115     OPENPIC_OUTPUT_INT = 0, /* IRQ                       */

   116     OPENPIC_OUTPUT_CINT,    /* critical IRQ              */

   117     OPENPIC_OUTPUT_MCK,     /* Machine check event       */

   118     OPENPIC_OUTPUT_DEBUG,   /* Inconditional debug event */

   119     OPENPIC_OUTPUT_RESET,   /* Core reset event          */

   120     OPENPIC_OUTPUT_NB,

   121 };

   122 qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,

   123                         qemu_irq **irqs, qemu_irq irq_out);

   124 

   125 #endif /* !defined(__PPC_MAC_H__) */