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1 /* |
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2 * vm86 linux syscall support |
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3 * |
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4 * Copyright (c) 2003 Fabrice Bellard |
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5 * |
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6 * This program is free software; you can redistribute it and/or modify |
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7 * it under the terms of the GNU General Public License as published by |
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8 * the Free Software Foundation; either version 2 of the License, or |
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9 * (at your option) any later version. |
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10 * |
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11 * This program is distributed in the hope that it will be useful, |
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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14 * GNU General Public License for more details. |
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15 * |
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16 * You should have received a copy of the GNU General Public License |
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17 * along with this program; if not, write to the Free Software |
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18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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19 */ |
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20 #include <stdlib.h> |
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21 #include <stdio.h> |
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22 #include <stdarg.h> |
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23 #include <string.h> |
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24 #include <errno.h> |
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25 #include <unistd.h> |
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26 |
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27 #include "qemu.h" |
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28 |
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29 //#define DEBUG_VM86 |
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30 |
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31 #define set_flags(X,new,mask) \ |
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32 ((X) = ((X) & ~(mask)) | ((new) & (mask))) |
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33 |
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34 #define SAFE_MASK (0xDD5) |
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35 #define RETURN_MASK (0xDFF) |
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36 |
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37 static inline int is_revectored(int nr, struct target_revectored_struct *bitmap) |
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38 { |
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39 return (((uint8_t *)bitmap)[nr >> 3] >> (nr & 7)) & 1; |
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40 } |
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41 |
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42 static inline void vm_putw(uint32_t segptr, unsigned int reg16, unsigned int val) |
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43 { |
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44 stw(segptr + (reg16 & 0xffff), val); |
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45 } |
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46 |
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47 static inline void vm_putl(uint32_t segptr, unsigned int reg16, unsigned int val) |
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48 { |
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49 stl(segptr + (reg16 & 0xffff), val); |
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50 } |
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51 |
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52 static inline unsigned int vm_getb(uint32_t segptr, unsigned int reg16) |
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53 { |
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54 return ldub(segptr + (reg16 & 0xffff)); |
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55 } |
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56 |
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57 static inline unsigned int vm_getw(uint32_t segptr, unsigned int reg16) |
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58 { |
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59 return lduw(segptr + (reg16 & 0xffff)); |
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60 } |
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61 |
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62 static inline unsigned int vm_getl(uint32_t segptr, unsigned int reg16) |
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63 { |
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64 return ldl(segptr + (reg16 & 0xffff)); |
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65 } |
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66 |
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67 void save_v86_state(CPUX86State *env) |
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68 { |
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69 TaskState *ts = env->opaque; |
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70 struct target_vm86plus_struct * target_v86; |
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71 |
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72 if (!lock_user_struct(VERIFY_WRITE, target_v86, ts->target_v86, 0)) |
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73 /* FIXME - should return an error */ |
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74 return; |
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75 /* put the VM86 registers in the userspace register structure */ |
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76 target_v86->regs.eax = tswap32(env->regs[R_EAX]); |
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77 target_v86->regs.ebx = tswap32(env->regs[R_EBX]); |
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78 target_v86->regs.ecx = tswap32(env->regs[R_ECX]); |
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79 target_v86->regs.edx = tswap32(env->regs[R_EDX]); |
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80 target_v86->regs.esi = tswap32(env->regs[R_ESI]); |
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81 target_v86->regs.edi = tswap32(env->regs[R_EDI]); |
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82 target_v86->regs.ebp = tswap32(env->regs[R_EBP]); |
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83 target_v86->regs.esp = tswap32(env->regs[R_ESP]); |
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84 target_v86->regs.eip = tswap32(env->eip); |
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85 target_v86->regs.cs = tswap16(env->segs[R_CS].selector); |
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86 target_v86->regs.ss = tswap16(env->segs[R_SS].selector); |
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87 target_v86->regs.ds = tswap16(env->segs[R_DS].selector); |
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88 target_v86->regs.es = tswap16(env->segs[R_ES].selector); |
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89 target_v86->regs.fs = tswap16(env->segs[R_FS].selector); |
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90 target_v86->regs.gs = tswap16(env->segs[R_GS].selector); |
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91 set_flags(env->eflags, ts->v86flags, VIF_MASK | ts->v86mask); |
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92 target_v86->regs.eflags = tswap32(env->eflags); |
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93 unlock_user_struct(target_v86, ts->target_v86, 1); |
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94 #ifdef DEBUG_VM86 |
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95 fprintf(logfile, "save_v86_state: eflags=%08x cs:ip=%04x:%04x\n", |
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96 env->eflags, env->segs[R_CS].selector, env->eip); |
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97 #endif |
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98 |
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99 /* restore 32 bit registers */ |
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100 env->regs[R_EAX] = ts->vm86_saved_regs.eax; |
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101 env->regs[R_EBX] = ts->vm86_saved_regs.ebx; |
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102 env->regs[R_ECX] = ts->vm86_saved_regs.ecx; |
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103 env->regs[R_EDX] = ts->vm86_saved_regs.edx; |
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104 env->regs[R_ESI] = ts->vm86_saved_regs.esi; |
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105 env->regs[R_EDI] = ts->vm86_saved_regs.edi; |
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106 env->regs[R_EBP] = ts->vm86_saved_regs.ebp; |
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107 env->regs[R_ESP] = ts->vm86_saved_regs.esp; |
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108 env->eflags = ts->vm86_saved_regs.eflags; |
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109 env->eip = ts->vm86_saved_regs.eip; |
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110 |
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111 cpu_x86_load_seg(env, R_CS, ts->vm86_saved_regs.cs); |
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112 cpu_x86_load_seg(env, R_SS, ts->vm86_saved_regs.ss); |
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113 cpu_x86_load_seg(env, R_DS, ts->vm86_saved_regs.ds); |
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114 cpu_x86_load_seg(env, R_ES, ts->vm86_saved_regs.es); |
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115 cpu_x86_load_seg(env, R_FS, ts->vm86_saved_regs.fs); |
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116 cpu_x86_load_seg(env, R_GS, ts->vm86_saved_regs.gs); |
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117 } |
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118 |
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119 /* return from vm86 mode to 32 bit. The vm86() syscall will return |
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120 'retval' */ |
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121 static inline void return_to_32bit(CPUX86State *env, int retval) |
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122 { |
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123 #ifdef DEBUG_VM86 |
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124 fprintf(logfile, "return_to_32bit: ret=0x%x\n", retval); |
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125 #endif |
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126 save_v86_state(env); |
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127 env->regs[R_EAX] = retval; |
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128 } |
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129 |
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130 static inline int set_IF(CPUX86State *env) |
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131 { |
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132 TaskState *ts = env->opaque; |
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133 |
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134 ts->v86flags |= VIF_MASK; |
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135 if (ts->v86flags & VIP_MASK) { |
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136 return_to_32bit(env, TARGET_VM86_STI); |
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137 return 1; |
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138 } |
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139 return 0; |
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140 } |
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141 |
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142 static inline void clear_IF(CPUX86State *env) |
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143 { |
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144 TaskState *ts = env->opaque; |
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145 |
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146 ts->v86flags &= ~VIF_MASK; |
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147 } |
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148 |
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149 static inline void clear_TF(CPUX86State *env) |
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150 { |
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151 env->eflags &= ~TF_MASK; |
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152 } |
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153 |
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154 static inline void clear_AC(CPUX86State *env) |
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155 { |
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156 env->eflags &= ~AC_MASK; |
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157 } |
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158 |
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159 static inline int set_vflags_long(unsigned long eflags, CPUX86State *env) |
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160 { |
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161 TaskState *ts = env->opaque; |
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162 |
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163 set_flags(ts->v86flags, eflags, ts->v86mask); |
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164 set_flags(env->eflags, eflags, SAFE_MASK); |
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165 if (eflags & IF_MASK) |
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166 return set_IF(env); |
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167 else |
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168 clear_IF(env); |
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169 return 0; |
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170 } |
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171 |
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172 static inline int set_vflags_short(unsigned short flags, CPUX86State *env) |
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173 { |
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174 TaskState *ts = env->opaque; |
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175 |
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176 set_flags(ts->v86flags, flags, ts->v86mask & 0xffff); |
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177 set_flags(env->eflags, flags, SAFE_MASK); |
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178 if (flags & IF_MASK) |
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179 return set_IF(env); |
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180 else |
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181 clear_IF(env); |
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182 return 0; |
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183 } |
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184 |
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185 static inline unsigned int get_vflags(CPUX86State *env) |
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186 { |
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187 TaskState *ts = env->opaque; |
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188 unsigned int flags; |
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189 |
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190 flags = env->eflags & RETURN_MASK; |
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191 if (ts->v86flags & VIF_MASK) |
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192 flags |= IF_MASK; |
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193 flags |= IOPL_MASK; |
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194 return flags | (ts->v86flags & ts->v86mask); |
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195 } |
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196 |
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197 #define ADD16(reg, val) reg = (reg & ~0xffff) | ((reg + (val)) & 0xffff) |
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198 |
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199 /* handle VM86 interrupt (NOTE: the CPU core currently does not |
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200 support TSS interrupt revectoring, so this code is always executed) */ |
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201 static void do_int(CPUX86State *env, int intno) |
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202 { |
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203 TaskState *ts = env->opaque; |
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204 uint32_t int_addr, segoffs, ssp; |
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205 unsigned int sp; |
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206 |
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207 if (env->segs[R_CS].selector == TARGET_BIOSSEG) |
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208 goto cannot_handle; |
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209 if (is_revectored(intno, &ts->vm86plus.int_revectored)) |
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210 goto cannot_handle; |
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211 if (intno == 0x21 && is_revectored((env->regs[R_EAX] >> 8) & 0xff, |
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212 &ts->vm86plus.int21_revectored)) |
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213 goto cannot_handle; |
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214 int_addr = (intno << 2); |
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215 segoffs = ldl(int_addr); |
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216 if ((segoffs >> 16) == TARGET_BIOSSEG) |
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217 goto cannot_handle; |
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218 #if defined(DEBUG_VM86) |
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219 fprintf(logfile, "VM86: emulating int 0x%x. CS:IP=%04x:%04x\n", |
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220 intno, segoffs >> 16, segoffs & 0xffff); |
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221 #endif |
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222 /* save old state */ |
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223 ssp = env->segs[R_SS].selector << 4; |
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224 sp = env->regs[R_ESP] & 0xffff; |
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225 vm_putw(ssp, sp - 2, get_vflags(env)); |
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226 vm_putw(ssp, sp - 4, env->segs[R_CS].selector); |
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227 vm_putw(ssp, sp - 6, env->eip); |
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228 ADD16(env->regs[R_ESP], -6); |
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229 /* goto interrupt handler */ |
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230 env->eip = segoffs & 0xffff; |
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231 cpu_x86_load_seg(env, R_CS, segoffs >> 16); |
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232 clear_TF(env); |
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233 clear_IF(env); |
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234 clear_AC(env); |
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235 return; |
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236 cannot_handle: |
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237 #if defined(DEBUG_VM86) |
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238 fprintf(logfile, "VM86: return to 32 bits int 0x%x\n", intno); |
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239 #endif |
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240 return_to_32bit(env, TARGET_VM86_INTx | (intno << 8)); |
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241 } |
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242 |
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243 void handle_vm86_trap(CPUX86State *env, int trapno) |
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244 { |
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245 if (trapno == 1 || trapno == 3) { |
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246 return_to_32bit(env, TARGET_VM86_TRAP + (trapno << 8)); |
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247 } else { |
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248 do_int(env, trapno); |
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249 } |
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250 } |
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251 |
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252 #define CHECK_IF_IN_TRAP() \ |
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253 if ((ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_active) && \ |
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254 (ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_TFpendig)) \ |
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255 newflags |= TF_MASK |
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256 |
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257 #define VM86_FAULT_RETURN \ |
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258 if ((ts->vm86plus.vm86plus.flags & TARGET_force_return_for_pic) && \ |
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259 (ts->v86flags & (IF_MASK | VIF_MASK))) \ |
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260 return_to_32bit(env, TARGET_VM86_PICRETURN); \ |
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261 return |
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262 |
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263 void handle_vm86_fault(CPUX86State *env) |
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264 { |
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265 TaskState *ts = env->opaque; |
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266 uint32_t csp, ssp; |
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267 unsigned int ip, sp, newflags, newip, newcs, opcode, intno; |
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268 int data32, pref_done; |
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269 |
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270 csp = env->segs[R_CS].selector << 4; |
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271 ip = env->eip & 0xffff; |
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272 |
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273 ssp = env->segs[R_SS].selector << 4; |
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274 sp = env->regs[R_ESP] & 0xffff; |
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275 |
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276 #if defined(DEBUG_VM86) |
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277 fprintf(logfile, "VM86 exception %04x:%08x\n", |
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278 env->segs[R_CS].selector, env->eip); |
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279 #endif |
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280 |
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281 data32 = 0; |
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282 pref_done = 0; |
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283 do { |
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284 opcode = vm_getb(csp, ip); |
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285 ADD16(ip, 1); |
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286 switch (opcode) { |
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287 case 0x66: /* 32-bit data */ data32=1; break; |
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288 case 0x67: /* 32-bit address */ break; |
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289 case 0x2e: /* CS */ break; |
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290 case 0x3e: /* DS */ break; |
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291 case 0x26: /* ES */ break; |
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292 case 0x36: /* SS */ break; |
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293 case 0x65: /* GS */ break; |
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294 case 0x64: /* FS */ break; |
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295 case 0xf2: /* repnz */ break; |
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296 case 0xf3: /* rep */ break; |
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297 default: pref_done = 1; |
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298 } |
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299 } while (!pref_done); |
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300 |
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301 /* VM86 mode */ |
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302 switch(opcode) { |
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303 case 0x9c: /* pushf */ |
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304 if (data32) { |
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305 vm_putl(ssp, sp - 4, get_vflags(env)); |
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306 ADD16(env->regs[R_ESP], -4); |
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307 } else { |
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308 vm_putw(ssp, sp - 2, get_vflags(env)); |
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309 ADD16(env->regs[R_ESP], -2); |
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310 } |
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311 env->eip = ip; |
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312 VM86_FAULT_RETURN; |
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313 |
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314 case 0x9d: /* popf */ |
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315 if (data32) { |
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316 newflags = vm_getl(ssp, sp); |
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317 ADD16(env->regs[R_ESP], 4); |
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318 } else { |
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319 newflags = vm_getw(ssp, sp); |
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320 ADD16(env->regs[R_ESP], 2); |
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321 } |
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322 env->eip = ip; |
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323 CHECK_IF_IN_TRAP(); |
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324 if (data32) { |
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325 if (set_vflags_long(newflags, env)) |
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326 return; |
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327 } else { |
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328 if (set_vflags_short(newflags, env)) |
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329 return; |
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330 } |
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331 VM86_FAULT_RETURN; |
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332 |
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333 case 0xcd: /* int */ |
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334 intno = vm_getb(csp, ip); |
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335 ADD16(ip, 1); |
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336 env->eip = ip; |
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337 if (ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_active) { |
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338 if ( (ts->vm86plus.vm86plus.vm86dbg_intxxtab[intno >> 3] >> |
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339 (intno &7)) & 1) { |
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340 return_to_32bit(env, TARGET_VM86_INTx + (intno << 8)); |
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341 return; |
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342 } |
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343 } |
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344 do_int(env, intno); |
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345 break; |
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346 |
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347 case 0xcf: /* iret */ |
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348 if (data32) { |
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349 newip = vm_getl(ssp, sp) & 0xffff; |
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350 newcs = vm_getl(ssp, sp + 4) & 0xffff; |
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351 newflags = vm_getl(ssp, sp + 8); |
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352 ADD16(env->regs[R_ESP], 12); |
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353 } else { |
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354 newip = vm_getw(ssp, sp); |
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355 newcs = vm_getw(ssp, sp + 2); |
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356 newflags = vm_getw(ssp, sp + 4); |
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357 ADD16(env->regs[R_ESP], 6); |
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358 } |
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359 env->eip = newip; |
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360 cpu_x86_load_seg(env, R_CS, newcs); |
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361 CHECK_IF_IN_TRAP(); |
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362 if (data32) { |
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363 if (set_vflags_long(newflags, env)) |
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364 return; |
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365 } else { |
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366 if (set_vflags_short(newflags, env)) |
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367 return; |
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368 } |
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369 VM86_FAULT_RETURN; |
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370 |
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371 case 0xfa: /* cli */ |
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372 env->eip = ip; |
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373 clear_IF(env); |
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374 VM86_FAULT_RETURN; |
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375 |
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376 case 0xfb: /* sti */ |
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377 env->eip = ip; |
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378 if (set_IF(env)) |
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379 return; |
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380 VM86_FAULT_RETURN; |
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381 |
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382 default: |
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383 /* real VM86 GPF exception */ |
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384 return_to_32bit(env, TARGET_VM86_UNKNOWN); |
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385 break; |
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386 } |
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387 } |
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388 |
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389 int do_vm86(CPUX86State *env, long subfunction, abi_ulong vm86_addr) |
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390 { |
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391 TaskState *ts = env->opaque; |
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392 struct target_vm86plus_struct * target_v86; |
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393 int ret; |
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394 |
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395 switch (subfunction) { |
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396 case TARGET_VM86_REQUEST_IRQ: |
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397 case TARGET_VM86_FREE_IRQ: |
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398 case TARGET_VM86_GET_IRQ_BITS: |
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399 case TARGET_VM86_GET_AND_RESET_IRQ: |
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400 gemu_log("qemu: unsupported vm86 subfunction (%ld)\n", subfunction); |
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401 ret = -TARGET_EINVAL; |
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402 goto out; |
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403 case TARGET_VM86_PLUS_INSTALL_CHECK: |
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404 /* NOTE: on old vm86 stuff this will return the error |
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405 from verify_area(), because the subfunction is |
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406 interpreted as (invalid) address to vm86_struct. |
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407 So the installation check works. |
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408 */ |
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409 ret = 0; |
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410 goto out; |
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411 } |
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412 |
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413 /* save current CPU regs */ |
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414 ts->vm86_saved_regs.eax = 0; /* default vm86 syscall return code */ |
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415 ts->vm86_saved_regs.ebx = env->regs[R_EBX]; |
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416 ts->vm86_saved_regs.ecx = env->regs[R_ECX]; |
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417 ts->vm86_saved_regs.edx = env->regs[R_EDX]; |
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418 ts->vm86_saved_regs.esi = env->regs[R_ESI]; |
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419 ts->vm86_saved_regs.edi = env->regs[R_EDI]; |
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420 ts->vm86_saved_regs.ebp = env->regs[R_EBP]; |
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421 ts->vm86_saved_regs.esp = env->regs[R_ESP]; |
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422 ts->vm86_saved_regs.eflags = env->eflags; |
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423 ts->vm86_saved_regs.eip = env->eip; |
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424 ts->vm86_saved_regs.cs = env->segs[R_CS].selector; |
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425 ts->vm86_saved_regs.ss = env->segs[R_SS].selector; |
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426 ts->vm86_saved_regs.ds = env->segs[R_DS].selector; |
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427 ts->vm86_saved_regs.es = env->segs[R_ES].selector; |
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428 ts->vm86_saved_regs.fs = env->segs[R_FS].selector; |
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429 ts->vm86_saved_regs.gs = env->segs[R_GS].selector; |
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430 |
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431 ts->target_v86 = vm86_addr; |
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432 if (!lock_user_struct(VERIFY_READ, target_v86, vm86_addr, 1)) |
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433 return -TARGET_EFAULT; |
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434 /* build vm86 CPU state */ |
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435 ts->v86flags = tswap32(target_v86->regs.eflags); |
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436 env->eflags = (env->eflags & ~SAFE_MASK) | |
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437 (tswap32(target_v86->regs.eflags) & SAFE_MASK) | VM_MASK; |
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438 |
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439 ts->vm86plus.cpu_type = tswapl(target_v86->cpu_type); |
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440 switch (ts->vm86plus.cpu_type) { |
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441 case TARGET_CPU_286: |
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442 ts->v86mask = 0; |
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443 break; |
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444 case TARGET_CPU_386: |
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445 ts->v86mask = NT_MASK | IOPL_MASK; |
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446 break; |
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447 case TARGET_CPU_486: |
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448 ts->v86mask = AC_MASK | NT_MASK | IOPL_MASK; |
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449 break; |
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450 default: |
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451 ts->v86mask = ID_MASK | AC_MASK | NT_MASK | IOPL_MASK; |
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452 break; |
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453 } |
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454 |
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455 env->regs[R_EBX] = tswap32(target_v86->regs.ebx); |
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456 env->regs[R_ECX] = tswap32(target_v86->regs.ecx); |
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457 env->regs[R_EDX] = tswap32(target_v86->regs.edx); |
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458 env->regs[R_ESI] = tswap32(target_v86->regs.esi); |
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459 env->regs[R_EDI] = tswap32(target_v86->regs.edi); |
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460 env->regs[R_EBP] = tswap32(target_v86->regs.ebp); |
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461 env->regs[R_ESP] = tswap32(target_v86->regs.esp); |
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462 env->eip = tswap32(target_v86->regs.eip); |
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463 cpu_x86_load_seg(env, R_CS, tswap16(target_v86->regs.cs)); |
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464 cpu_x86_load_seg(env, R_SS, tswap16(target_v86->regs.ss)); |
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465 cpu_x86_load_seg(env, R_DS, tswap16(target_v86->regs.ds)); |
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466 cpu_x86_load_seg(env, R_ES, tswap16(target_v86->regs.es)); |
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467 cpu_x86_load_seg(env, R_FS, tswap16(target_v86->regs.fs)); |
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468 cpu_x86_load_seg(env, R_GS, tswap16(target_v86->regs.gs)); |
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469 ret = tswap32(target_v86->regs.eax); /* eax will be restored at |
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470 the end of the syscall */ |
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471 memcpy(&ts->vm86plus.int_revectored, |
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472 &target_v86->int_revectored, 32); |
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473 memcpy(&ts->vm86plus.int21_revectored, |
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474 &target_v86->int21_revectored, 32); |
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475 ts->vm86plus.vm86plus.flags = tswapl(target_v86->vm86plus.flags); |
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476 memcpy(&ts->vm86plus.vm86plus.vm86dbg_intxxtab, |
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477 target_v86->vm86plus.vm86dbg_intxxtab, 32); |
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478 unlock_user_struct(target_v86, vm86_addr, 0); |
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479 |
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480 #ifdef DEBUG_VM86 |
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481 fprintf(logfile, "do_vm86: cs:ip=%04x:%04x\n", |
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482 env->segs[R_CS].selector, env->eip); |
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483 #endif |
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484 /* now the virtual CPU is ready for vm86 execution ! */ |
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485 out: |
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486 return ret; |
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487 } |