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1 /* |
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2 * Atomic operation helper include |
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3 * |
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4 * Copyright (c) 2005 Fabrice Bellard |
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5 * |
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6 * This library is free software; you can redistribute it and/or |
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7 * modify it under the terms of the GNU Lesser General Public |
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8 * License as published by the Free Software Foundation; either |
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9 * version 2 of the License, or (at your option) any later version. |
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10 * |
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11 * This library is distributed in the hope that it will be useful, |
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 * Lesser General Public License for more details. |
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15 * |
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16 * You should have received a copy of the GNU Lesser General Public |
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17 * License along with this library; if not, write to the Free Software |
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18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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19 */ |
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20 #ifndef QEMU_SPINLOCK_H |
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21 #define QEMU_SPINLOCK_H |
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22 |
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23 #if defined(__hppa__) |
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24 |
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25 typedef int spinlock_t[4]; |
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26 |
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27 #define SPIN_LOCK_UNLOCKED { 1, 1, 1, 1 } |
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28 |
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29 static inline void resetlock (spinlock_t *p) |
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30 { |
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31 (*p)[0] = (*p)[1] = (*p)[2] = (*p)[3] = 1; |
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32 } |
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33 |
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34 #else |
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35 |
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36 typedef int spinlock_t; |
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37 |
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38 #define SPIN_LOCK_UNLOCKED 0 |
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39 |
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40 static inline void resetlock (spinlock_t *p) |
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41 { |
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42 *p = SPIN_LOCK_UNLOCKED; |
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43 } |
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44 |
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45 #endif |
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46 |
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47 #if defined(__powerpc__) |
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48 static inline int testandset (int *p) |
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49 { |
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50 int ret; |
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51 __asm__ __volatile__ ( |
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52 "0: lwarx %0,0,%1\n" |
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53 " xor. %0,%3,%0\n" |
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54 " bne 1f\n" |
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55 " stwcx. %2,0,%1\n" |
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56 " bne- 0b\n" |
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57 "1: " |
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58 : "=&r" (ret) |
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59 : "r" (p), "r" (1), "r" (0) |
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60 : "cr0", "memory"); |
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61 return ret; |
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62 } |
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63 #elif defined(__i386__) |
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64 static inline int testandset (int *p) |
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65 { |
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66 long int readval = 0; |
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67 |
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68 __asm__ __volatile__ ("lock; cmpxchgl %2, %0" |
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69 : "+m" (*p), "+a" (readval) |
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70 : "r" (1) |
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71 : "cc"); |
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72 return readval; |
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73 } |
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74 #elif defined(__x86_64__) |
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75 static inline int testandset (int *p) |
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76 { |
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77 long int readval = 0; |
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78 |
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79 __asm__ __volatile__ ("lock; cmpxchgl %2, %0" |
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80 : "+m" (*p), "+a" (readval) |
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81 : "r" (1) |
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82 : "cc"); |
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83 return readval; |
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84 } |
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85 #elif defined(__s390__) |
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86 static inline int testandset (int *p) |
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87 { |
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88 int ret; |
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89 |
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90 __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n" |
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91 " jl 0b" |
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92 : "=&d" (ret) |
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93 : "r" (1), "a" (p), "0" (*p) |
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94 : "cc", "memory" ); |
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95 return ret; |
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96 } |
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97 #elif defined(__alpha__) |
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98 static inline int testandset (int *p) |
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99 { |
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100 int ret; |
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101 unsigned long one; |
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102 |
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103 __asm__ __volatile__ ("0: mov 1,%2\n" |
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104 " ldl_l %0,%1\n" |
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105 " stl_c %2,%1\n" |
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106 " beq %2,1f\n" |
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107 ".subsection 2\n" |
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108 "1: br 0b\n" |
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109 ".previous" |
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110 : "=r" (ret), "=m" (*p), "=r" (one) |
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111 : "m" (*p)); |
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112 return ret; |
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113 } |
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114 #elif defined(__sparc__) |
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115 static inline int testandset (int *p) |
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116 { |
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117 int ret; |
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118 |
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119 __asm__ __volatile__("ldstub [%1], %0" |
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120 : "=r" (ret) |
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121 : "r" (p) |
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122 : "memory"); |
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123 |
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124 return (ret ? 1 : 0); |
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125 } |
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126 #elif defined(__arm__) |
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127 static inline int testandset (int *spinlock) |
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128 { |
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129 register unsigned int ret; |
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130 __asm__ __volatile__("swp %0, %1, [%2]" |
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131 : "=r"(ret) |
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132 : "0"(1), "r"(spinlock)); |
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133 |
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134 return ret; |
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135 } |
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136 #elif defined(__mc68000) |
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137 static inline int testandset (int *p) |
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138 { |
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139 char ret; |
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140 __asm__ __volatile__("tas %1; sne %0" |
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141 : "=r" (ret) |
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142 : "m" (p) |
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143 : "cc","memory"); |
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144 return ret; |
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145 } |
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146 #elif defined(__hppa__) |
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147 |
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148 /* Because malloc only guarantees 8-byte alignment for malloc'd data, |
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149 and GCC only guarantees 8-byte alignment for stack locals, we can't |
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150 be assured of 16-byte alignment for atomic lock data even if we |
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151 specify "__attribute ((aligned(16)))" in the type declaration. So, |
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152 we use a struct containing an array of four ints for the atomic lock |
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153 type and dynamically select the 16-byte aligned int from the array |
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154 for the semaphore. */ |
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155 #define __PA_LDCW_ALIGNMENT 16 |
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156 static inline void *ldcw_align (void *p) { |
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157 unsigned long a = (unsigned long)p; |
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158 a = (a + __PA_LDCW_ALIGNMENT - 1) & ~(__PA_LDCW_ALIGNMENT - 1); |
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159 return (void *)a; |
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160 } |
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161 |
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162 static inline int testandset (spinlock_t *p) |
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163 { |
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164 unsigned int ret; |
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165 p = ldcw_align(p); |
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166 __asm__ __volatile__("ldcw 0(%1),%0" |
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167 : "=r" (ret) |
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168 : "r" (p) |
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169 : "memory" ); |
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170 return !ret; |
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171 } |
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172 |
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173 #elif defined(__ia64) |
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174 |
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175 #include <ia64intrin.h> |
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176 |
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177 static inline int testandset (int *p) |
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178 { |
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179 return __sync_lock_test_and_set (p, 1); |
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180 } |
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181 #elif defined(__mips__) |
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182 static inline int testandset (int *p) |
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183 { |
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184 int ret; |
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185 |
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186 __asm__ __volatile__ ( |
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187 " .set push \n" |
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188 " .set noat \n" |
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189 " .set mips2 \n" |
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190 "1: li $1, 1 \n" |
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191 " ll %0, %1 \n" |
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192 " sc $1, %1 \n" |
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193 " beqz $1, 1b \n" |
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194 " .set pop " |
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195 : "=r" (ret), "+R" (*p) |
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196 : |
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197 : "memory"); |
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198 |
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199 return ret; |
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200 } |
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201 #else |
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202 #error unimplemented CPU support |
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203 #endif |
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204 |
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205 #if defined(CONFIG_USER_ONLY) |
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206 static inline void spin_lock(spinlock_t *lock) |
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207 { |
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208 while (testandset(lock)); |
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209 } |
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210 |
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211 static inline void spin_unlock(spinlock_t *lock) |
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212 { |
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213 resetlock(lock); |
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214 } |
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215 |
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216 static inline int spin_trylock(spinlock_t *lock) |
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217 { |
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218 return !testandset(lock); |
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219 } |
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220 #else |
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221 static inline void spin_lock(spinlock_t *lock) |
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222 { |
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223 } |
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224 |
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225 static inline void spin_unlock(spinlock_t *lock) |
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226 { |
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227 } |
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228 |
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229 static inline int spin_trylock(spinlock_t *lock) |
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230 { |
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231 return 1; |
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232 } |
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233 #endif |
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234 |
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235 #endif |