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1 /* |
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2 * These files from binutils are concatenated: |
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3 * include/opcode/sparc.h, opcodes/sparc-opc.c, opcodes/sparc-dis.c |
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4 */ |
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5 |
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6 /* include/opcode/sparc.h */ |
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7 |
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8 /* Definitions for opcode table for the sparc. |
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9 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002, |
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10 2003, 2005 Free Software Foundation, Inc. |
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11 |
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12 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and |
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13 the GNU Binutils. |
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14 |
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15 GAS/GDB is free software; you can redistribute it and/or modify |
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16 it under the terms of the GNU General Public License as published by |
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17 the Free Software Foundation; either version 2, or (at your option) |
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18 any later version. |
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19 |
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20 GAS/GDB is distributed in the hope that it will be useful, |
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21 but WITHOUT ANY WARRANTY; without even the implied warranty of |
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22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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23 GNU General Public License for more details. |
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24 |
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25 You should have received a copy of the GNU General Public License |
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26 along with GAS or GDB; see the file COPYING. If not, write to |
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27 the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
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28 Boston, MA 02110-1301, USA. */ |
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29 |
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30 #include <stdlib.h> |
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31 #include "dis-asm.h" |
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32 |
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33 /* The SPARC opcode table (and other related data) is defined in |
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34 the opcodes library in sparc-opc.c. If you change anything here, make |
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35 sure you fix up that file, and vice versa. */ |
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36 |
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37 /* FIXME-someday: perhaps the ,a's and such should be embedded in the |
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38 instruction's name rather than the args. This would make gas faster, pinsn |
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39 slower, but would mess up some macros a bit. xoxorich. */ |
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40 |
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41 /* List of instruction sets variations. |
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42 These values are such that each element is either a superset of a |
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43 preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P |
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44 returns non-zero. |
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45 The values are indices into `sparc_opcode_archs' defined in sparc-opc.c. |
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46 Don't change this without updating sparc-opc.c. */ |
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47 |
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48 enum sparc_opcode_arch_val |
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49 { |
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50 SPARC_OPCODE_ARCH_V6 = 0, |
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51 SPARC_OPCODE_ARCH_V7, |
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52 SPARC_OPCODE_ARCH_V8, |
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53 SPARC_OPCODE_ARCH_SPARCLET, |
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54 SPARC_OPCODE_ARCH_SPARCLITE, |
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55 /* V9 variants must appear last. */ |
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56 SPARC_OPCODE_ARCH_V9, |
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57 SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */ |
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58 SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */ |
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59 SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */ |
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60 }; |
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61 |
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62 /* The highest architecture in the table. */ |
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63 #define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1) |
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64 |
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65 /* Given an enum sparc_opcode_arch_val, return the bitmask to use in |
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66 insn encoding/decoding. */ |
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67 #define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch)) |
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68 |
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69 /* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */ |
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70 #define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9) |
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71 |
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72 /* Table of cpu variants. */ |
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73 |
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74 typedef struct sparc_opcode_arch |
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75 { |
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76 const char *name; |
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77 /* Mask of sparc_opcode_arch_val's supported. |
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78 EG: For v7 this would be |
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79 (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)). |
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80 These are short's because sparc_opcode.architecture is. */ |
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81 short supported; |
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82 } sparc_opcode_arch; |
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83 |
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84 static const struct sparc_opcode_arch sparc_opcode_archs[]; |
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85 |
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86 /* Return the bitmask of supported architectures for ARCH. */ |
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87 #define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported) |
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88 |
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89 /* Non-zero if ARCH1 conflicts with ARCH2. |
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90 IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */ |
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91 #define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \ |
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92 (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ |
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93 != SPARC_OPCODE_SUPPORTED (ARCH1)) \ |
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94 && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ |
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95 != SPARC_OPCODE_SUPPORTED (ARCH2))) |
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96 |
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97 /* Structure of an opcode table entry. */ |
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98 |
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99 typedef struct sparc_opcode |
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100 { |
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101 const char *name; |
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102 unsigned long match; /* Bits that must be set. */ |
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103 unsigned long lose; /* Bits that must not be set. */ |
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104 const char *args; |
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105 /* This was called "delayed" in versions before the flags. */ |
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106 char flags; |
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107 short architecture; /* Bitmask of sparc_opcode_arch_val's. */ |
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108 } sparc_opcode; |
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109 |
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110 #define F_DELAYED 1 /* Delayed branch. */ |
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111 #define F_ALIAS 2 /* Alias for a "real" instruction. */ |
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112 #define F_UNBR 4 /* Unconditional branch. */ |
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113 #define F_CONDBR 8 /* Conditional branch. */ |
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114 #define F_JSR 16 /* Subroutine call. */ |
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115 #define F_FLOAT 32 /* Floating point instruction (not a branch). */ |
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116 #define F_FBR 64 /* Floating point branch. */ |
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117 /* FIXME: Add F_ANACHRONISTIC flag for v9. */ |
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118 |
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119 /* All sparc opcodes are 32 bits, except for the `set' instruction (really a |
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120 macro), which is 64 bits. It is handled as a special case. |
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121 |
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122 The match component is a mask saying which bits must match a particular |
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123 opcode in order for an instruction to be an instance of that opcode. |
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124 |
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125 The args component is a string containing one character for each operand of the |
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126 instruction. |
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127 |
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128 Kinds of operands: |
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129 # Number used by optimizer. It is ignored. |
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130 1 rs1 register. |
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131 2 rs2 register. |
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132 d rd register. |
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133 e frs1 floating point register. |
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134 v frs1 floating point register (double/even). |
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135 V frs1 floating point register (quad/multiple of 4). |
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136 f frs2 floating point register. |
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137 B frs2 floating point register (double/even). |
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138 R frs2 floating point register (quad/multiple of 4). |
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139 g frsd floating point register. |
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140 H frsd floating point register (double/even). |
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141 J frsd floating point register (quad/multiple of 4). |
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142 b crs1 coprocessor register |
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143 c crs2 coprocessor register |
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144 D crsd coprocessor register |
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145 m alternate space register (asr) in rd |
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146 M alternate space register (asr) in rs1 |
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147 h 22 high bits. |
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148 X 5 bit unsigned immediate |
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149 Y 6 bit unsigned immediate |
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150 3 SIAM mode (3 bits). (v9b) |
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151 K MEMBAR mask (7 bits). (v9) |
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152 j 10 bit Immediate. (v9) |
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153 I 11 bit Immediate. (v9) |
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154 i 13 bit Immediate. |
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155 n 22 bit immediate. |
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156 k 2+14 bit PC relative immediate. (v9) |
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157 G 19 bit PC relative immediate. (v9) |
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158 l 22 bit PC relative immediate. |
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159 L 30 bit PC relative immediate. |
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160 a Annul. The annul bit is set. |
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161 A Alternate address space. Stored as 8 bits. |
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162 C Coprocessor state register. |
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163 F floating point state register. |
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164 p Processor state register. |
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165 N Branch predict clear ",pn" (v9) |
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166 T Branch predict set ",pt" (v9) |
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167 z %icc. (v9) |
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168 Z %xcc. (v9) |
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169 q Floating point queue. |
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170 r Single register that is both rs1 and rd. |
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171 O Single register that is both rs2 and rd. |
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172 Q Coprocessor queue. |
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173 S Special case. |
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174 t Trap base register. |
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175 w Window invalid mask register. |
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176 y Y register. |
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177 u sparclet coprocessor registers in rd position |
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178 U sparclet coprocessor registers in rs1 position |
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179 E %ccr. (v9) |
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180 s %fprs. (v9) |
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181 P %pc. (v9) |
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182 W %tick. (v9) |
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183 o %asi. (v9) |
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184 6 %fcc0. (v9) |
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185 7 %fcc1. (v9) |
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186 8 %fcc2. (v9) |
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187 9 %fcc3. (v9) |
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188 ! Privileged Register in rd (v9) |
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189 ? Privileged Register in rs1 (v9) |
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190 * Prefetch function constant. (v9) |
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191 x OPF field (v9 impdep). |
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192 0 32/64 bit immediate for set or setx (v9) insns |
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193 _ Ancillary state register in rd (v9a) |
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194 / Ancillary state register in rs1 (v9a) |
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195 |
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196 The following chars are unused: (note: ,[] are used as punctuation) |
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197 [45]. */ |
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198 |
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199 #define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */ |
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200 #define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */ |
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201 #define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */ |
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202 #define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */ |
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203 #define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */ |
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204 #define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */ |
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205 #define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */ |
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206 #define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */ |
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207 #define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */ |
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208 #define F1(x) (OP (x)) |
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209 #define DISP30(x) ((x) & 0x3fffffff) |
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210 #define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */ |
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211 #define RS2(x) ((x) & 0x1f) /* Rs2 field. */ |
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212 #define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */ |
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213 #define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */ |
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214 #define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */ |
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215 #define ASI_RS2(x) (SIMM13 (x)) |
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216 #define MEMBAR(x) ((x) & 0x7f) |
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217 #define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */ |
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218 |
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219 #define ANNUL (1 << 29) |
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220 #define BPRED (1 << 19) /* V9. */ |
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221 #define IMMED F3I (1) |
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222 #define RD_G0 RD (~0) |
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223 #define RS1_G0 RS1 (~0) |
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224 #define RS2_G0 RS2 (~0) |
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225 |
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226 static const struct sparc_opcode sparc_opcodes[]; |
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227 static const int sparc_num_opcodes; |
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228 |
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229 static const char *sparc_decode_asi_v8 (int); |
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230 static const char *sparc_decode_asi_v9 (int); |
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231 static const char *sparc_decode_membar (int); |
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232 static const char *sparc_decode_prefetch (int); |
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233 static const char *sparc_decode_sparclet_cpreg (int); |
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234 |
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235 /* Local Variables: |
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236 fill-column: 131 |
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237 comment-column: 0 |
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238 End: */ |
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239 |
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240 /* opcodes/sparc-opc.c */ |
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241 |
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242 /* Table of opcodes for the sparc. |
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243 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
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244 2000, 2002, 2004, 2005 |
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245 Free Software Foundation, Inc. |
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246 |
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247 This file is part of the BFD library. |
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248 |
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249 BFD is free software; you can redistribute it and/or modify it under |
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250 the terms of the GNU General Public License as published by the Free |
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251 Software Foundation; either version 2, or (at your option) any later |
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252 version. |
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253 |
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254 BFD is distributed in the hope that it will be useful, but WITHOUT ANY |
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255 WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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256 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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257 for more details. |
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258 |
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259 You should have received a copy of the GNU General Public License |
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260 along with this software; see the file COPYING. If not, write to |
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261 the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
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262 Boston, MA 02110-1301, USA. */ |
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263 |
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264 /* FIXME-someday: perhaps the ,a's and such should be embedded in the |
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265 instruction's name rather than the args. This would make gas faster, pinsn |
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266 slower, but would mess up some macros a bit. xoxorich. */ |
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267 |
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268 /* Some defines to make life easy. */ |
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269 #define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6) |
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270 #define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7) |
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271 #define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8) |
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272 #define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET) |
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273 #define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) |
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274 #define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) |
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275 #define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A) |
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276 #define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B) |
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277 |
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278 /* Bit masks of architectures supporting the insn. */ |
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279 |
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280 #define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \ |
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281 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) |
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282 /* v6 insns not supported on the sparclet. */ |
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283 #define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \ |
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284 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) |
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285 #define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \ |
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286 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B) |
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287 /* Although not all insns are implemented in hardware, sparclite is defined |
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288 to be a superset of v8. Unimplemented insns trap and are then theoretically |
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289 implemented in software. |
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290 It's not clear that the same is true for sparclet, although the docs |
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291 suggest it is. Rather than complicating things, the sparclet assembler |
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292 recognizes all v8 insns. */ |
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293 #define v8 (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \ |
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294 | MASK_V9 | MASK_V9A | MASK_V9B) |
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295 #define sparclet (MASK_SPARCLET) |
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296 #define sparclite (MASK_SPARCLITE) |
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297 #define v9 (MASK_V9 | MASK_V9A | MASK_V9B) |
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298 #define v9a (MASK_V9A | MASK_V9B) |
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299 #define v9b (MASK_V9B) |
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300 /* v6 insns not supported by v9. */ |
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301 #define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \ |
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302 | MASK_SPARCLET | MASK_SPARCLITE) |
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303 /* v9a instructions which would appear to be aliases to v9's impdep's |
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304 otherwise. */ |
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305 #define v9notv9a (MASK_V9) |
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306 |
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307 /* Table of opcode architectures. |
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308 The order is defined in opcode/sparc.h. */ |
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309 |
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310 static const struct sparc_opcode_arch sparc_opcode_archs[] = |
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311 { |
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312 { "v6", MASK_V6 }, |
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313 { "v7", MASK_V6 | MASK_V7 }, |
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314 { "v8", MASK_V6 | MASK_V7 | MASK_V8 }, |
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315 { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET }, |
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316 { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE }, |
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317 /* ??? Don't some v8 privileged insns conflict with v9? */ |
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318 { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 }, |
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319 /* v9 with ultrasparc additions */ |
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320 { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A }, |
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321 /* v9 with cheetah additions */ |
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322 { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B }, |
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323 { NULL, 0 } |
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324 }; |
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325 |
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326 /* Branch condition field. */ |
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327 #define COND(x) (((x) & 0xf) << 25) |
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328 |
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329 /* v9: Move (MOVcc and FMOVcc) condition field. */ |
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330 #define MCOND(x,i_or_f) ((((i_or_f) & 1) << 18) | (((x) >> 11) & (0xf << 14))) /* v9 */ |
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331 |
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332 /* v9: Move register (MOVRcc and FMOVRcc) condition field. */ |
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333 #define RCOND(x) (((x) & 0x7) << 10) /* v9 */ |
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334 |
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335 #define CONDA (COND (0x8)) |
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336 #define CONDCC (COND (0xd)) |
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337 #define CONDCS (COND (0x5)) |
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338 #define CONDE (COND (0x1)) |
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339 #define CONDG (COND (0xa)) |
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340 #define CONDGE (COND (0xb)) |
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341 #define CONDGU (COND (0xc)) |
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342 #define CONDL (COND (0x3)) |
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343 #define CONDLE (COND (0x2)) |
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344 #define CONDLEU (COND (0x4)) |
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345 #define CONDN (COND (0x0)) |
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346 #define CONDNE (COND (0x9)) |
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347 #define CONDNEG (COND (0x6)) |
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348 #define CONDPOS (COND (0xe)) |
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349 #define CONDVC (COND (0xf)) |
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350 #define CONDVS (COND (0x7)) |
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351 |
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352 #define CONDNZ CONDNE |
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353 #define CONDZ CONDE |
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354 #define CONDGEU CONDCC |
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355 #define CONDLU CONDCS |
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356 |
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357 #define FCONDA (COND (0x8)) |
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358 #define FCONDE (COND (0x9)) |
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359 #define FCONDG (COND (0x6)) |
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360 #define FCONDGE (COND (0xb)) |
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361 #define FCONDL (COND (0x4)) |
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362 #define FCONDLE (COND (0xd)) |
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363 #define FCONDLG (COND (0x2)) |
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364 #define FCONDN (COND (0x0)) |
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365 #define FCONDNE (COND (0x1)) |
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366 #define FCONDO (COND (0xf)) |
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367 #define FCONDU (COND (0x7)) |
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368 #define FCONDUE (COND (0xa)) |
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369 #define FCONDUG (COND (0x5)) |
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370 #define FCONDUGE (COND (0xc)) |
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371 #define FCONDUL (COND (0x3)) |
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372 #define FCONDULE (COND (0xe)) |
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373 |
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374 #define FCONDNZ FCONDNE |
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375 #define FCONDZ FCONDE |
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376 |
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377 #define ICC (0) /* v9 */ |
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378 #define XCC (1 << 12) /* v9 */ |
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379 #define FCC(x) (((x) & 0x3) << 11) /* v9 */ |
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380 #define FBFCC(x) (((x) & 0x3) << 20) /* v9 */ |
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381 |
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382 /* The order of the opcodes in the table is significant: |
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383 |
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384 * The assembler requires that all instances of the same mnemonic must |
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385 be consecutive. If they aren't, the assembler will bomb at runtime. |
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386 |
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387 * The disassembler should not care about the order of the opcodes. */ |
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388 |
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389 /* Entries for commutative arithmetic operations. */ |
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390 /* ??? More entries can make use of this. */ |
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391 #define COMMUTEOP(opcode, op3, arch_mask) \ |
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392 { opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, arch_mask }, \ |
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393 { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, arch_mask }, \ |
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394 { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, arch_mask } |
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395 |
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396 static const struct sparc_opcode sparc_opcodes[] = { |
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397 |
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398 { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, v6 }, |
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399 { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, v6 }, /* ld [rs1+%g0],d */ |
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400 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, v6 }, |
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401 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, v6 }, |
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402 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", 0, v6 }, |
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403 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ld [rs1+0],d */ |
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404 { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, v6 }, |
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405 { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, v6 }, /* ld [rs1+%g0],d */ |
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406 { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0, v6 }, |
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407 { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", 0, v6 }, |
|
408 { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g", 0, v6 }, |
|
409 { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, v6 }, /* ld [rs1+0],d */ |
|
410 |
|
411 { "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0, v6 }, |
|
412 { "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+%g0],d */ |
|
413 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0, v6 }, |
|
414 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0, v6 }, |
|
415 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, v6 }, |
|
416 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+0],d */ |
|
417 |
|
418 { "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", 0, v6notv9 }, |
|
419 { "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", 0, v6notv9 }, /* ld [rs1+%g0],d */ |
|
420 { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", 0, v6notv9 }, |
|
421 { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", 0, v6notv9 }, |
|
422 { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D", 0, v6notv9 }, |
|
423 { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ld [rs1+0],d */ |
|
424 { "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", 0, v6notv9 }, |
|
425 { "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", 0, v6notv9 }, /* ld [rs1+%g0],d */ |
|
426 { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", 0, v6notv9 }, |
|
427 { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", 0, v6notv9 }, |
|
428 { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C", 0, v6notv9 }, |
|
429 { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0, v6notv9 }, /* ld [rs1+0],d */ |
|
430 |
|
431 /* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the |
|
432 'ld' pseudo-op in v9. */ |
|
433 { "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", F_ALIAS, v9 }, |
|
434 { "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", F_ALIAS, v9 }, /* ld [rs1+%g0],d */ |
|
435 { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", F_ALIAS, v9 }, |
|
436 { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", F_ALIAS, v9 }, |
|
437 { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", F_ALIAS, v9 }, |
|
438 { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS, v9 }, /* ld [rs1+0],d */ |
|
439 |
|
440 { "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, v6 }, |
|
441 { "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldd [rs1+%g0],d */ |
|
442 { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", 0, v6 }, |
|
443 { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", 0, v6 }, |
|
444 { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", 0, v6 }, |
|
445 { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldd [rs1+0],d */ |
|
446 { "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", 0, v6 }, |
|
447 { "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],H", 0, v6 }, /* ldd [rs1+%g0],d */ |
|
448 { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],H", 0, v6 }, |
|
449 { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],H", 0, v6 }, |
|
450 { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0, "[i],H", 0, v6 }, |
|
451 { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H", 0, v6 }, /* ldd [rs1+0],d */ |
|
452 |
|
453 { "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, v6notv9 }, |
|
454 { "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+%g0],d */ |
|
455 { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D", 0, v6notv9 }, |
|
456 { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D", 0, v6notv9 }, |
|
457 { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i],D", 0, v6notv9 }, |
|
458 { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+0],d */ |
|
459 |
|
460 { "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0, v9 }, |
|
461 { "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0), "[1],J", 0, v9 }, /* ldd [rs1+%g0],d */ |
|
462 { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[1+i],J", 0, v9 }, |
|
463 { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[i+1],J", 0, v9 }, |
|
464 { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0, "[i],J", 0, v9 }, |
|
465 { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J", 0, v9 }, /* ldd [rs1+0],d */ |
|
466 |
|
467 { "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, v6 }, |
|
468 { "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsb [rs1+%g0],d */ |
|
469 { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d", 0, v6 }, |
|
470 { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d", 0, v6 }, |
|
471 { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0, "[i],d", 0, v6 }, |
|
472 { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsb [rs1+0],d */ |
|
473 |
|
474 { "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsh [rs1+%g0],d */ |
|
475 { "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, v6 }, |
|
476 { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d", 0, v6 }, |
|
477 { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d", 0, v6 }, |
|
478 { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0, "[i],d", 0, v6 }, |
|
479 { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsh [rs1+0],d */ |
|
480 |
|
481 { "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, v6 }, |
|
482 { "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldstub [rs1+%g0],d */ |
|
483 { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d", 0, v6 }, |
|
484 { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d", 0, v6 }, |
|
485 { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0, "[i],d", 0, v6 }, |
|
486 { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldstub [rs1+0],d */ |
|
487 |
|
488 { "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, v9 }, |
|
489 { "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldsw [rs1+%g0],d */ |
|
490 { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d", 0, v9 }, |
|
491 { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d", 0, v9 }, |
|
492 { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0, "[i],d", 0, v9 }, |
|
493 { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldsw [rs1+0],d */ |
|
494 |
|
495 { "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, v6 }, |
|
496 { "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldub [rs1+%g0],d */ |
|
497 { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d", 0, v6 }, |
|
498 { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d", 0, v6 }, |
|
499 { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0, "[i],d", 0, v6 }, |
|
500 { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldub [rs1+0],d */ |
|
501 |
|
502 { "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, v6 }, |
|
503 { "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* lduh [rs1+%g0],d */ |
|
504 { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d", 0, v6 }, |
|
505 { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d", 0, v6 }, |
|
506 { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0, "[i],d", 0, v6 }, |
|
507 { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* lduh [rs1+0],d */ |
|
508 |
|
509 { "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, v9 }, |
|
510 { "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldx [rs1+%g0],d */ |
|
511 { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d", 0, v9 }, |
|
512 { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d", 0, v9 }, |
|
513 { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0, "[i],d", 0, v9 }, |
|
514 { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldx [rs1+0],d */ |
|
515 |
|
516 { "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, v9 }, |
|
517 { "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1), "[1],F", 0, v9 }, /* ld [rs1+%g0],d */ |
|
518 { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, v9 }, |
|
519 { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, v9 }, |
|
520 { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1), "[i],F", 0, v9 }, |
|
521 { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, v9 }, /* ld [rs1+0],d */ |
|
522 |
|
523 { "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, v6 }, |
|
524 { "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lda [rs1+%g0],d */ |
|
525 { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0, v9 }, |
|
526 { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", 0, v9 }, |
|
527 { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
|
528 { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
|
529 { "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2]A,g", 0, v9 }, |
|
530 { "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1]A,g", 0, v9 }, /* lda [rs1+%g0],d */ |
|
531 { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i]o,g", 0, v9 }, |
|
532 { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1]o,g", 0, v9 }, |
|
533 { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i]o,g", 0, v9 }, |
|
534 { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, v9 }, /* ld [rs1+0],d */ |
|
535 |
|
536 { "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0, v6 }, |
|
537 { "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldda [rs1+%g0],d */ |
|
538 { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", 0, v9 }, |
|
539 { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", 0, v9 }, |
|
540 { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
|
541 { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
|
542 |
|
543 { "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0), "[1+2]A,H", 0, v9 }, |
|
544 { "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0, "[1]A,H", 0, v9 }, /* ldda [rs1+%g0],d */ |
|
545 { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i]o,H", 0, v9 }, |
|
546 { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1]o,H", 0, v9 }, |
|
547 { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i]o,H", 0, v9 }, |
|
548 { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H", 0, v9 }, /* ld [rs1+0],d */ |
|
549 |
|
550 { "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0), "[1+2]A,J", 0, v9 }, |
|
551 { "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0, "[1]A,J", 0, v9 }, /* ldd [rs1+%g0],d */ |
|
552 { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[1+i]o,J", 0, v9 }, |
|
553 { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[i+1]o,J", 0, v9 }, |
|
554 { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0, "[i]o,J", 0, v9 }, |
|
555 { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J", 0, v9 }, /* ldd [rs1+0],d */ |
|
556 |
|
557 { "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d", 0, v6 }, |
|
558 { "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsba [rs1+%g0],d */ |
|
559 { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[1+i]o,d", 0, v9 }, |
|
560 { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[i+1]o,d", 0, v9 }, |
|
561 { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
|
562 { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
|
563 |
|
564 { "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d", 0, v6 }, |
|
565 { "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsha [rs1+%g0],d */ |
|
566 { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[1+i]o,d", 0, v9 }, |
|
567 { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[i+1]o,d", 0, v9 }, |
|
568 { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
|
569 { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
|
570 |
|
571 { "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d", 0, v6 }, |
|
572 { "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldstuba [rs1+%g0],d */ |
|
573 { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[1+i]o,d", 0, v9 }, |
|
574 { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[i+1]o,d", 0, v9 }, |
|
575 { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
|
576 { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
|
577 |
|
578 { "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d", 0, v9 }, |
|
579 { "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */ |
|
580 { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[1+i]o,d", 0, v9 }, |
|
581 { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[i+1]o,d", 0, v9 }, |
|
582 { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
|
583 { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
|
584 |
|
585 { "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d", 0, v6 }, |
|
586 { "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduba [rs1+%g0],d */ |
|
587 { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[1+i]o,d", 0, v9 }, |
|
588 { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[i+1]o,d", 0, v9 }, |
|
589 { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
|
590 { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
|
591 |
|
592 { "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d", 0, v6 }, |
|
593 { "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduha [rs1+%g0],d */ |
|
594 { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[1+i]o,d", 0, v9 }, |
|
595 { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[i+1]o,d", 0, v9 }, |
|
596 { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
|
597 { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
|
598 |
|
599 { "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", F_ALIAS, v9 }, /* lduwa === lda */ |
|
600 { "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", F_ALIAS, v9 }, /* lda [rs1+%g0],d */ |
|
601 { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", F_ALIAS, v9 }, |
|
602 { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", F_ALIAS, v9 }, |
|
603 { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", F_ALIAS, v9 }, |
|
604 { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, v9 }, /* ld [rs1+0],d */ |
|
605 |
|
606 { "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d", 0, v9 }, |
|
607 { "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */ |
|
608 { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[1+i]o,d", 0, v9 }, |
|
609 { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[i+1]o,d", 0, v9 }, |
|
610 { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
|
611 { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */ |
|
612 |
|
613 { "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, |
|
614 { "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* st d,[rs1+%g0] */ |
|
615 { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", 0, v6 }, |
|
616 { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", 0, v6 }, |
|
617 { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", 0, v6 }, |
|
618 { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* st d,[rs1+0] */ |
|
619 { "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", 0, v6 }, |
|
620 { "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", 0, v6 }, /* st d[rs1+%g0] */ |
|
621 { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", 0, v6 }, |
|
622 { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", 0, v6 }, |
|
623 { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0, "g,[i]", 0, v6 }, |
|
624 { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", 0, v6 }, /* st d,[rs1+0] */ |
|
625 |
|
626 { "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 }, |
|
627 { "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */ |
|
628 { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", 0, v6notv9 }, |
|
629 { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", 0, v6notv9 }, |
|
630 { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "D,[i]", 0, v6notv9 }, |
|
631 { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+0] */ |
|
632 { "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", 0, v6notv9 }, |
|
633 { "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */ |
|
634 { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", 0, v6notv9 }, |
|
635 { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", 0, v6notv9 }, |
|
636 { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0, "C,[i]", 0, v6notv9 }, |
|
637 { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+0] */ |
|
638 |
|
639 { "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]", 0, v6 }, |
|
640 { "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0), "F,[1]", 0, v6 }, /* st d,[rs1+%g0] */ |
|
641 { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[1+i]", 0, v6 }, |
|
642 { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[i+1]", 0, v6 }, |
|
643 { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0, "F,[i]", 0, v6 }, |
|
644 { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0), "F,[1]", 0, v6 }, /* st d,[rs1+0] */ |
|
645 |
|
646 { "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, |
|
647 { "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ |
|
648 { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, |
|
649 { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, |
|
650 { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, |
|
651 { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ |
|
652 { "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, |
|
653 { "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ |
|
654 { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, |
|
655 { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, |
|
656 { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, |
|
657 { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ |
|
658 { "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 }, |
|
659 { "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */ |
|
660 { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 }, |
|
661 { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 }, |
|
662 { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 }, |
|
663 { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */ |
|
664 |
|
665 { "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, |
|
666 { "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+%g0] */ |
|
667 { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v6 }, |
|
668 { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v6 }, |
|
669 { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, |
|
670 { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+0] */ |
|
671 |
|
672 { "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", 0, v6 }, |
|
673 { "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* sta d,[rs1+%g0] */ |
|
674 { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", 0, v9 }, |
|
675 { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", 0, v9 }, |
|
676 { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", 0, v9 }, |
|
677 { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* st d,[rs1+0] */ |
|
678 |
|
679 { "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0), "g,[1+2]A", 0, v9 }, |
|
680 { "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A", 0, v9 }, /* sta d,[rs1+%g0] */ |
|
681 { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[1+i]o", 0, v9 }, |
|
682 { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[i+1]o", 0, v9 }, |
|
683 { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "g,[i]o", 0, v9 }, |
|
684 { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o", 0, v9 }, /* st d,[rs1+0] */ |
|
685 |
|
686 { "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, |
|
687 { "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ |
|
688 { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, |
|
689 { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, |
|
690 { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, |
|
691 { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ |
|
692 { "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, |
|
693 { "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ |
|
694 { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, |
|
695 { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, |
|
696 { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, |
|
697 { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ |
|
698 { "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 }, |
|
699 { "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */ |
|
700 { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 }, |
|
701 { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 }, |
|
702 { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, |
|
703 { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */ |
|
704 |
|
705 { "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, |
|
706 { "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+%g0] */ |
|
707 { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", 0, v6 }, |
|
708 { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", 0, v6 }, |
|
709 { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", 0, v6 }, |
|
710 { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+0] */ |
|
711 |
|
712 { "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, |
|
713 { "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */ |
|
714 { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 }, |
|
715 { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 }, |
|
716 { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, |
|
717 { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */ |
|
718 { "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, |
|
719 { "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */ |
|
720 { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 }, |
|
721 { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 }, |
|
722 { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, |
|
723 { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */ |
|
724 |
|
725 { "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", 0, v6 }, |
|
726 { "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stba d,[rs1+%g0] */ |
|
727 { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", 0, v9 }, |
|
728 { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", 0, v9 }, |
|
729 { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", 0, v9 }, |
|
730 { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stb d,[rs1+0] */ |
|
731 |
|
732 { "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 }, |
|
733 { "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */ |
|
734 { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 }, |
|
735 { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 }, |
|
736 { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, |
|
737 { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */ |
|
738 { "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 }, |
|
739 { "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */ |
|
740 { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 }, |
|
741 { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 }, |
|
742 { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, |
|
743 { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */ |
|
744 |
|
745 { "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, |
|
746 { "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* std d,[rs1+%g0] */ |
|
747 { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", 0, v6 }, |
|
748 { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", 0, v6 }, |
|
749 { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", 0, v6 }, |
|
750 { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* std d,[rs1+0] */ |
|
751 |
|
752 { "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, v6notv9 }, |
|
753 { "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ |
|
754 { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]", 0, v6notv9 }, |
|
755 { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]", 0, v6notv9 }, |
|
756 { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "q,[i]", 0, v6notv9 }, |
|
757 { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ |
|
758 { "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0, v6 }, |
|
759 { "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "H,[1]", 0, v6 }, /* std d,[rs1+%g0] */ |
|
760 { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[1+i]", 0, v6 }, |
|
761 { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[i+1]", 0, v6 }, |
|
762 { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0, "H,[i]", 0, v6 }, |
|
763 { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]", 0, v6 }, /* std d,[rs1+0] */ |
|
764 |
|
765 { "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, v6notv9 }, |
|
766 { "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ |
|
767 { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]", 0, v6notv9 }, |
|
768 { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]", 0, v6notv9 }, |
|
769 { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "Q,[i]", 0, v6notv9 }, |
|
770 { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ |
|
771 { "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 }, |
|
772 { "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */ |
|
773 { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]", 0, v6notv9 }, |
|
774 { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]", 0, v6notv9 }, |
|
775 { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "D,[i]", 0, v6notv9 }, |
|
776 { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+0] */ |
|
777 |
|
778 { "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, |
|
779 { "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+%g0] */ |
|
780 { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_ALIAS, v6 }, |
|
781 { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_ALIAS, v6 }, |
|
782 { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, |
|
783 { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+0] */ |
|
784 |
|
785 { "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", 0, v6 }, |
|
786 { "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stda d,[rs1+%g0] */ |
|
787 { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", 0, v9 }, |
|
788 { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", 0, v9 }, |
|
789 { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", 0, v9 }, |
|
790 { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* std d,[rs1+0] */ |
|
791 { "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0), "H,[1+2]A", 0, v9 }, |
|
792 { "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A", 0, v9 }, /* stda d,[rs1+%g0] */ |
|
793 { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[1+i]o", 0, v9 }, |
|
794 { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[i+1]o", 0, v9 }, |
|
795 { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "H,[i]o", 0, v9 }, |
|
796 { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o", 0, v9 }, /* std d,[rs1+0] */ |
|
797 |
|
798 { "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, v6 }, |
|
799 { "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+%g0] */ |
|
800 { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", 0, v6 }, |
|
801 { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", 0, v6 }, |
|
802 { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", 0, v6 }, |
|
803 { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+0] */ |
|
804 |
|
805 { "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, |
|
806 { "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */ |
|
807 { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 }, |
|
808 { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 }, |
|
809 { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, |
|
810 { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */ |
|
811 { "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 }, |
|
812 { "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */ |
|
813 { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 }, |
|
814 { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 }, |
|
815 { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 }, |
|
816 { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */ |
|
817 |
|
818 { "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", 0, v6 }, |
|
819 { "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stha ,[rs1+%g0] */ |
|
820 { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", 0, v9 }, |
|
821 { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", 0, v9 }, |
|
822 { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", 0, v9 }, |
|
823 { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* sth d,[rs1+0] */ |
|
824 |
|
825 { "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 }, |
|
826 { "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */ |
|
827 { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 }, |
|
828 { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 }, |
|
829 { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, |
|
830 { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */ |
|
831 { "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 }, |
|
832 { "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */ |
|
833 { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 }, |
|
834 { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 }, |
|
835 { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 }, |
|
836 { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */ |
|
837 |
|
838 { "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, v9 }, |
|
839 { "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+%g0] */ |
|
840 { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]", 0, v9 }, |
|
841 { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]", 0, v9 }, |
|
842 { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0, "d,[i]", 0, v9 }, |
|
843 { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+0] */ |
|
844 |
|
845 { "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, v9 }, |
|
846 { "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+%g0] */ |
|
847 { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[1+i]", 0, v9 }, |
|
848 { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[i+1]", 0, v9 }, |
|
849 { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1), "F,[i]", 0, v9 }, |
|
850 { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+0] */ |
|
851 |
|
852 { "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A", 0, v9 }, |
|
853 { "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, v9 }, /* stxa d,[rs1+%g0] */ |
|
854 { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[1+i]o", 0, v9 }, |
|
855 { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[i+1]o", 0, v9 }, |
|
856 { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0, "d,[i]o", 0, v9 }, |
|
857 { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stx d,[rs1+0] */ |
|
858 |
|
859 { "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0, v9 }, |
|
860 { "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "J,[1]", 0, v9 }, /* stq [rs1+%g0] */ |
|
861 { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[1+i]", 0, v9 }, |
|
862 { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[i+1]", 0, v9 }, |
|
863 { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "J,[i]", 0, v9 }, |
|
864 { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]", 0, v9 }, /* stq [rs1+0] */ |
|
865 |
|
866 { "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0, v9 }, |
|
867 { "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "J,[1]A", 0, v9 }, /* stqa [rs1+%g0] */ |
|
868 { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[1+i]o", 0, v9 }, |
|
869 { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[i+1]o", 0, v9 }, |
|
870 { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "J,[i]o", 0, v9 }, |
|
871 { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o", 0, v9 }, /* stqa [rs1+0] */ |
|
872 |
|
873 { "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, v7 }, |
|
874 { "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, v7 }, /* swap [rs1+%g0],d */ |
|
875 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0, v7 }, |
|
876 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0, v7 }, |
|
877 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0, "[i],d", 0, v7 }, |
|
878 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, v7 }, /* swap [rs1+0],d */ |
|
879 |
|
880 { "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0, v7 }, |
|
881 { "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, v7 }, /* swapa [rs1+%g0],d */ |
|
882 { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[1+i]o,d", 0, v9 }, |
|
883 { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[i+1]o,d", 0, v9 }, |
|
884 { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0, "[i]o,d", 0, v9 }, |
|
885 { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* swap [rs1+0],d */ |
|
886 |
|
887 { "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
|
888 { "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v6 }, /* restore %g0,%g0,%g0 */ |
|
889 { "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d", 0, v6 }, |
|
890 { "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0), "", 0, v6 }, /* restore %g0,0,%g0 */ |
|
891 |
|
892 { "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* rett rs1+rs2 */ |
|
893 { "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1,%g0 */ |
|
894 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* rett rs1+X */ |
|
895 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */ |
|
896 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */ |
|
897 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X */ |
|
898 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1+0 */ |
|
899 |
|
900 { "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
|
901 { "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, v6 }, |
|
902 { "save", 0x81e00000, ~0x81e00000, "", F_ALIAS, v6 }, |
|
903 |
|
904 { "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */ |
|
905 { "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %o7+8,%g0 */ |
|
906 |
|
907 { "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_JSR|F_DELAYED, v6 }, |
|
908 { "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,d */ |
|
909 { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,d */ |
|
910 { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0, "i,d", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,d */ |
|
911 { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d", F_JSR|F_DELAYED, v6 }, |
|
912 { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d", F_JSR|F_DELAYED, v6 }, |
|
913 |
|
914 { "done", F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 }, |
|
915 { "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 }, |
|
916 { "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 }, |
|
917 { "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 }, |
|
918 { "allclean", F3(2, 0x31, 0)|RD(2), F3(~2, ~0x31, ~0)|RD(~2)|RS1_G0|SIMM13(~0), "", 0, v9 }, |
|
919 { "otherw", F3(2, 0x31, 0)|RD(3), F3(~2, ~0x31, ~0)|RD(~3)|RS1_G0|SIMM13(~0), "", 0, v9 }, |
|
920 { "normalw", F3(2, 0x31, 0)|RD(4), F3(~2, ~0x31, ~0)|RD(~4)|RS1_G0|SIMM13(~0), "", 0, v9 }, |
|
921 { "invalw", F3(2, 0x31, 0)|RD(5), F3(~2, ~0x31, ~0)|RD(~5)|RS1_G0|SIMM13(~0), "", 0, v9 }, |
|
922 { "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0, "i", 0, v9 }, |
|
923 |
|
924 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", 0, v8 }, |
|
925 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", 0, v8 }, /* flush rs1+%g0 */ |
|
926 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", 0, v8 }, /* flush rs1+0 */ |
|
927 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", 0, v8 }, /* flush %g0+i */ |
|
928 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", 0, v8 }, |
|
929 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", 0, v8 }, |
|
930 |
|
931 /* IFLUSH was renamed to FLUSH in v8. */ |
|
932 { "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, v6 }, |
|
933 { "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, v6 }, /* flush rs1+%g0 */ |
|
934 { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, v6 }, /* flush rs1+0 */ |
|
935 { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, v6 }, |
|
936 { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, v6 }, |
|
937 { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS, v6 }, |
|
938 |
|
939 { "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, v9 }, |
|
940 { "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0), "1", 0, v9 }, /* return rs1+%g0 */ |
|
941 { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1", 0, v9 }, /* return rs1+0 */ |
|
942 { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0, "i", 0, v9 }, /* return %g0+i */ |
|
943 { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "1+i", 0, v9 }, |
|
944 { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "i+1", 0, v9 }, |
|
945 |
|
946 { "flushw", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v9 }, |
|
947 |
|
948 { "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, v9 }, |
|
949 { "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, v8 }, |
|
950 |
|
951 { "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0), "[1+2],*", 0, v9 }, |
|
952 { "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0, "[1],*", 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */ |
|
953 { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[1+i],*", 0, v9 }, |
|
954 { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[i+1],*", 0, v9 }, |
|
955 { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0, "[i],*", 0, v9 }, |
|
956 { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "[1],*", 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */ |
|
957 { "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0), "[1+2]A,*", 0, v9 }, |
|
958 { "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0, "[1]A,*", 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */ |
|
959 { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[1+i]o,*", 0, v9 }, |
|
960 { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[i+1]o,*", 0, v9 }, |
|
961 { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0, "[i]o,*", 0, v9 }, |
|
962 { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0), "[1]o,*", 0, v9 }, /* prefetcha [rs1+0],d */ |
|
963 |
|
964 { "sll", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, |
|
965 { "sll", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, |
|
966 { "sra", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, |
|
967 { "sra", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, |
|
968 { "srl", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 }, |
|
969 { "srl", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 }, |
|
970 |
|
971 { "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, |
|
972 { "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, |
|
973 { "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, |
|
974 { "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, |
|
975 { "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5), "1,2,d", 0, v9 }, |
|
976 { "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6), "1,Y,d", 0, v9 }, |
|
977 |
|
978 { "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
|
979 { "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d", 0, v6 }, |
|
980 |
|
981 { "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, sparclite }, |
|
982 { "divscc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d", 0, sparclite }, |
|
983 |
|
984 { "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0, sparclet|sparclite }, |
|
985 { "scan", F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1), "1,i,d", 0, sparclet|sparclite }, |
|
986 |
|
987 { "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, v9 }, |
|
988 { "popc", F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0, "i,d", 0, v9 }, |
|
989 |
|
990 { "clr", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "d", F_ALIAS, v6 }, /* or %g0,%g0,d */ |
|
991 { "clr", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0), "d", F_ALIAS, v6 }, /* or %g0,0,d */ |
|
992 { "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, |
|
993 { "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+%g0] */ |
|
994 { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, |
|
995 { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, |
|
996 { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, |
|
997 { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+0] */ |
|
998 |
|
999 { "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, |
|
1000 { "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+%g0] */ |
|
1001 { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, |
|
1002 { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, |
|
1003 { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, |
|
1004 { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+0] */ |
|
1005 |
|
1006 { "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 }, |
|
1007 { "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+%g0] */ |
|
1008 { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 }, |
|
1009 { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 }, |
|
1010 { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 }, |
|
1011 { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+0] */ |
|
1012 |
|
1013 { "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v9 }, |
|
1014 { "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+%g0] */ |
|
1015 { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[1+i]", F_ALIAS, v9 }, |
|
1016 { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[i+1]", F_ALIAS, v9 }, |
|
1017 { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v9 }, |
|
1018 { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+0] */ |
|
1019 |
|
1020 { "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
|
1021 { "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d", 0, v6 }, |
|
1022 { "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d", 0, v6 }, |
|
1023 |
|
1024 /* This is not a commutative instruction. */ |
|
1025 { "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
|
1026 { "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d", 0, v6 }, |
|
1027 |
|
1028 /* This is not a commutative instruction. */ |
|
1029 { "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
|
1030 { "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d", 0, v6 }, |
|
1031 |
|
1032 { "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0), "1", 0, v6 }, /* orcc rs1, %g0, %g0 */ |
|
1033 { "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, v6 }, /* orcc %g0, rs2, %g0 */ |
|
1034 { "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0), "1", 0, v6 }, /* orcc rs1, 0, %g0 */ |
|
1035 |
|
1036 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, v8 }, /* wr r,r,%asrX */ |
|
1037 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, v8 }, /* wr r,i,%asrX */ |
|
1038 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */ |
|
1039 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", 0, v6 }, /* wr r,r,%y */ |
|
1040 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", 0, v6 }, /* wr r,i,%y */ |
|
1041 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */ |
|
1042 { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", 0, v6notv9 }, /* wr r,r,%psr */ |
|
1043 { "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", 0, v6notv9 }, /* wr r,i,%psr */ |
|
1044 { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */ |
|
1045 { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", 0, v6notv9 }, /* wr r,r,%wim */ |
|
1046 { "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", 0, v6notv9 }, /* wr r,i,%wim */ |
|
1047 { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */ |
|
1048 { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", 0, v6notv9 }, /* wr r,r,%tbr */ |
|
1049 { "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", 0, v6notv9 }, /* wr r,i,%tbr */ |
|
1050 { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */ |
|
1051 |
|
1052 { "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, v9 }, /* wr r,r,%ccr */ |
|
1053 { "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E", 0, v9 }, /* wr r,i,%ccr */ |
|
1054 { "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, v9 }, /* wr r,r,%asi */ |
|
1055 { "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o", 0, v9 }, /* wr r,i,%asi */ |
|
1056 { "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, v9 }, /* wr r,r,%fprs */ |
|
1057 { "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6), "1,i,s", 0, v9 }, /* wr r,i,%fprs */ |
|
1058 |
|
1059 { "wr", F3(2, 0x30, 0)|RD(16), F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pcr */ |
|
1060 { "wr", F3(2, 0x30, 1)|RD(16), F3(~2, ~0x30, ~1)|RD(~16), "1,i,_", 0, v9a }, /* wr r,i,%pcr */ |
|
1061 { "wr", F3(2, 0x30, 0)|RD(17), F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pic */ |
|
1062 { "wr", F3(2, 0x30, 1)|RD(17), F3(~2, ~0x30, ~1)|RD(~17), "1,i,_", 0, v9a }, /* wr r,i,%pic */ |
|
1063 { "wr", F3(2, 0x30, 0)|RD(18), F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%dcr */ |
|
1064 { "wr", F3(2, 0x30, 1)|RD(18), F3(~2, ~0x30, ~1)|RD(~18), "1,i,_", 0, v9a }, /* wr r,i,%dcr */ |
|
1065 { "wr", F3(2, 0x30, 0)|RD(19), F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%gsr */ |
|
1066 { "wr", F3(2, 0x30, 1)|RD(19), F3(~2, ~0x30, ~1)|RD(~19), "1,i,_", 0, v9a }, /* wr r,i,%gsr */ |
|
1067 { "wr", F3(2, 0x30, 0)|RD(20), F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%set_softint */ |
|
1068 { "wr", F3(2, 0x30, 1)|RD(20), F3(~2, ~0x30, ~1)|RD(~20), "1,i,_", 0, v9a }, /* wr r,i,%set_softint */ |
|
1069 { "wr", F3(2, 0x30, 0)|RD(21), F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%clear_softint */ |
|
1070 { "wr", F3(2, 0x30, 1)|RD(21), F3(~2, ~0x30, ~1)|RD(~21), "1,i,_", 0, v9a }, /* wr r,i,%clear_softint */ |
|
1071 { "wr", F3(2, 0x30, 0)|RD(22), F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%softint */ |
|
1072 { "wr", F3(2, 0x30, 1)|RD(22), F3(~2, ~0x30, ~1)|RD(~22), "1,i,_", 0, v9a }, /* wr r,i,%softint */ |
|
1073 { "wr", F3(2, 0x30, 0)|RD(23), F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%tick_cmpr */ |
|
1074 { "wr", F3(2, 0x30, 1)|RD(23), F3(~2, ~0x30, ~1)|RD(~23), "1,i,_", 0, v9a }, /* wr r,i,%tick_cmpr */ |
|
1075 { "wr", F3(2, 0x30, 0)|RD(24), F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick */ |
|
1076 { "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick */ |
|
1077 { "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick_cmpr */ |
|
1078 { "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick_cmpr */ |
|
1079 |
|
1080 { "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, v8 }, /* rd %asrX,r */ |
|
1081 { "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, v6 }, /* rd %y,r */ |
|
1082 { "rd", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", 0, v6notv9 }, /* rd %psr,r */ |
|
1083 { "rd", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", 0, v6notv9 }, /* rd %wim,r */ |
|
1084 { "rd", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", 0, v6notv9 }, /* rd %tbr,r */ |
|
1085 |
|
1086 { "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, v9 }, /* rd %ccr,r */ |
|
1087 { "rd", F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, v9 }, /* rd %asi,r */ |
|
1088 { "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, v9 }, /* rd %tick,r */ |
|
1089 { "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, v9 }, /* rd %pc,r */ |
|
1090 { "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, v9 }, /* rd %fprs,r */ |
|
1091 |
|
1092 { "rd", F3(2, 0x28, 0)|RS1(16), F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pcr,r */ |
|
1093 { "rd", F3(2, 0x28, 0)|RS1(17), F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pic,r */ |
|
1094 { "rd", F3(2, 0x28, 0)|RS1(18), F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0), "/,d", 0, v9a }, /* rd %dcr,r */ |
|
1095 { "rd", F3(2, 0x28, 0)|RS1(19), F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0), "/,d", 0, v9a }, /* rd %gsr,r */ |
|
1096 { "rd", F3(2, 0x28, 0)|RS1(22), F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0), "/,d", 0, v9a }, /* rd %softint,r */ |
|
1097 { "rd", F3(2, 0x28, 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d", 0, v9a }, /* rd %tick_cmpr,r */ |
|
1098 { "rd", F3(2, 0x28, 0)|RS1(24), F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick,r */ |
|
1099 { "rd", F3(2, 0x28, 0)|RS1(25), F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick_cmpr,r */ |
|
1100 |
|
1101 { "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, v9 }, /* rdpr %priv,r */ |
|
1102 { "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0), "1,2,!", 0, v9 }, /* wrpr r1,r2,%priv */ |
|
1103 { "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|SIMM13(~0), "1,!", 0, v9 }, /* wrpr r1,%priv */ |
|
1104 { "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "1,i,!", 0, v9 }, /* wrpr r1,i,%priv */ |
|
1105 { "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,1,!", F_ALIAS, v9 }, /* wrpr i,r1,%priv */ |
|
1106 { "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RS1(~0), "i,!", 0, v9 }, /* wrpr i,%priv */ |
|
1107 |
|
1108 { "rdhpr", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|SIMM13(~0), "$,d", 0, v9 }, /* rdhpr %hpriv,r */ |
|
1109 { "wrhpr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0), "1,2,%", 0, v9 }, /* wrhpr r1,r2,%hpriv */ |
|
1110 { "wrhpr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|SIMM13(~0), "1,%", 0, v9 }, /* wrhpr r1,%hpriv */ |
|
1111 { "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "1,i,%", 0, v9 }, /* wrhpr r1,i,%hpriv */ |
|
1112 { "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "i,1,%", F_ALIAS, v9 }, /* wrhpr i,r1,%hpriv */ |
|
1113 { "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RS1(~0), "i,%", 0, v9 }, /* wrhpr i,%hpriv */ |
|
1114 |
|
1115 /* ??? This group seems wrong. A three operand move? */ |
|
1116 { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */ |
|
1117 { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */ |
|
1118 { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", F_ALIAS, v6 }, /* wr r,r,%y */ |
|
1119 { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", F_ALIAS, v6 }, /* wr r,i,%y */ |
|
1120 { "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", F_ALIAS, v6notv9 }, /* wr r,r,%psr */ |
|
1121 { "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", F_ALIAS, v6notv9 }, /* wr r,i,%psr */ |
|
1122 { "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", F_ALIAS, v6notv9 }, /* wr r,r,%wim */ |
|
1123 { "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", F_ALIAS, v6notv9 }, /* wr r,i,%wim */ |
|
1124 { "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", F_ALIAS, v6notv9 }, /* wr r,r,%tbr */ |
|
1125 { "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", F_ALIAS, v6notv9 }, /* wr r,i,%tbr */ |
|
1126 |
|
1127 { "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", F_ALIAS, v8 }, /* rd %asr1,r */ |
|
1128 { "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", F_ALIAS, v6 }, /* rd %y,r */ |
|
1129 { "mov", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", F_ALIAS, v6notv9 }, /* rd %psr,r */ |
|
1130 { "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", F_ALIAS, v6notv9 }, /* rd %wim,r */ |
|
1131 { "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", F_ALIAS, v6notv9 }, /* rd %tbr,r */ |
|
1132 |
|
1133 { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */ |
|
1134 { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "i,m", F_ALIAS, v8 }, /* wr %g0,i,%asrX */ |
|
1135 { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,0,%asrX */ |
|
1136 { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */ |
|
1137 { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "i,y", F_ALIAS, v6 }, /* wr %g0,i,%y */ |
|
1138 { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,0,%y */ |
|
1139 { "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */ |
|
1140 { "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "i,p", F_ALIAS, v6notv9 }, /* wr %g0,i,%psr */ |
|
1141 { "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,0,%psr */ |
|
1142 { "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */ |
|
1143 { "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "i,w", F_ALIAS, v6notv9 }, /* wr %g0,i,%wim */ |
|
1144 { "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,0,%wim */ |
|
1145 { "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */ |
|
1146 { "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "i,t", F_ALIAS, v6notv9 }, /* wr %g0,i,%tbr */ |
|
1147 { "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,0,%tbr */ |
|
1148 |
|
1149 { "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0), "2,d", 0, v6 }, /* or %g0,rs2,d */ |
|
1150 { "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0, "i,d", 0, v6 }, /* or %g0,i,d */ |
|
1151 { "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0), "1,d", 0, v6 }, /* or rs1,%g0,d */ |
|
1152 { "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0), "1,d", 0, v6 }, /* or rs1,0,d */ |
|
1153 |
|
1154 { "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
|
1155 { "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d", 0, v6 }, |
|
1156 { "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d", 0, v6 }, |
|
1157 |
|
1158 { "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* or rd,rs2,rd */ |
|
1159 { "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS, v6 }, /* or rd,i,rd */ |
|
1160 |
|
1161 /* This is not a commutative instruction. */ |
|
1162 { "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
|
1163 { "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d", 0, v6 }, |
|
1164 |
|
1165 /* This is not a commutative instruction. */ |
|
1166 { "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
|
1167 { "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d", 0, v6 }, |
|
1168 |
|
1169 { "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* andn rd,rs2,rd */ |
|
1170 { "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS, v6 }, /* andn rd,i,rd */ |
|
1171 |
|
1172 { "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0), "1,2", 0, v6 }, /* subcc rs1,rs2,%g0 */ |
|
1173 { "cmp", F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0, "1,i", 0, v6 }, /* subcc rs1,i,%g0 */ |
|
1174 |
|
1175 { "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
|
1176 { "sub", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d", 0, v6 }, |
|
1177 |
|
1178 { "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
|
1179 { "subcc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d", 0, v6 }, |
|
1180 |
|
1181 { "subx", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, |
|
1182 { "subx", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v6notv9 }, |
|
1183 { "subc", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v9 }, |
|
1184 { "subc", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v9 }, |
|
1185 |
|
1186 { "subxcc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, |
|
1187 { "subxcc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v6notv9 }, |
|
1188 { "subccc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v9 }, |
|
1189 { "subccc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v9 }, |
|
1190 |
|
1191 { "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
|
1192 { "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d", 0, v6 }, |
|
1193 { "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d", 0, v6 }, |
|
1194 |
|
1195 { "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
|
1196 { "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d", 0, v6 }, |
|
1197 { "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d", 0, v6 }, |
|
1198 |
|
1199 { "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* sub rd,1,rd */ |
|
1200 { "dec", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "i,r", F_ALIAS, v8 }, /* sub rd,imm,rd */ |
|
1201 { "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* subcc rd,1,rd */ |
|
1202 { "deccc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "i,r", F_ALIAS, v8 }, /* subcc rd,imm,rd */ |
|
1203 { "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* add rd,1,rd */ |
|
1204 { "inc", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,r", F_ALIAS, v8 }, /* add rd,imm,rd */ |
|
1205 { "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* addcc rd,1,rd */ |
|
1206 { "inccc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,r", F_ALIAS, v8 }, /* addcc rd,imm,rd */ |
|
1207 |
|
1208 { "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, v6 }, /* andcc rs1,rs2,%g0 */ |
|
1209 { "btst", F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, v6 }, /* andcc rs1,i,%g0 */ |
|
1210 |
|
1211 { "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, v6 }, /* sub %g0,rs2,rd */ |
|
1212 { "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, v6 }, /* sub %g0,rd,rd */ |
|
1213 |
|
1214 { "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
|
1215 { "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d", 0, v6 }, |
|
1216 { "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d", 0, v6 }, |
|
1217 { "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
|
1218 { "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d", 0, v6 }, |
|
1219 { "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d", 0, v6 }, |
|
1220 |
|
1221 { "addx", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, |
|
1222 { "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v6notv9 }, |
|
1223 { "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v6notv9 }, |
|
1224 { "addc", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v9 }, |
|
1225 { "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v9 }, |
|
1226 { "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v9 }, |
|
1227 |
|
1228 { "addxcc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v6notv9 }, |
|
1229 { "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v6notv9 }, |
|
1230 { "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v6notv9 }, |
|
1231 { "addccc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v9 }, |
|
1232 { "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v9 }, |
|
1233 { "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v9 }, |
|
1234 |
|
1235 { "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, v8 }, |
|
1236 { "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, v8 }, |
|
1237 { "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d", 0, v8 }, |
|
1238 { "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, v8 }, |
|
1239 { "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d", 0, v8 }, |
|
1240 { "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d", 0, v8 }, |
|
1241 { "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, v8 }, |
|
1242 { "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d", 0, v8 }, |
|
1243 { "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d", 0, v8 }, |
|
1244 { "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, v8 }, |
|
1245 { "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d", 0, v8 }, |
|
1246 { "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d", 0, v8 }, |
|
1247 { "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, v8 }, |
|
1248 { "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d", 0, v8 }, |
|
1249 { "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d", 0, v8 }, |
|
1250 { "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, v8 }, |
|
1251 { "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d", 0, v8 }, |
|
1252 { "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d", 0, v8 }, |
|
1253 { "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, v8 }, |
|
1254 { "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d", 0, v8 }, |
|
1255 { "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d", 0, v8 }, |
|
1256 { "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, v8 }, |
|
1257 { "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d", 0, v8 }, |
|
1258 { "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d", 0, v8 }, |
|
1259 |
|
1260 { "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, v9 }, |
|
1261 { "mulx", F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d", 0, v9 }, |
|
1262 { "sdivx", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, v9 }, |
|
1263 { "sdivx", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, v9 }, |
|
1264 { "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, v9 }, |
|
1265 { "udivx", F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d", 0, v9 }, |
|
1266 |
|
1267 { "call", F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, v6 }, |
|
1268 { "call", F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, v6 }, |
|
1269 |
|
1270 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%o7 */ |
|
1271 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2,#", F_JSR|F_DELAYED, v6 }, |
|
1272 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%o7 */ |
|
1273 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR|F_DELAYED, v6 }, |
|
1274 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+i,%o7 */ |
|
1275 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i,#", F_JSR|F_DELAYED, v6 }, |
|
1276 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1", F_JSR|F_DELAYED, v6 }, /* jmpl i+rs1,%o7 */ |
|
1277 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1,#", F_JSR|F_DELAYED, v6 }, |
|
1278 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,%o7 */ |
|
1279 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i,#", F_JSR|F_DELAYED, v6 }, |
|
1280 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,%o7 */ |
|
1281 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR|F_DELAYED, v6 }, |
|
1282 |
|
1283 |
|
1284 /* Conditional instructions. |
|
1285 |
|
1286 Because this part of the table was such a mess earlier, I have |
|
1287 macrofied it so that all the branches and traps are generated from |
|
1288 a single-line description of each condition value. John Gilmore. */ |
|
1289 |
|
1290 /* Define branches -- one annulled, one without, etc. */ |
|
1291 #define br(opcode, mask, lose, flags) \ |
|
1292 { opcode, (mask)|ANNUL, (lose), ",a l", (flags), v6 }, \ |
|
1293 { opcode, (mask) , (lose)|ANNUL, "l", (flags), v6 } |
|
1294 |
|
1295 #define brx(opcode, mask, lose, flags) /* v9 */ \ |
|
1296 { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G", (flags), v9 }, \ |
|
1297 { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G", (flags), v9 }, \ |
|
1298 { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G", (flags), v9 }, \ |
|
1299 { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), v9 }, \ |
|
1300 { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G", (flags), v9 }, \ |
|
1301 { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), v9 }, \ |
|
1302 { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G", (flags), v9 }, \ |
|
1303 { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G", (flags), v9 }, \ |
|
1304 { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G", (flags), v9 }, \ |
|
1305 { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), v9 }, \ |
|
1306 { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G", (flags), v9 }, \ |
|
1307 { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), v9 } |
|
1308 |
|
1309 /* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */ |
|
1310 #define tr(opcode, mask, lose, flags) \ |
|
1311 { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i", (flags), v9 }, /* %g0 + imm */ \ |
|
1312 { opcode, (mask)|(2<<11)|IMMED, (lose), "Z,1+i", (flags), v9 }, /* rs1 + imm */ \ |
|
1313 { opcode, (mask)|(2<<11), IMMED|(lose), "Z,1+2", (flags), v9 }, /* rs1 + rs2 */ \ |
|
1314 { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1", (flags), v9 }, /* rs1 + %g0 */ \ |
|
1315 { opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i", (flags)|F_ALIAS, v9 }, /* %g0 + imm */ \ |
|
1316 { opcode, (mask)|IMMED, (lose), "z,1+i", (flags)|F_ALIAS, v9 }, /* rs1 + imm */ \ |
|
1317 { opcode, (mask), IMMED|(lose), "z,1+2", (flags)|F_ALIAS, v9 }, /* rs1 + rs2 */ \ |
|
1318 { opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, v9 }, /* rs1 + %g0 */ \ |
|
1319 { opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), v6 }, /* %g0 + imm */ \ |
|
1320 { opcode, (mask)|IMMED, (lose), "1+i", (flags), v6 }, /* rs1 + imm */ \ |
|
1321 { opcode, (mask), IMMED|(lose), "1+2", (flags), v6 }, /* rs1 + rs2 */ \ |
|
1322 { opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), v6 } /* rs1 + %g0 */ |
|
1323 |
|
1324 /* v9: We must put `brx' before `br', to ensure that we never match something |
|
1325 v9: against an expression unless it is an expression. Otherwise, we end |
|
1326 v9: up with undefined symbol tables entries, because they get added, but |
|
1327 v9: are not deleted if the pattern fails to match. */ |
|
1328 |
|
1329 /* Define both branches and traps based on condition mask */ |
|
1330 #define cond(bop, top, mask, flags) \ |
|
1331 brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \ |
|
1332 br(bop, F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \ |
|
1333 tr(top, F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR))) |
|
1334 |
|
1335 /* Define all the conditions, all the branches, all the traps. */ |
|
1336 |
|
1337 /* Standard branch, trap mnemonics */ |
|
1338 cond ("b", "ta", CONDA, F_UNBR), |
|
1339 /* Alternative form (just for assembly, not for disassembly) */ |
|
1340 cond ("ba", "t", CONDA, F_UNBR|F_ALIAS), |
|
1341 |
|
1342 cond ("bcc", "tcc", CONDCC, F_CONDBR), |
|
1343 cond ("bcs", "tcs", CONDCS, F_CONDBR), |
|
1344 cond ("be", "te", CONDE, F_CONDBR), |
|
1345 cond ("beq", "teq", CONDE, F_CONDBR|F_ALIAS), |
|
1346 cond ("bg", "tg", CONDG, F_CONDBR), |
|
1347 cond ("bgt", "tgt", CONDG, F_CONDBR|F_ALIAS), |
|
1348 cond ("bge", "tge", CONDGE, F_CONDBR), |
|
1349 cond ("bgeu", "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */ |
|
1350 cond ("bgu", "tgu", CONDGU, F_CONDBR), |
|
1351 cond ("bl", "tl", CONDL, F_CONDBR), |
|
1352 cond ("blt", "tlt", CONDL, F_CONDBR|F_ALIAS), |
|
1353 cond ("ble", "tle", CONDLE, F_CONDBR), |
|
1354 cond ("bleu", "tleu", CONDLEU, F_CONDBR), |
|
1355 cond ("blu", "tlu", CONDLU, F_CONDBR|F_ALIAS), /* for cs */ |
|
1356 cond ("bn", "tn", CONDN, F_CONDBR), |
|
1357 cond ("bne", "tne", CONDNE, F_CONDBR), |
|
1358 cond ("bneg", "tneg", CONDNEG, F_CONDBR), |
|
1359 cond ("bnz", "tnz", CONDNZ, F_CONDBR|F_ALIAS), /* for ne */ |
|
1360 cond ("bpos", "tpos", CONDPOS, F_CONDBR), |
|
1361 cond ("bvc", "tvc", CONDVC, F_CONDBR), |
|
1362 cond ("bvs", "tvs", CONDVS, F_CONDBR), |
|
1363 cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */ |
|
1364 |
|
1365 #undef cond |
|
1366 #undef br |
|
1367 #undef brr /* v9 */ |
|
1368 #undef tr |
|
1369 |
|
1370 #define brr(opcode, mask, lose, flags) /* v9 */ \ |
|
1371 { opcode, (mask)|BPRED, ANNUL|(lose), "1,k", F_DELAYED|(flags), v9 }, \ |
|
1372 { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k", F_DELAYED|(flags), v9 }, \ |
|
1373 { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k", F_DELAYED|(flags), v9 }, \ |
|
1374 { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), v9 }, \ |
|
1375 { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k", F_DELAYED|(flags), v9 }, \ |
|
1376 { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), v9 } |
|
1377 |
|
1378 #define condr(bop, mask, flags) /* v9 */ \ |
|
1379 brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */ |
|
1380 |
|
1381 /* v9 */ condr("brnz", 0x5, F_CONDBR), |
|
1382 /* v9 */ condr("brz", 0x1, F_CONDBR), |
|
1383 /* v9 */ condr("brgez", 0x7, F_CONDBR), |
|
1384 /* v9 */ condr("brlz", 0x3, F_CONDBR), |
|
1385 /* v9 */ condr("brlez", 0x2, F_CONDBR), |
|
1386 /* v9 */ condr("brgz", 0x6, F_CONDBR), |
|
1387 |
|
1388 #undef condr /* v9 */ |
|
1389 #undef brr /* v9 */ |
|
1390 |
|
1391 #define movr(opcode, mask, flags) /* v9 */ \ |
|
1392 { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), v9 }, \ |
|
1393 { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), v9 } |
|
1394 |
|
1395 #define fmrrs(opcode, mask, lose, flags) /* v9 */ \ |
|
1396 { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, v9 } |
|
1397 #define fmrrd(opcode, mask, lose, flags) /* v9 */ \ |
|
1398 { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, v9 } |
|
1399 #define fmrrq(opcode, mask, lose, flags) /* v9 */ \ |
|
1400 { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, v9 } |
|
1401 |
|
1402 #define fmovrs(mop, mask, flags) /* v9 */ \ |
|
1403 fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */ |
|
1404 #define fmovrd(mop, mask, flags) /* v9 */ \ |
|
1405 fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */ |
|
1406 #define fmovrq(mop, mask, flags) /* v9 */ \ |
|
1407 fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */ |
|
1408 |
|
1409 /* v9 */ movr("movrne", 0x5, 0), |
|
1410 /* v9 */ movr("movre", 0x1, 0), |
|
1411 /* v9 */ movr("movrgez", 0x7, 0), |
|
1412 /* v9 */ movr("movrlz", 0x3, 0), |
|
1413 /* v9 */ movr("movrlez", 0x2, 0), |
|
1414 /* v9 */ movr("movrgz", 0x6, 0), |
|
1415 /* v9 */ movr("movrnz", 0x5, F_ALIAS), |
|
1416 /* v9 */ movr("movrz", 0x1, F_ALIAS), |
|
1417 |
|
1418 /* v9 */ fmovrs("fmovrsne", 0x5, 0), |
|
1419 /* v9 */ fmovrs("fmovrse", 0x1, 0), |
|
1420 /* v9 */ fmovrs("fmovrsgez", 0x7, 0), |
|
1421 /* v9 */ fmovrs("fmovrslz", 0x3, 0), |
|
1422 /* v9 */ fmovrs("fmovrslez", 0x2, 0), |
|
1423 /* v9 */ fmovrs("fmovrsgz", 0x6, 0), |
|
1424 /* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS), |
|
1425 /* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS), |
|
1426 |
|
1427 /* v9 */ fmovrd("fmovrdne", 0x5, 0), |
|
1428 /* v9 */ fmovrd("fmovrde", 0x1, 0), |
|
1429 /* v9 */ fmovrd("fmovrdgez", 0x7, 0), |
|
1430 /* v9 */ fmovrd("fmovrdlz", 0x3, 0), |
|
1431 /* v9 */ fmovrd("fmovrdlez", 0x2, 0), |
|
1432 /* v9 */ fmovrd("fmovrdgz", 0x6, 0), |
|
1433 /* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS), |
|
1434 /* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS), |
|
1435 |
|
1436 /* v9 */ fmovrq("fmovrqne", 0x5, 0), |
|
1437 /* v9 */ fmovrq("fmovrqe", 0x1, 0), |
|
1438 /* v9 */ fmovrq("fmovrqgez", 0x7, 0), |
|
1439 /* v9 */ fmovrq("fmovrqlz", 0x3, 0), |
|
1440 /* v9 */ fmovrq("fmovrqlez", 0x2, 0), |
|
1441 /* v9 */ fmovrq("fmovrqgz", 0x6, 0), |
|
1442 /* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS), |
|
1443 /* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS), |
|
1444 |
|
1445 #undef movr /* v9 */ |
|
1446 #undef fmovr /* v9 */ |
|
1447 #undef fmrr /* v9 */ |
|
1448 |
|
1449 #define movicc(opcode, cond, flags) /* v9 */ \ |
|
1450 { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, v9 }, \ |
|
1451 { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, v9 }, \ |
|
1452 { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11), "Z,2,d", flags, v9 }, \ |
|
1453 { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11), "Z,I,d", flags, v9 } |
|
1454 |
|
1455 #define movfcc(opcode, fcond, flags) /* v9 */ \ |
|
1456 { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, v9 }, \ |
|
1457 { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, v9 }, \ |
|
1458 { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, v9 }, \ |
|
1459 { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, v9 }, \ |
|
1460 { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, v9 }, \ |
|
1461 { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, v9 }, \ |
|
1462 { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, v9 }, \ |
|
1463 { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, v9 } |
|
1464 |
|
1465 #define movcc(opcode, cond, fcond, flags) /* v9 */ \ |
|
1466 movfcc (opcode, fcond, flags), /* v9 */ \ |
|
1467 movicc (opcode, cond, flags) /* v9 */ |
|
1468 |
|
1469 /* v9 */ movcc ("mova", CONDA, FCONDA, 0), |
|
1470 /* v9 */ movicc ("movcc", CONDCC, 0), |
|
1471 /* v9 */ movicc ("movgeu", CONDGEU, F_ALIAS), |
|
1472 /* v9 */ movicc ("movcs", CONDCS, 0), |
|
1473 /* v9 */ movicc ("movlu", CONDLU, F_ALIAS), |
|
1474 /* v9 */ movcc ("move", CONDE, FCONDE, 0), |
|
1475 /* v9 */ movcc ("movg", CONDG, FCONDG, 0), |
|
1476 /* v9 */ movcc ("movge", CONDGE, FCONDGE, 0), |
|
1477 /* v9 */ movicc ("movgu", CONDGU, 0), |
|
1478 /* v9 */ movcc ("movl", CONDL, FCONDL, 0), |
|
1479 /* v9 */ movcc ("movle", CONDLE, FCONDLE, 0), |
|
1480 /* v9 */ movicc ("movleu", CONDLEU, 0), |
|
1481 /* v9 */ movfcc ("movlg", FCONDLG, 0), |
|
1482 /* v9 */ movcc ("movn", CONDN, FCONDN, 0), |
|
1483 /* v9 */ movcc ("movne", CONDNE, FCONDNE, 0), |
|
1484 /* v9 */ movicc ("movneg", CONDNEG, 0), |
|
1485 /* v9 */ movcc ("movnz", CONDNZ, FCONDNZ, F_ALIAS), |
|
1486 /* v9 */ movfcc ("movo", FCONDO, 0), |
|
1487 /* v9 */ movicc ("movpos", CONDPOS, 0), |
|
1488 /* v9 */ movfcc ("movu", FCONDU, 0), |
|
1489 /* v9 */ movfcc ("movue", FCONDUE, 0), |
|
1490 /* v9 */ movfcc ("movug", FCONDUG, 0), |
|
1491 /* v9 */ movfcc ("movuge", FCONDUGE, 0), |
|
1492 /* v9 */ movfcc ("movul", FCONDUL, 0), |
|
1493 /* v9 */ movfcc ("movule", FCONDULE, 0), |
|
1494 /* v9 */ movicc ("movvc", CONDVC, 0), |
|
1495 /* v9 */ movicc ("movvs", CONDVS, 0), |
|
1496 /* v9 */ movcc ("movz", CONDZ, FCONDZ, F_ALIAS), |
|
1497 |
|
1498 #undef movicc /* v9 */ |
|
1499 #undef movfcc /* v9 */ |
|
1500 #undef movcc /* v9 */ |
|
1501 |
|
1502 #define FM_SF 1 /* v9 - values for fpsize */ |
|
1503 #define FM_DF 2 /* v9 */ |
|
1504 #define FM_QF 3 /* v9 */ |
|
1505 |
|
1506 #define fmoviccx(opcode, fpsize, args, cond, flags) /* v9 */ \ |
|
1507 { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags, v9 }, \ |
|
1508 { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags, v9 } |
|
1509 |
|
1510 #define fmovfccx(opcode, fpsize, args, fcond, flags) /* v9 */ \ |
|
1511 { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags, v9 }, \ |
|
1512 { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags, v9 }, \ |
|
1513 { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags, v9 }, \ |
|
1514 { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags, v9 } |
|
1515 |
|
1516 /* FIXME: use fmovicc/fmovfcc? */ /* v9 */ |
|
1517 #define fmovccx(opcode, fpsize, args, cond, fcond, flags) /* v9 */ \ |
|
1518 { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags | F_FLOAT, v9 }, \ |
|
1519 { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags | F_FLOAT, v9 }, \ |
|
1520 { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags | F_FLOAT, v9 }, \ |
|
1521 { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags | F_FLOAT, v9 }, \ |
|
1522 { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags | F_FLOAT, v9 }, \ |
|
1523 { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags | F_FLOAT, v9 } |
|
1524 |
|
1525 #define fmovicc(suffix, cond, flags) /* v9 */ \ |
|
1526 fmoviccx("fmovd" suffix, FM_DF, "B,H", cond, flags), \ |
|
1527 fmoviccx("fmovq" suffix, FM_QF, "R,J", cond, flags), \ |
|
1528 fmoviccx("fmovs" suffix, FM_SF, "f,g", cond, flags) |
|
1529 |
|
1530 #define fmovfcc(suffix, fcond, flags) /* v9 */ \ |
|
1531 fmovfccx("fmovd" suffix, FM_DF, "B,H", fcond, flags), \ |
|
1532 fmovfccx("fmovq" suffix, FM_QF, "R,J", fcond, flags), \ |
|
1533 fmovfccx("fmovs" suffix, FM_SF, "f,g", fcond, flags) |
|
1534 |
|
1535 #define fmovcc(suffix, cond, fcond, flags) /* v9 */ \ |
|
1536 fmovccx("fmovd" suffix, FM_DF, "B,H", cond, fcond, flags), \ |
|
1537 fmovccx("fmovq" suffix, FM_QF, "R,J", cond, fcond, flags), \ |
|
1538 fmovccx("fmovs" suffix, FM_SF, "f,g", cond, fcond, flags) |
|
1539 |
|
1540 /* v9 */ fmovcc ("a", CONDA, FCONDA, 0), |
|
1541 /* v9 */ fmovicc ("cc", CONDCC, 0), |
|
1542 /* v9 */ fmovicc ("cs", CONDCS, 0), |
|
1543 /* v9 */ fmovcc ("e", CONDE, FCONDE, 0), |
|
1544 /* v9 */ fmovcc ("g", CONDG, FCONDG, 0), |
|
1545 /* v9 */ fmovcc ("ge", CONDGE, FCONDGE, 0), |
|
1546 /* v9 */ fmovicc ("geu", CONDGEU, F_ALIAS), |
|
1547 /* v9 */ fmovicc ("gu", CONDGU, 0), |
|
1548 /* v9 */ fmovcc ("l", CONDL, FCONDL, 0), |
|
1549 /* v9 */ fmovcc ("le", CONDLE, FCONDLE, 0), |
|
1550 /* v9 */ fmovicc ("leu", CONDLEU, 0), |
|
1551 /* v9 */ fmovfcc ("lg", FCONDLG, 0), |
|
1552 /* v9 */ fmovicc ("lu", CONDLU, F_ALIAS), |
|
1553 /* v9 */ fmovcc ("n", CONDN, FCONDN, 0), |
|
1554 /* v9 */ fmovcc ("ne", CONDNE, FCONDNE, 0), |
|
1555 /* v9 */ fmovicc ("neg", CONDNEG, 0), |
|
1556 /* v9 */ fmovcc ("nz", CONDNZ, FCONDNZ, F_ALIAS), |
|
1557 /* v9 */ fmovfcc ("o", FCONDO, 0), |
|
1558 /* v9 */ fmovicc ("pos", CONDPOS, 0), |
|
1559 /* v9 */ fmovfcc ("u", FCONDU, 0), |
|
1560 /* v9 */ fmovfcc ("ue", FCONDUE, 0), |
|
1561 /* v9 */ fmovfcc ("ug", FCONDUG, 0), |
|
1562 /* v9 */ fmovfcc ("uge", FCONDUGE, 0), |
|
1563 /* v9 */ fmovfcc ("ul", FCONDUL, 0), |
|
1564 /* v9 */ fmovfcc ("ule", FCONDULE, 0), |
|
1565 /* v9 */ fmovicc ("vc", CONDVC, 0), |
|
1566 /* v9 */ fmovicc ("vs", CONDVS, 0), |
|
1567 /* v9 */ fmovcc ("z", CONDZ, FCONDZ, F_ALIAS), |
|
1568 |
|
1569 #undef fmoviccx /* v9 */ |
|
1570 #undef fmovfccx /* v9 */ |
|
1571 #undef fmovccx /* v9 */ |
|
1572 #undef fmovicc /* v9 */ |
|
1573 #undef fmovfcc /* v9 */ |
|
1574 #undef fmovcc /* v9 */ |
|
1575 #undef FM_DF /* v9 */ |
|
1576 #undef FM_QF /* v9 */ |
|
1577 #undef FM_SF /* v9 */ |
|
1578 |
|
1579 /* Coprocessor branches. */ |
|
1580 #define CBR(opcode, mask, lose, flags, arch) \ |
|
1581 { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED, arch }, \ |
|
1582 { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED, arch } |
|
1583 |
|
1584 /* Floating point branches. */ |
|
1585 #define FBR(opcode, mask, lose, flags) \ |
|
1586 { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED | F_FBR, v6 }, \ |
|
1587 { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED | F_FBR, v6 } |
|
1588 |
|
1589 /* V9 extended floating point branches. */ |
|
1590 #define FBRX(opcode, mask, lose, flags) /* v9 */ \ |
|
1591 { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G", flags|F_DELAYED|F_FBR, v9 }, \ |
|
1592 { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G", flags|F_DELAYED|F_FBR, v9 }, \ |
|
1593 { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G", flags|F_DELAYED|F_FBR, v9 }, \ |
|
1594 { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, v9 }, \ |
|
1595 { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G", flags|F_DELAYED|F_FBR, v9 }, \ |
|
1596 { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, v9 }, \ |
|
1597 { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G", flags|F_DELAYED|F_FBR, v9 }, \ |
|
1598 { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G", flags|F_DELAYED|F_FBR, v9 }, \ |
|
1599 { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G", flags|F_DELAYED|F_FBR, v9 }, \ |
|
1600 { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, v9 }, \ |
|
1601 { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G", flags|F_DELAYED|F_FBR, v9 }, \ |
|
1602 { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, v9 }, \ |
|
1603 { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G", flags|F_DELAYED|F_FBR, v9 }, \ |
|
1604 { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G", flags|F_DELAYED|F_FBR, v9 }, \ |
|
1605 { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G", flags|F_DELAYED|F_FBR, v9 }, \ |
|
1606 { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, v9 }, \ |
|
1607 { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G", flags|F_DELAYED|F_FBR, v9 }, \ |
|
1608 { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, v9 }, \ |
|
1609 { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G", flags|F_DELAYED|F_FBR, v9 }, \ |
|
1610 { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G", flags|F_DELAYED|F_FBR, v9 }, \ |
|
1611 { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G", flags|F_DELAYED|F_FBR, v9 }, \ |
|
1612 { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, v9 }, \ |
|
1613 { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G", flags|F_DELAYED|F_FBR, v9 }, \ |
|
1614 { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, v9 } |
|
1615 |
|
1616 /* v9: We must put `FBRX' before `FBR', to ensure that we never match |
|
1617 v9: something against an expression unless it is an expression. Otherwise, |
|
1618 v9: we end up with undefined symbol tables entries, because they get added, |
|
1619 v9: but are not deleted if the pattern fails to match. */ |
|
1620 |
|
1621 #define CONDFC(fop, cop, mask, flags) \ |
|
1622 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ |
|
1623 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \ |
|
1624 CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet) |
|
1625 |
|
1626 #define CONDFCL(fop, cop, mask, flags) \ |
|
1627 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ |
|
1628 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \ |
|
1629 CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6) |
|
1630 |
|
1631 #define CONDF(fop, mask, flags) \ |
|
1632 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ |
|
1633 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags) |
|
1634 |
|
1635 CONDFC ("fb", "cb", 0x8, F_UNBR), |
|
1636 CONDFCL ("fba", "cba", 0x8, F_UNBR|F_ALIAS), |
|
1637 CONDFC ("fbe", "cb0", 0x9, F_CONDBR), |
|
1638 CONDF ("fbz", 0x9, F_CONDBR|F_ALIAS), |
|
1639 CONDFC ("fbg", "cb2", 0x6, F_CONDBR), |
|
1640 CONDFC ("fbge", "cb02", 0xb, F_CONDBR), |
|
1641 CONDFC ("fbl", "cb1", 0x4, F_CONDBR), |
|
1642 CONDFC ("fble", "cb01", 0xd, F_CONDBR), |
|
1643 CONDFC ("fblg", "cb12", 0x2, F_CONDBR), |
|
1644 CONDFCL ("fbn", "cbn", 0x0, F_UNBR), |
|
1645 CONDFC ("fbne", "cb123", 0x1, F_CONDBR), |
|
1646 CONDF ("fbnz", 0x1, F_CONDBR|F_ALIAS), |
|
1647 CONDFC ("fbo", "cb012", 0xf, F_CONDBR), |
|
1648 CONDFC ("fbu", "cb3", 0x7, F_CONDBR), |
|
1649 CONDFC ("fbue", "cb03", 0xa, F_CONDBR), |
|
1650 CONDFC ("fbug", "cb23", 0x5, F_CONDBR), |
|
1651 CONDFC ("fbuge", "cb023", 0xc, F_CONDBR), |
|
1652 CONDFC ("fbul", "cb13", 0x3, F_CONDBR), |
|
1653 CONDFC ("fbule", "cb013", 0xe, F_CONDBR), |
|
1654 |
|
1655 #undef CONDFC |
|
1656 #undef CONDFCL |
|
1657 #undef CONDF |
|
1658 #undef CBR |
|
1659 #undef FBR |
|
1660 #undef FBRX /* v9 */ |
|
1661 |
|
1662 { "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%g0 */ |
|
1663 { "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%g0 */ |
|
1664 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+i,%g0 */ |
|
1665 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* jmpl i+rs1,%g0 */ |
|
1666 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* jmpl %g0+i,%g0 */ |
|
1667 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+0,%g0 */ |
|
1668 |
|
1669 { "nop", F2(0, 4), 0xfeffffff, "", 0, v6 }, /* sethi 0, %g0 */ |
|
1670 |
|
1671 { "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v6 }, |
|
1672 { "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 }, |
|
1673 { "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 }, |
|
1674 { "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, v9 }, |
|
1675 |
|
1676 { "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6 }, |
|
1677 |
|
1678 { "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
|
1679 { "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, v6 }, |
|
1680 { "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d", 0, v6 }, |
|
1681 { "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
|
1682 { "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "1,i,d", 0, v6 }, |
|
1683 { "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "i,1,d", 0, v6 }, |
|
1684 |
|
1685 { "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
|
1686 { "tsubcc", F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d", 0, v6 }, |
|
1687 { "tsubcctv", F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
|
1688 { "tsubcctv", F3(2, 0x23, 1), F3(~2, ~0x23, ~1), "1,i,d", 0, v6 }, |
|
1689 |
|
1690 { "unimp", F2(0x0, 0x0), 0xffc00000, "n", 0, v6notv9 }, |
|
1691 { "illtrap", F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, v9 }, |
|
1692 |
|
1693 /* This *is* a commutative instruction. */ |
|
1694 { "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
|
1695 { "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d", 0, v6 }, |
|
1696 { "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d", 0, v6 }, |
|
1697 /* This *is* a commutative instruction. */ |
|
1698 { "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
|
1699 { "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d", 0, v6 }, |
|
1700 { "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d", 0, v6 }, |
|
1701 { "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
|
1702 { "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d", 0, v6 }, |
|
1703 { "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d", 0, v6 }, |
|
1704 { "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, v6 }, |
|
1705 { "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d", 0, v6 }, |
|
1706 { "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d", 0, v6 }, |
|
1707 |
|
1708 { "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, v6 }, /* xnor rs1,%0,rd */ |
|
1709 { "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, v6 }, /* xnor rd,%0,rd */ |
|
1710 |
|
1711 { "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* xor rd,rs2,rd */ |
|
1712 { "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS, v6 }, /* xor rd,i,rd */ |
|
1713 |
|
1714 /* FPop1 and FPop2 are not instructions. Don't accept them. */ |
|
1715 |
|
1716 { "fdtoi", F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, v6 }, |
|
1717 { "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, v6 }, |
|
1718 { "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, v8 }, |
|
1719 |
|
1720 { "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,H", F_FLOAT, v9 }, |
|
1721 { "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,H", F_FLOAT, v9 }, |
|
1722 { "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,H", F_FLOAT, v9 }, |
|
1723 |
|
1724 { "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, v6 }, |
|
1725 { "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, v6 }, |
|
1726 { "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, v8 }, |
|
1727 |
|
1728 { "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "B,H", F_FLOAT, v9 }, |
|
1729 { "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "B,g", F_FLOAT, v9 }, |
|
1730 { "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "B,J", F_FLOAT, v9 }, |
|
1731 |
|
1732 { "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, v8 }, |
|
1733 { "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, v6 }, |
|
1734 { "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, v8 }, |
|
1735 { "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, v8 }, |
|
1736 { "fstod", F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, v6 }, |
|
1737 { "fstoq", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, v8 }, |
|
1738 |
|
1739 { "fdivd", F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, v6 }, |
|
1740 { "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, v8 }, |
|
1741 { "fdivx", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, v8 }, |
|
1742 { "fdivs", F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, v6 }, |
|
1743 { "fmuld", F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, v6 }, |
|
1744 { "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, v8 }, |
|
1745 { "fmulx", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, v8 }, |
|
1746 { "fmuls", F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, v6 }, |
|
1747 |
|
1748 { "fdmulq", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, v8 }, |
|
1749 { "fdmulx", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, v8 }, |
|
1750 { "fsmuld", F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, v8 }, |
|
1751 |
|
1752 { "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, v7 }, |
|
1753 { "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, v8 }, |
|
1754 { "fsqrtx", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v8 }, |
|
1755 { "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, v7 }, |
|
1756 |
|
1757 { "fabsd", F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, v9 }, |
|
1758 { "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, v9 }, |
|
1759 { "fabsx", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, |
|
1760 { "fabss", F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, v6 }, |
|
1761 { "fmovd", F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, v9 }, |
|
1762 { "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, v9 }, |
|
1763 { "fmovx", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, |
|
1764 { "fmovs", F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, v6 }, |
|
1765 { "fnegd", F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, v9 }, |
|
1766 { "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, v9 }, |
|
1767 { "fnegx", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 }, |
|
1768 { "fnegs", F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, v6 }, |
|
1769 |
|
1770 { "faddd", F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, v6 }, |
|
1771 { "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, v8 }, |
|
1772 { "faddx", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, v8 }, |
|
1773 { "fadds", F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, v6 }, |
|
1774 { "fsubd", F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, v6 }, |
|
1775 { "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, v8 }, |
|
1776 { "fsubx", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, v8 }, |
|
1777 { "fsubs", F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, v6 }, |
|
1778 |
|
1779 #define CMPFCC(x) (((x)&0x3)<<25) |
|
1780 |
|
1781 { "fcmpd", F3F(2, 0x35, 0x052), F3F(~2, ~0x35, ~0x052)|RD_G0, "v,B", F_FLOAT, v6 }, |
|
1782 { "fcmpd", CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052), "6,v,B", F_FLOAT, v9 }, |
|
1783 { "fcmpd", CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052), "7,v,B", F_FLOAT, v9 }, |
|
1784 { "fcmpd", CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052), "8,v,B", F_FLOAT, v9 }, |
|
1785 { "fcmpd", CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052), "9,v,B", F_FLOAT, v9 }, |
|
1786 { "fcmped", F3F(2, 0x35, 0x056), F3F(~2, ~0x35, ~0x056)|RD_G0, "v,B", F_FLOAT, v6 }, |
|
1787 { "fcmped", CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056), "6,v,B", F_FLOAT, v9 }, |
|
1788 { "fcmped", CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056), "7,v,B", F_FLOAT, v9 }, |
|
1789 { "fcmped", CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056), "8,v,B", F_FLOAT, v9 }, |
|
1790 { "fcmped", CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056), "9,v,B", F_FLOAT, v9 }, |
|
1791 { "fcmpq", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT, v8 }, |
|
1792 { "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT, v9 }, |
|
1793 { "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT, v9 }, |
|
1794 { "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT, v9 }, |
|
1795 { "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT, v9 }, |
|
1796 { "fcmpeq", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT, v8 }, |
|
1797 { "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT, v9 }, |
|
1798 { "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT, v9 }, |
|
1799 { "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT, v9 }, |
|
1800 { "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT, v9 }, |
|
1801 { "fcmpx", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 }, |
|
1802 { "fcmpx", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT|F_ALIAS, v9 }, |
|
1803 { "fcmpx", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT|F_ALIAS, v9 }, |
|
1804 { "fcmpx", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT|F_ALIAS, v9 }, |
|
1805 { "fcmpx", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT|F_ALIAS, v9 }, |
|
1806 { "fcmpex", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 }, |
|
1807 { "fcmpex", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT|F_ALIAS, v9 }, |
|
1808 { "fcmpex", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT|F_ALIAS, v9 }, |
|
1809 { "fcmpex", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT|F_ALIAS, v9 }, |
|
1810 { "fcmpex", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT|F_ALIAS, v9 }, |
|
1811 { "fcmps", F3F(2, 0x35, 0x051), F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f", F_FLOAT, v6 }, |
|
1812 { "fcmps", CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051), "6,e,f", F_FLOAT, v9 }, |
|
1813 { "fcmps", CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051), "7,e,f", F_FLOAT, v9 }, |
|
1814 { "fcmps", CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051), "8,e,f", F_FLOAT, v9 }, |
|
1815 { "fcmps", CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051), "9,e,f", F_FLOAT, v9 }, |
|
1816 { "fcmpes", F3F(2, 0x35, 0x055), F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f", F_FLOAT, v6 }, |
|
1817 { "fcmpes", CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055), "6,e,f", F_FLOAT, v9 }, |
|
1818 { "fcmpes", CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055), "7,e,f", F_FLOAT, v9 }, |
|
1819 { "fcmpes", CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055), "8,e,f", F_FLOAT, v9 }, |
|
1820 { "fcmpes", CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055), "9,e,f", F_FLOAT, v9 }, |
|
1821 |
|
1822 /* These Extended FPop (FIFO) instructions are new in the Fujitsu |
|
1823 MB86934, replacing the CPop instructions from v6 and later |
|
1824 processors. */ |
|
1825 |
|
1826 #define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, sparclite } |
|
1827 #define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op), args, 0, sparclite } |
|
1828 #define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0, args, 0, sparclite } |
|
1829 |
|
1830 EFPOP1_2 ("efitod", 0x0c8, "f,H"), |
|
1831 EFPOP1_2 ("efitos", 0x0c4, "f,g"), |
|
1832 EFPOP1_2 ("efdtoi", 0x0d2, "B,g"), |
|
1833 EFPOP1_2 ("efstoi", 0x0d1, "f,g"), |
|
1834 EFPOP1_2 ("efstod", 0x0c9, "f,H"), |
|
1835 EFPOP1_2 ("efdtos", 0x0c6, "B,g"), |
|
1836 EFPOP1_2 ("efmovs", 0x001, "f,g"), |
|
1837 EFPOP1_2 ("efnegs", 0x005, "f,g"), |
|
1838 EFPOP1_2 ("efabss", 0x009, "f,g"), |
|
1839 EFPOP1_2 ("efsqrtd", 0x02a, "B,H"), |
|
1840 EFPOP1_2 ("efsqrts", 0x029, "f,g"), |
|
1841 EFPOP1_3 ("efaddd", 0x042, "v,B,H"), |
|
1842 EFPOP1_3 ("efadds", 0x041, "e,f,g"), |
|
1843 EFPOP1_3 ("efsubd", 0x046, "v,B,H"), |
|
1844 EFPOP1_3 ("efsubs", 0x045, "e,f,g"), |
|
1845 EFPOP1_3 ("efdivd", 0x04e, "v,B,H"), |
|
1846 EFPOP1_3 ("efdivs", 0x04d, "e,f,g"), |
|
1847 EFPOP1_3 ("efmuld", 0x04a, "v,B,H"), |
|
1848 EFPOP1_3 ("efmuls", 0x049, "e,f,g"), |
|
1849 EFPOP1_3 ("efsmuld", 0x069, "e,f,H"), |
|
1850 EFPOP2_2 ("efcmpd", 0x052, "v,B"), |
|
1851 EFPOP2_2 ("efcmped", 0x056, "v,B"), |
|
1852 EFPOP2_2 ("efcmps", 0x051, "e,f"), |
|
1853 EFPOP2_2 ("efcmpes", 0x055, "e,f"), |
|
1854 |
|
1855 #undef EFPOP1_2 |
|
1856 #undef EFPOP1_3 |
|
1857 #undef EFPOP2_2 |
|
1858 |
|
1859 /* These are marked F_ALIAS, so that they won't conflict with sparclite insns |
|
1860 present. Otherwise, the F_ALIAS flag is ignored. */ |
|
1861 { "cpop1", F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, v6notv9 }, |
|
1862 { "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, v6notv9 }, |
|
1863 |
|
1864 /* sparclet specific insns */ |
|
1865 |
|
1866 COMMUTEOP ("umac", 0x3e, sparclet), |
|
1867 COMMUTEOP ("smac", 0x3f, sparclet), |
|
1868 COMMUTEOP ("umacd", 0x2e, sparclet), |
|
1869 COMMUTEOP ("smacd", 0x2f, sparclet), |
|
1870 COMMUTEOP ("umuld", 0x09, sparclet), |
|
1871 COMMUTEOP ("smuld", 0x0d, sparclet), |
|
1872 |
|
1873 { "shuffle", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, sparclet }, |
|
1874 { "shuffle", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, sparclet }, |
|
1875 |
|
1876 /* The manual isn't completely accurate on these insns. The `rs2' field is |
|
1877 treated as being 6 bits to account for 6 bit immediates to cpush. It is |
|
1878 assumed that it is intended that bit 5 is 0 when rs2 contains a reg. */ |
|
1879 #define BIT5 (1<<5) |
|
1880 { "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, sparclet }, |
|
1881 { "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, sparclet }, |
|
1882 { "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, sparclet }, |
|
1883 { "cpush", F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0), "1,Y", 0, sparclet }, |
|
1884 { "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, sparclet }, |
|
1885 { "cpusha", F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0), "1,Y", 0, sparclet }, |
|
1886 { "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, sparclet }, |
|
1887 #undef BIT5 |
|
1888 |
|
1889 /* sparclet coprocessor branch insns */ |
|
1890 #define SLCBCC2(opcode, mask, lose) \ |
|
1891 { opcode, (mask), ANNUL|(lose), "l", F_DELAYED|F_CONDBR, sparclet }, \ |
|
1892 { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, sparclet } |
|
1893 #define SLCBCC(opcode, mask) \ |
|
1894 SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask))) |
|
1895 |
|
1896 /* cbn,cba can't be defined here because they're defined elsewhere and GAS |
|
1897 requires all mnemonics of the same name to be consecutive. */ |
|
1898 /*SLCBCC("cbn", 0), - already defined */ |
|
1899 SLCBCC("cbe", 1), |
|
1900 SLCBCC("cbf", 2), |
|
1901 SLCBCC("cbef", 3), |
|
1902 SLCBCC("cbr", 4), |
|
1903 SLCBCC("cber", 5), |
|
1904 SLCBCC("cbfr", 6), |
|
1905 SLCBCC("cbefr", 7), |
|
1906 /*SLCBCC("cba", 8), - already defined */ |
|
1907 SLCBCC("cbne", 9), |
|
1908 SLCBCC("cbnf", 10), |
|
1909 SLCBCC("cbnef", 11), |
|
1910 SLCBCC("cbnr", 12), |
|
1911 SLCBCC("cbner", 13), |
|
1912 SLCBCC("cbnfr", 14), |
|
1913 SLCBCC("cbnefr", 15), |
|
1914 |
|
1915 #undef SLCBCC2 |
|
1916 #undef SLCBCC |
|
1917 |
|
1918 { "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, v9 }, |
|
1919 { "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, v9 }, |
|
1920 { "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, v9 }, |
|
1921 { "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, v9 }, |
|
1922 |
|
1923 /* v9 synthetic insns */ |
|
1924 { "iprefetch", F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, v9 }, /* bn,a,pt %xcc,label */ |
|
1925 { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* sra rs1,%g0,rd */ |
|
1926 { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* sra rd,%g0,rd */ |
|
1927 { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* srl rs1,%g0,rd */ |
|
1928 { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* srl rd,%g0,rd */ |
|
1929 { "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P,rs2,rd */ |
|
1930 { "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */ |
|
1931 { "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */ |
|
1932 { "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */ |
|
1933 |
|
1934 /* Ultrasparc extensions */ |
|
1935 { "shutdown", F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, v9a }, |
|
1936 |
|
1937 /* FIXME: Do we want to mark these as F_FLOAT, or something similar? */ |
|
1938 { "fpadd16", F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, v9a }, |
|
1939 { "fpadd16s", F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, v9a }, |
|
1940 { "fpadd32", F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, v9a }, |
|
1941 { "fpadd32s", F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, v9a }, |
|
1942 { "fpsub16", F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, v9a }, |
|
1943 { "fpsub16s", F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, v9a }, |
|
1944 { "fpsub32", F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, v9a }, |
|
1945 { "fpsub32s", F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, v9a }, |
|
1946 |
|
1947 { "fpack32", F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, v9a }, |
|
1948 { "fpack16", F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, v9a }, |
|
1949 { "fpackfix", F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, v9a }, |
|
1950 { "fexpand", F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, v9a }, |
|
1951 { "fpmerge", F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, v9a }, |
|
1952 |
|
1953 /* Note that the mixing of 32/64 bit regs is intentional. */ |
|
1954 { "fmul8x16", F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, v9a }, |
|
1955 { "fmul8x16au", F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, v9a }, |
|
1956 { "fmul8x16al", F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, v9a }, |
|
1957 { "fmul8sux16", F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, v9a }, |
|
1958 { "fmul8ulx16", F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, v9a }, |
|
1959 { "fmuld8sux16", F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, v9a }, |
|
1960 { "fmuld8ulx16", F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, v9a }, |
|
1961 |
|
1962 { "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, v9a }, |
|
1963 { "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, v9a }, |
|
1964 { "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, v9a }, |
|
1965 |
|
1966 { "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, v9a }, |
|
1967 { "fzeros", F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, v9a }, |
|
1968 { "fone", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, v9a }, |
|
1969 { "fones", F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, v9a }, |
|
1970 { "fsrc1", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, v9a }, |
|
1971 { "fsrc1s", F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, v9a }, |
|
1972 { "fsrc2", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, v9a }, |
|
1973 { "fsrc2s", F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, v9a }, |
|
1974 { "fnot1", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, v9a }, |
|
1975 { "fnot1s", F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, v9a }, |
|
1976 { "fnot2", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, v9a }, |
|
1977 { "fnot2s", F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, v9a }, |
|
1978 { "for", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, v9a }, |
|
1979 { "fors", F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, v9a }, |
|
1980 { "fnor", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, v9a }, |
|
1981 { "fnors", F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, v9a }, |
|
1982 { "fand", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, v9a }, |
|
1983 { "fands", F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, v9a }, |
|
1984 { "fnand", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, v9a }, |
|
1985 { "fnands", F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, v9a }, |
|
1986 { "fxor", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, v9a }, |
|
1987 { "fxors", F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, v9a }, |
|
1988 { "fxnor", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, v9a }, |
|
1989 { "fxnors", F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, v9a }, |
|
1990 { "fornot1", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, v9a }, |
|
1991 { "fornot1s", F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, v9a }, |
|
1992 { "fornot2", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, v9a }, |
|
1993 { "fornot2s", F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, v9a }, |
|
1994 { "fandnot1", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, v9a }, |
|
1995 { "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, v9a }, |
|
1996 { "fandnot2", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, v9a }, |
|
1997 { "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, v9a }, |
|
1998 |
|
1999 { "fcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, v9a }, |
|
2000 { "fcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, v9a }, |
|
2001 { "fcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, v9a }, |
|
2002 { "fcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, v9a }, |
|
2003 { "fcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, v9a }, |
|
2004 { "fcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, v9a }, |
|
2005 { "fcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, v9a }, |
|
2006 { "fcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, v9a }, |
|
2007 |
|
2008 { "edge8", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, v9a }, |
|
2009 { "edge8l", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, v9a }, |
|
2010 { "edge16", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, v9a }, |
|
2011 { "edge16l", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, v9a }, |
|
2012 { "edge32", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, v9a }, |
|
2013 { "edge32l", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, v9a }, |
|
2014 |
|
2015 { "pdist", F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, v9a }, |
|
2016 |
|
2017 { "array8", F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, v9a }, |
|
2018 { "array16", F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, v9a }, |
|
2019 { "array32", F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, v9a }, |
|
2020 |
|
2021 /* Cheetah instructions */ |
|
2022 { "edge8n", F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", 0, v9b }, |
|
2023 { "edge8ln", F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", 0, v9b }, |
|
2024 { "edge16n", F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", 0, v9b }, |
|
2025 { "edge16ln", F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", 0, v9b }, |
|
2026 { "edge32n", F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", 0, v9b }, |
|
2027 { "edge32ln", F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", 0, v9b }, |
|
2028 |
|
2029 { "bmask", F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", 0, v9b }, |
|
2030 { "bshuffle", F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", 0, v9b }, |
|
2031 |
|
2032 { "siam", F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", 0, v9b }, |
|
2033 |
|
2034 /* More v9 specific insns, these need to come last so they do not clash |
|
2035 with v9a instructions such as "edge8" which looks like impdep1. */ |
|
2036 |
|
2037 #define IMPDEP(name, code) \ |
|
2038 { name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, v9notv9a }, \ |
|
2039 { name, F3(2, code, 1), F3(~2, ~code, ~1), "1,i,d", 0, v9notv9a }, \ |
|
2040 { name, F3(2, code, 0), F3(~2, ~code, ~0), "x,1,2,d", 0, v9notv9a }, \ |
|
2041 { name, F3(2, code, 0), F3(~2, ~code, ~0), "x,e,f,g", 0, v9notv9a } |
|
2042 |
|
2043 IMPDEP ("impdep1", 0x36), |
|
2044 IMPDEP ("impdep2", 0x37), |
|
2045 |
|
2046 #undef IMPDEP |
|
2047 |
|
2048 }; |
|
2049 |
|
2050 static const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0])); |
|
2051 |
|
2052 /* Utilities for argument parsing. */ |
|
2053 |
|
2054 typedef struct |
|
2055 { |
|
2056 int value; |
|
2057 const char *name; |
|
2058 } arg; |
|
2059 |
|
2060 /* Look up VALUE in TABLE. */ |
|
2061 |
|
2062 static const char * |
|
2063 lookup_value (const arg *table, int value) |
|
2064 { |
|
2065 const arg *p; |
|
2066 |
|
2067 for (p = table; p->name; ++p) |
|
2068 if (value == p->value) |
|
2069 return p->name; |
|
2070 |
|
2071 return NULL; |
|
2072 } |
|
2073 |
|
2074 /* Handle ASI's. */ |
|
2075 |
|
2076 static const arg asi_table_v8[] = |
|
2077 { |
|
2078 { 0x00, "#ASI_M_RES00" }, |
|
2079 { 0x01, "#ASI_M_UNA01" }, |
|
2080 { 0x02, "#ASI_M_MXCC" }, |
|
2081 { 0x03, "#ASI_M_FLUSH_PROBE" }, |
|
2082 { 0x04, "#ASI_M_MMUREGS" }, |
|
2083 { 0x05, "#ASI_M_TLBDIAG" }, |
|
2084 { 0x06, "#ASI_M_DIAGS" }, |
|
2085 { 0x07, "#ASI_M_IODIAG" }, |
|
2086 { 0x08, "#ASI_M_USERTXT" }, |
|
2087 { 0x09, "#ASI_M_KERNELTXT" }, |
|
2088 { 0x0A, "#ASI_M_USERDATA" }, |
|
2089 { 0x0B, "#ASI_M_KERNELDATA" }, |
|
2090 { 0x0C, "#ASI_M_TXTC_TAG" }, |
|
2091 { 0x0D, "#ASI_M_TXTC_DATA" }, |
|
2092 { 0x0E, "#ASI_M_DATAC_TAG" }, |
|
2093 { 0x0F, "#ASI_M_DATAC_DATA" }, |
|
2094 { 0x10, "#ASI_M_FLUSH_PAGE" }, |
|
2095 { 0x11, "#ASI_M_FLUSH_SEG" }, |
|
2096 { 0x12, "#ASI_M_FLUSH_REGION" }, |
|
2097 { 0x13, "#ASI_M_FLUSH_CTX" }, |
|
2098 { 0x14, "#ASI_M_FLUSH_USER" }, |
|
2099 { 0x17, "#ASI_M_BCOPY" }, |
|
2100 { 0x18, "#ASI_M_IFLUSH_PAGE" }, |
|
2101 { 0x19, "#ASI_M_IFLUSH_SEG" }, |
|
2102 { 0x1A, "#ASI_M_IFLUSH_REGION" }, |
|
2103 { 0x1B, "#ASI_M_IFLUSH_CTX" }, |
|
2104 { 0x1C, "#ASI_M_IFLUSH_USER" }, |
|
2105 { 0x1F, "#ASI_M_BFILL" }, |
|
2106 { 0x20, "#ASI_M_BYPASS" }, |
|
2107 { 0x29, "#ASI_M_FBMEM" }, |
|
2108 { 0x2A, "#ASI_M_VMEUS" }, |
|
2109 { 0x2B, "#ASI_M_VMEPS" }, |
|
2110 { 0x2C, "#ASI_M_VMEUT" }, |
|
2111 { 0x2D, "#ASI_M_VMEPT" }, |
|
2112 { 0x2E, "#ASI_M_SBUS" }, |
|
2113 { 0x2F, "#ASI_M_CTL" }, |
|
2114 { 0x31, "#ASI_M_FLUSH_IWHOLE" }, |
|
2115 { 0x36, "#ASI_M_IC_FLCLEAR" }, |
|
2116 { 0x37, "#ASI_M_DC_FLCLEAR" }, |
|
2117 { 0x39, "#ASI_M_DCDR" }, |
|
2118 { 0x40, "#ASI_M_VIKING_TMP1" }, |
|
2119 { 0x41, "#ASI_M_VIKING_TMP2" }, |
|
2120 { 0x4c, "#ASI_M_ACTION" }, |
|
2121 { 0, 0 } |
|
2122 }; |
|
2123 |
|
2124 static const arg asi_table_v9[] = |
|
2125 { |
|
2126 /* These are in the v9 architecture manual. */ |
|
2127 /* The shorter versions appear first, they're here because Sun's as has them. |
|
2128 Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the |
|
2129 UltraSPARC architecture manual). */ |
|
2130 { 0x04, "#ASI_N" }, |
|
2131 { 0x0c, "#ASI_N_L" }, |
|
2132 { 0x10, "#ASI_AIUP" }, |
|
2133 { 0x11, "#ASI_AIUS" }, |
|
2134 { 0x18, "#ASI_AIUP_L" }, |
|
2135 { 0x19, "#ASI_AIUS_L" }, |
|
2136 { 0x80, "#ASI_P" }, |
|
2137 { 0x81, "#ASI_S" }, |
|
2138 { 0x82, "#ASI_PNF" }, |
|
2139 { 0x83, "#ASI_SNF" }, |
|
2140 { 0x88, "#ASI_P_L" }, |
|
2141 { 0x89, "#ASI_S_L" }, |
|
2142 { 0x8a, "#ASI_PNF_L" }, |
|
2143 { 0x8b, "#ASI_SNF_L" }, |
|
2144 { 0x04, "#ASI_NUCLEUS" }, |
|
2145 { 0x0c, "#ASI_NUCLEUS_LITTLE" }, |
|
2146 { 0x10, "#ASI_AS_IF_USER_PRIMARY" }, |
|
2147 { 0x11, "#ASI_AS_IF_USER_SECONDARY" }, |
|
2148 { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE" }, |
|
2149 { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE" }, |
|
2150 { 0x80, "#ASI_PRIMARY" }, |
|
2151 { 0x81, "#ASI_SECONDARY" }, |
|
2152 { 0x82, "#ASI_PRIMARY_NOFAULT" }, |
|
2153 { 0x83, "#ASI_SECONDARY_NOFAULT" }, |
|
2154 { 0x88, "#ASI_PRIMARY_LITTLE" }, |
|
2155 { 0x89, "#ASI_SECONDARY_LITTLE" }, |
|
2156 { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" }, |
|
2157 { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" }, |
|
2158 /* These are UltraSPARC extensions. */ |
|
2159 /* FIXME: There are dozens of them. Not sure we want them all. |
|
2160 Most are for kernel building but some are for vis type stuff. */ |
|
2161 { 0, 0 } |
|
2162 }; |
|
2163 |
|
2164 /* Return the name for ASI value VALUE or NULL if not found. */ |
|
2165 |
|
2166 static const char * |
|
2167 sparc_decode_asi_v9 (int value) |
|
2168 { |
|
2169 return lookup_value (asi_table_v9, value); |
|
2170 } |
|
2171 |
|
2172 static const char * |
|
2173 sparc_decode_asi_v8 (int value) |
|
2174 { |
|
2175 return lookup_value (asi_table_v8, value); |
|
2176 } |
|
2177 |
|
2178 /* Handle membar masks. */ |
|
2179 |
|
2180 static const arg membar_table[] = |
|
2181 { |
|
2182 { 0x40, "#Sync" }, |
|
2183 { 0x20, "#MemIssue" }, |
|
2184 { 0x10, "#Lookaside" }, |
|
2185 { 0x08, "#StoreStore" }, |
|
2186 { 0x04, "#LoadStore" }, |
|
2187 { 0x02, "#StoreLoad" }, |
|
2188 { 0x01, "#LoadLoad" }, |
|
2189 { 0, 0 } |
|
2190 }; |
|
2191 |
|
2192 /* Return the name for membar value VALUE or NULL if not found. */ |
|
2193 |
|
2194 static const char * |
|
2195 sparc_decode_membar (int value) |
|
2196 { |
|
2197 return lookup_value (membar_table, value); |
|
2198 } |
|
2199 |
|
2200 /* Handle prefetch args. */ |
|
2201 |
|
2202 static const arg prefetch_table[] = |
|
2203 { |
|
2204 { 0, "#n_reads" }, |
|
2205 { 1, "#one_read" }, |
|
2206 { 2, "#n_writes" }, |
|
2207 { 3, "#one_write" }, |
|
2208 { 4, "#page" }, |
|
2209 { 16, "#invalidate" }, |
|
2210 { 0, 0 } |
|
2211 }; |
|
2212 |
|
2213 /* Return the name for prefetch value VALUE or NULL if not found. */ |
|
2214 |
|
2215 static const char * |
|
2216 sparc_decode_prefetch (int value) |
|
2217 { |
|
2218 return lookup_value (prefetch_table, value); |
|
2219 } |
|
2220 |
|
2221 /* Handle sparclet coprocessor registers. */ |
|
2222 |
|
2223 static const arg sparclet_cpreg_table[] = |
|
2224 { |
|
2225 { 0, "%ccsr" }, |
|
2226 { 1, "%ccfr" }, |
|
2227 { 2, "%cccrcr" }, |
|
2228 { 3, "%ccpr" }, |
|
2229 { 4, "%ccsr2" }, |
|
2230 { 5, "%cccrr" }, |
|
2231 { 6, "%ccrstr" }, |
|
2232 { 0, 0 } |
|
2233 }; |
|
2234 |
|
2235 /* Return the name for sparclet cpreg value VALUE or NULL if not found. */ |
|
2236 |
|
2237 static const char * |
|
2238 sparc_decode_sparclet_cpreg (int value) |
|
2239 { |
|
2240 return lookup_value (sparclet_cpreg_table, value); |
|
2241 } |
|
2242 |
|
2243 #undef MASK_V9 |
|
2244 |
|
2245 /* opcodes/sparc-dis.c */ |
|
2246 |
|
2247 /* Print SPARC instructions. |
|
2248 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
|
2249 2000, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. |
|
2250 |
|
2251 This program is free software; you can redistribute it and/or modify |
|
2252 it under the terms of the GNU General Public License as published by |
|
2253 the Free Software Foundation; either version 2 of the License, or |
|
2254 (at your option) any later version. |
|
2255 |
|
2256 This program is distributed in the hope that it will be useful, |
|
2257 but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
2258 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
2259 GNU General Public License for more details. |
|
2260 |
|
2261 You should have received a copy of the GNU General Public License |
|
2262 along with this program; if not, write to the Free Software |
|
2263 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
|
2264 MA 02110-1301, USA. */ |
|
2265 |
|
2266 /* Bitmask of v9 architectures. */ |
|
2267 #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \ |
|
2268 | (1 << SPARC_OPCODE_ARCH_V9A) \ |
|
2269 | (1 << SPARC_OPCODE_ARCH_V9B)) |
|
2270 /* 1 if INSN is for v9 only. */ |
|
2271 #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9)) |
|
2272 /* 1 if INSN is for v9. */ |
|
2273 #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0) |
|
2274 |
|
2275 /* The sorted opcode table. */ |
|
2276 static const sparc_opcode **sorted_opcodes; |
|
2277 |
|
2278 /* For faster lookup, after insns are sorted they are hashed. */ |
|
2279 /* ??? I think there is room for even more improvement. */ |
|
2280 |
|
2281 #define HASH_SIZE 256 |
|
2282 /* It is important that we only look at insn code bits as that is how the |
|
2283 opcode table is hashed. OPCODE_BITS is a table of valid bits for each |
|
2284 of the main types (0,1,2,3). */ |
|
2285 static const int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 }; |
|
2286 #define HASH_INSN(INSN) \ |
|
2287 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19)) |
|
2288 typedef struct sparc_opcode_hash |
|
2289 { |
|
2290 struct sparc_opcode_hash *next; |
|
2291 const sparc_opcode *opcode; |
|
2292 } sparc_opcode_hash; |
|
2293 |
|
2294 static sparc_opcode_hash *opcode_hash_table[HASH_SIZE]; |
|
2295 |
|
2296 /* Sign-extend a value which is N bits long. */ |
|
2297 #define SEX(value, bits) \ |
|
2298 ((((int)(value)) << ((8 * sizeof (int)) - bits)) \ |
|
2299 >> ((8 * sizeof (int)) - bits) ) |
|
2300 |
|
2301 static const char * const reg_names[] = |
|
2302 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
|
2303 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", |
|
2304 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", |
|
2305 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", |
|
2306 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
|
2307 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
|
2308 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
|
2309 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
|
2310 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", |
|
2311 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", |
|
2312 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55", |
|
2313 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63", |
|
2314 /* psr, wim, tbr, fpsr, cpsr are v8 only. */ |
|
2315 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr" |
|
2316 }; |
|
2317 |
|
2318 #define freg_names (®_names[4 * 8]) |
|
2319 |
|
2320 /* These are ordered according to there register number in |
|
2321 rdpr and wrpr insns. */ |
|
2322 static const char * const v9_priv_reg_names[] = |
|
2323 { |
|
2324 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl", |
|
2325 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", |
|
2326 "wstate", "fq", "gl" |
|
2327 /* "ver" - special cased */ |
|
2328 }; |
|
2329 |
|
2330 /* These are ordered according to there register number in |
|
2331 rdhpr and wrhpr insns. */ |
|
2332 static const char * const v9_hpriv_reg_names[] = |
|
2333 { |
|
2334 "hpstate", "htstate", "resv2", "hintp", "resv4", "htba", "hver", |
|
2335 "resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13", |
|
2336 "resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20", |
|
2337 "resv21", "resv22", "resv23", "resv24", "resv25", "resv26", "resv27", |
|
2338 "resv28", "resv29", "resv30", "hstick_cmpr" |
|
2339 }; |
|
2340 |
|
2341 /* These are ordered according to there register number in |
|
2342 rd and wr insns (-16). */ |
|
2343 static const char * const v9a_asr_reg_names[] = |
|
2344 { |
|
2345 "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint", |
|
2346 "softint", "tick_cmpr", "sys_tick", "sys_tick_cmpr" |
|
2347 }; |
|
2348 |
|
2349 /* Macros used to extract instruction fields. Not all fields have |
|
2350 macros defined here, only those which are actually used. */ |
|
2351 |
|
2352 #define X_RD(i) (((i) >> 25) & 0x1f) |
|
2353 #define X_RS1(i) (((i) >> 14) & 0x1f) |
|
2354 #define X_LDST_I(i) (((i) >> 13) & 1) |
|
2355 #define X_ASI(i) (((i) >> 5) & 0xff) |
|
2356 #define X_RS2(i) (((i) >> 0) & 0x1f) |
|
2357 #define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1)) |
|
2358 #define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n)) |
|
2359 #define X_DISP22(i) (((i) >> 0) & 0x3fffff) |
|
2360 #define X_IMM22(i) X_DISP22 (i) |
|
2361 #define X_DISP30(i) (((i) >> 0) & 0x3fffffff) |
|
2362 |
|
2363 /* These are for v9. */ |
|
2364 #define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff)) |
|
2365 #define X_DISP19(i) (((i) >> 0) & 0x7ffff) |
|
2366 #define X_MEMBAR(i) ((i) & 0x7f) |
|
2367 |
|
2368 /* Here is the union which was used to extract instruction fields |
|
2369 before the shift and mask macros were written. |
|
2370 |
|
2371 union sparc_insn |
|
2372 { |
|
2373 unsigned long int code; |
|
2374 struct |
|
2375 { |
|
2376 unsigned int anop:2; |
|
2377 #define op ldst.anop |
|
2378 unsigned int anrd:5; |
|
2379 #define rd ldst.anrd |
|
2380 unsigned int op3:6; |
|
2381 unsigned int anrs1:5; |
|
2382 #define rs1 ldst.anrs1 |
|
2383 unsigned int i:1; |
|
2384 unsigned int anasi:8; |
|
2385 #define asi ldst.anasi |
|
2386 unsigned int anrs2:5; |
|
2387 #define rs2 ldst.anrs2 |
|
2388 #define shcnt rs2 |
|
2389 } ldst; |
|
2390 struct |
|
2391 { |
|
2392 unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1; |
|
2393 unsigned int IMM13:13; |
|
2394 #define imm13 IMM13.IMM13 |
|
2395 } IMM13; |
|
2396 struct |
|
2397 { |
|
2398 unsigned int anop:2; |
|
2399 unsigned int a:1; |
|
2400 unsigned int cond:4; |
|
2401 unsigned int op2:3; |
|
2402 unsigned int DISP22:22; |
|
2403 #define disp22 branch.DISP22 |
|
2404 #define imm22 disp22 |
|
2405 } branch; |
|
2406 struct |
|
2407 { |
|
2408 unsigned int anop:2; |
|
2409 unsigned int a:1; |
|
2410 unsigned int z:1; |
|
2411 unsigned int rcond:3; |
|
2412 unsigned int op2:3; |
|
2413 unsigned int DISP16HI:2; |
|
2414 unsigned int p:1; |
|
2415 unsigned int _rs1:5; |
|
2416 unsigned int DISP16LO:14; |
|
2417 } branch16; |
|
2418 struct |
|
2419 { |
|
2420 unsigned int anop:2; |
|
2421 unsigned int adisp30:30; |
|
2422 #define disp30 call.adisp30 |
|
2423 } call; |
|
2424 }; */ |
|
2425 |
|
2426 /* Nonzero if INSN is the opcode for a delayed branch. */ |
|
2427 |
|
2428 static int |
|
2429 is_delayed_branch (unsigned long insn) |
|
2430 { |
|
2431 sparc_opcode_hash *op; |
|
2432 |
|
2433 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) |
|
2434 { |
|
2435 const sparc_opcode *opcode = op->opcode; |
|
2436 |
|
2437 if ((opcode->match & insn) == opcode->match |
|
2438 && (opcode->lose & insn) == 0) |
|
2439 return opcode->flags & F_DELAYED; |
|
2440 } |
|
2441 return 0; |
|
2442 } |
|
2443 |
|
2444 /* extern void qsort (); */ |
|
2445 |
|
2446 /* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value |
|
2447 to compare_opcodes. */ |
|
2448 static unsigned int current_arch_mask; |
|
2449 |
|
2450 /* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */ |
|
2451 |
|
2452 static int |
|
2453 compute_arch_mask (unsigned long mach) |
|
2454 { |
|
2455 switch (mach) |
|
2456 { |
|
2457 case 0 : |
|
2458 case bfd_mach_sparc : |
|
2459 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8); |
|
2460 case bfd_mach_sparc_sparclet : |
|
2461 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET); |
|
2462 case bfd_mach_sparc_sparclite : |
|
2463 case bfd_mach_sparc_sparclite_le : |
|
2464 /* sparclites insns are recognized by default (because that's how |
|
2465 they've always been treated, for better or worse). Kludge this by |
|
2466 indicating generic v8 is also selected. */ |
|
2467 return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) |
|
2468 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)); |
|
2469 case bfd_mach_sparc_v8plus : |
|
2470 case bfd_mach_sparc_v9 : |
|
2471 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); |
|
2472 case bfd_mach_sparc_v8plusa : |
|
2473 case bfd_mach_sparc_v9a : |
|
2474 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A); |
|
2475 case bfd_mach_sparc_v8plusb : |
|
2476 case bfd_mach_sparc_v9b : |
|
2477 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B); |
|
2478 } |
|
2479 abort (); |
|
2480 } |
|
2481 |
|
2482 /* Compare opcodes A and B. */ |
|
2483 |
|
2484 static int |
|
2485 compare_opcodes (const void * a, const void * b) |
|
2486 { |
|
2487 sparc_opcode *op0 = * (sparc_opcode **) a; |
|
2488 sparc_opcode *op1 = * (sparc_opcode **) b; |
|
2489 unsigned long int match0 = op0->match, match1 = op1->match; |
|
2490 unsigned long int lose0 = op0->lose, lose1 = op1->lose; |
|
2491 register unsigned int i; |
|
2492 |
|
2493 /* If one (and only one) insn isn't supported by the current architecture, |
|
2494 prefer the one that is. If neither are supported, but they're both for |
|
2495 the same architecture, continue processing. Otherwise (both unsupported |
|
2496 and for different architectures), prefer lower numbered arch's (fudged |
|
2497 by comparing the bitmasks). */ |
|
2498 if (op0->architecture & current_arch_mask) |
|
2499 { |
|
2500 if (! (op1->architecture & current_arch_mask)) |
|
2501 return -1; |
|
2502 } |
|
2503 else |
|
2504 { |
|
2505 if (op1->architecture & current_arch_mask) |
|
2506 return 1; |
|
2507 else if (op0->architecture != op1->architecture) |
|
2508 return op0->architecture - op1->architecture; |
|
2509 } |
|
2510 |
|
2511 /* If a bit is set in both match and lose, there is something |
|
2512 wrong with the opcode table. */ |
|
2513 if (match0 & lose0) |
|
2514 { |
|
2515 fprintf |
|
2516 (stderr, |
|
2517 /* xgettext:c-format */ |
|
2518 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), |
|
2519 op0->name, match0, lose0); |
|
2520 op0->lose &= ~op0->match; |
|
2521 lose0 = op0->lose; |
|
2522 } |
|
2523 |
|
2524 if (match1 & lose1) |
|
2525 { |
|
2526 fprintf |
|
2527 (stderr, |
|
2528 /* xgettext:c-format */ |
|
2529 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"), |
|
2530 op1->name, match1, lose1); |
|
2531 op1->lose &= ~op1->match; |
|
2532 lose1 = op1->lose; |
|
2533 } |
|
2534 |
|
2535 /* Because the bits that are variable in one opcode are constant in |
|
2536 another, it is important to order the opcodes in the right order. */ |
|
2537 for (i = 0; i < 32; ++i) |
|
2538 { |
|
2539 unsigned long int x = 1 << i; |
|
2540 int x0 = (match0 & x) != 0; |
|
2541 int x1 = (match1 & x) != 0; |
|
2542 |
|
2543 if (x0 != x1) |
|
2544 return x1 - x0; |
|
2545 } |
|
2546 |
|
2547 for (i = 0; i < 32; ++i) |
|
2548 { |
|
2549 unsigned long int x = 1 << i; |
|
2550 int x0 = (lose0 & x) != 0; |
|
2551 int x1 = (lose1 & x) != 0; |
|
2552 |
|
2553 if (x0 != x1) |
|
2554 return x1 - x0; |
|
2555 } |
|
2556 |
|
2557 /* They are functionally equal. So as long as the opcode table is |
|
2558 valid, we can put whichever one first we want, on aesthetic grounds. */ |
|
2559 |
|
2560 /* Our first aesthetic ground is that aliases defer to real insns. */ |
|
2561 { |
|
2562 int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS); |
|
2563 |
|
2564 if (alias_diff != 0) |
|
2565 /* Put the one that isn't an alias first. */ |
|
2566 return alias_diff; |
|
2567 } |
|
2568 |
|
2569 /* Except for aliases, two "identical" instructions had |
|
2570 better have the same opcode. This is a sanity check on the table. */ |
|
2571 i = strcmp (op0->name, op1->name); |
|
2572 if (i) |
|
2573 { |
|
2574 if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */ |
|
2575 return i; |
|
2576 else |
|
2577 fprintf (stderr, |
|
2578 /* xgettext:c-format */ |
|
2579 _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"), |
|
2580 op0->name, op1->name); |
|
2581 } |
|
2582 |
|
2583 /* Fewer arguments are preferred. */ |
|
2584 { |
|
2585 int length_diff = strlen (op0->args) - strlen (op1->args); |
|
2586 |
|
2587 if (length_diff != 0) |
|
2588 /* Put the one with fewer arguments first. */ |
|
2589 return length_diff; |
|
2590 } |
|
2591 |
|
2592 /* Put 1+i before i+1. */ |
|
2593 { |
|
2594 char *p0 = (char *) strchr (op0->args, '+'); |
|
2595 char *p1 = (char *) strchr (op1->args, '+'); |
|
2596 |
|
2597 if (p0 && p1) |
|
2598 { |
|
2599 /* There is a plus in both operands. Note that a plus |
|
2600 sign cannot be the first character in args, |
|
2601 so the following [-1]'s are valid. */ |
|
2602 if (p0[-1] == 'i' && p1[1] == 'i') |
|
2603 /* op0 is i+1 and op1 is 1+i, so op1 goes first. */ |
|
2604 return 1; |
|
2605 if (p0[1] == 'i' && p1[-1] == 'i') |
|
2606 /* op0 is 1+i and op1 is i+1, so op0 goes first. */ |
|
2607 return -1; |
|
2608 } |
|
2609 } |
|
2610 |
|
2611 /* Put 1,i before i,1. */ |
|
2612 { |
|
2613 int i0 = strncmp (op0->args, "i,1", 3) == 0; |
|
2614 int i1 = strncmp (op1->args, "i,1", 3) == 0; |
|
2615 |
|
2616 if (i0 ^ i1) |
|
2617 return i0 - i1; |
|
2618 } |
|
2619 |
|
2620 /* They are, as far as we can tell, identical. |
|
2621 Since qsort may have rearranged the table partially, there is |
|
2622 no way to tell which one was first in the opcode table as |
|
2623 written, so just say there are equal. */ |
|
2624 /* ??? This is no longer true now that we sort a vector of pointers, |
|
2625 not the table itself. */ |
|
2626 return 0; |
|
2627 } |
|
2628 |
|
2629 /* Build a hash table from the opcode table. |
|
2630 OPCODE_TABLE is a sorted list of pointers into the opcode table. */ |
|
2631 |
|
2632 static void |
|
2633 build_hash_table (const sparc_opcode **opcode_table, |
|
2634 sparc_opcode_hash **hash_table, |
|
2635 int num_opcodes) |
|
2636 { |
|
2637 int i; |
|
2638 int hash_count[HASH_SIZE]; |
|
2639 static sparc_opcode_hash *hash_buf = NULL; |
|
2640 |
|
2641 /* Start at the end of the table and work backwards so that each |
|
2642 chain is sorted. */ |
|
2643 |
|
2644 memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0])); |
|
2645 memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0])); |
|
2646 if (hash_buf != NULL) |
|
2647 free (hash_buf); |
|
2648 hash_buf = malloc (sizeof (* hash_buf) * num_opcodes); |
|
2649 for (i = num_opcodes - 1; i >= 0; --i) |
|
2650 { |
|
2651 int hash = HASH_INSN (opcode_table[i]->match); |
|
2652 sparc_opcode_hash *h = &hash_buf[i]; |
|
2653 |
|
2654 h->next = hash_table[hash]; |
|
2655 h->opcode = opcode_table[i]; |
|
2656 hash_table[hash] = h; |
|
2657 ++hash_count[hash]; |
|
2658 } |
|
2659 |
|
2660 #if 0 /* for debugging */ |
|
2661 { |
|
2662 int min_count = num_opcodes, max_count = 0; |
|
2663 int total; |
|
2664 |
|
2665 for (i = 0; i < HASH_SIZE; ++i) |
|
2666 { |
|
2667 if (hash_count[i] < min_count) |
|
2668 min_count = hash_count[i]; |
|
2669 if (hash_count[i] > max_count) |
|
2670 max_count = hash_count[i]; |
|
2671 total += hash_count[i]; |
|
2672 } |
|
2673 |
|
2674 printf ("Opcode hash table stats: min %d, max %d, ave %f\n", |
|
2675 min_count, max_count, (double) total / HASH_SIZE); |
|
2676 } |
|
2677 #endif |
|
2678 } |
|
2679 |
|
2680 /* Print one instruction from MEMADDR on INFO->STREAM. |
|
2681 |
|
2682 We suffix the instruction with a comment that gives the absolute |
|
2683 address involved, as well as its symbolic form, if the instruction |
|
2684 is preceded by a findable `sethi' and it either adds an immediate |
|
2685 displacement to that register, or it is an `add' or `or' instruction |
|
2686 on that register. */ |
|
2687 |
|
2688 int |
|
2689 print_insn_sparc (bfd_vma memaddr, disassemble_info *info) |
|
2690 { |
|
2691 FILE *stream = info->stream; |
|
2692 bfd_byte buffer[4]; |
|
2693 unsigned long insn; |
|
2694 sparc_opcode_hash *op; |
|
2695 /* Nonzero of opcode table has been initialized. */ |
|
2696 static int opcodes_initialized = 0; |
|
2697 /* bfd mach number of last call. */ |
|
2698 static unsigned long current_mach = 0; |
|
2699 bfd_vma (*getword) (const unsigned char *); |
|
2700 |
|
2701 if (!opcodes_initialized |
|
2702 || info->mach != current_mach) |
|
2703 { |
|
2704 int i; |
|
2705 |
|
2706 current_arch_mask = compute_arch_mask (info->mach); |
|
2707 |
|
2708 if (!opcodes_initialized) |
|
2709 sorted_opcodes = |
|
2710 malloc (sparc_num_opcodes * sizeof (sparc_opcode *)); |
|
2711 /* Reset the sorted table so we can resort it. */ |
|
2712 for (i = 0; i < sparc_num_opcodes; ++i) |
|
2713 sorted_opcodes[i] = &sparc_opcodes[i]; |
|
2714 qsort ((char *) sorted_opcodes, sparc_num_opcodes, |
|
2715 sizeof (sorted_opcodes[0]), compare_opcodes); |
|
2716 |
|
2717 build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes); |
|
2718 current_mach = info->mach; |
|
2719 opcodes_initialized = 1; |
|
2720 } |
|
2721 |
|
2722 { |
|
2723 int status = |
|
2724 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info); |
|
2725 |
|
2726 if (status != 0) |
|
2727 { |
|
2728 (*info->memory_error_func) (status, memaddr, info); |
|
2729 return -1; |
|
2730 } |
|
2731 } |
|
2732 |
|
2733 /* On SPARClite variants such as DANlite (sparc86x), instructions |
|
2734 are always big-endian even when the machine is in little-endian mode. */ |
|
2735 if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite) |
|
2736 getword = bfd_getb32; |
|
2737 else |
|
2738 getword = bfd_getl32; |
|
2739 |
|
2740 insn = getword (buffer); |
|
2741 |
|
2742 info->insn_info_valid = 1; /* We do return this info. */ |
|
2743 info->insn_type = dis_nonbranch; /* Assume non branch insn. */ |
|
2744 info->branch_delay_insns = 0; /* Assume no delay. */ |
|
2745 info->target = 0; /* Assume no target known. */ |
|
2746 |
|
2747 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) |
|
2748 { |
|
2749 const sparc_opcode *opcode = op->opcode; |
|
2750 |
|
2751 /* If the insn isn't supported by the current architecture, skip it. */ |
|
2752 if (! (opcode->architecture & current_arch_mask)) |
|
2753 continue; |
|
2754 |
|
2755 if ((opcode->match & insn) == opcode->match |
|
2756 && (opcode->lose & insn) == 0) |
|
2757 { |
|
2758 /* Nonzero means that we have found an instruction which has |
|
2759 the effect of adding or or'ing the imm13 field to rs1. */ |
|
2760 int imm_added_to_rs1 = 0; |
|
2761 int imm_ored_to_rs1 = 0; |
|
2762 |
|
2763 /* Nonzero means that we have found a plus sign in the args |
|
2764 field of the opcode table. */ |
|
2765 int found_plus = 0; |
|
2766 |
|
2767 /* Nonzero means we have an annulled branch. */ |
|
2768 int is_annulled = 0; |
|
2769 |
|
2770 /* Do we have an `add' or `or' instruction combining an |
|
2771 immediate with rs1? */ |
|
2772 if (opcode->match == 0x80102000) /* or */ |
|
2773 imm_ored_to_rs1 = 1; |
|
2774 if (opcode->match == 0x80002000) /* add */ |
|
2775 imm_added_to_rs1 = 1; |
|
2776 |
|
2777 if (X_RS1 (insn) != X_RD (insn) |
|
2778 && strchr (opcode->args, 'r') != 0) |
|
2779 /* Can't do simple format if source and dest are different. */ |
|
2780 continue; |
|
2781 if (X_RS2 (insn) != X_RD (insn) |
|
2782 && strchr (opcode->args, 'O') != 0) |
|
2783 /* Can't do simple format if source and dest are different. */ |
|
2784 continue; |
|
2785 |
|
2786 (*info->fprintf_func) (stream, opcode->name); |
|
2787 |
|
2788 { |
|
2789 const char *s; |
|
2790 |
|
2791 if (opcode->args[0] != ',') |
|
2792 (*info->fprintf_func) (stream, " "); |
|
2793 |
|
2794 for (s = opcode->args; *s != '\0'; ++s) |
|
2795 { |
|
2796 while (*s == ',') |
|
2797 { |
|
2798 (*info->fprintf_func) (stream, ","); |
|
2799 ++s; |
|
2800 switch (*s) |
|
2801 { |
|
2802 case 'a': |
|
2803 (*info->fprintf_func) (stream, "a"); |
|
2804 is_annulled = 1; |
|
2805 ++s; |
|
2806 continue; |
|
2807 case 'N': |
|
2808 (*info->fprintf_func) (stream, "pn"); |
|
2809 ++s; |
|
2810 continue; |
|
2811 |
|
2812 case 'T': |
|
2813 (*info->fprintf_func) (stream, "pt"); |
|
2814 ++s; |
|
2815 continue; |
|
2816 |
|
2817 default: |
|
2818 break; |
|
2819 } |
|
2820 } |
|
2821 |
|
2822 (*info->fprintf_func) (stream, " "); |
|
2823 |
|
2824 switch (*s) |
|
2825 { |
|
2826 case '+': |
|
2827 found_plus = 1; |
|
2828 /* Fall through. */ |
|
2829 |
|
2830 default: |
|
2831 (*info->fprintf_func) (stream, "%c", *s); |
|
2832 break; |
|
2833 |
|
2834 case '#': |
|
2835 (*info->fprintf_func) (stream, "0"); |
|
2836 break; |
|
2837 |
|
2838 #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n]) |
|
2839 case '1': |
|
2840 case 'r': |
|
2841 reg (X_RS1 (insn)); |
|
2842 break; |
|
2843 |
|
2844 case '2': |
|
2845 case 'O': |
|
2846 reg (X_RS2 (insn)); |
|
2847 break; |
|
2848 |
|
2849 case 'd': |
|
2850 reg (X_RD (insn)); |
|
2851 break; |
|
2852 #undef reg |
|
2853 |
|
2854 #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n]) |
|
2855 #define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)]) |
|
2856 case 'e': |
|
2857 freg (X_RS1 (insn)); |
|
2858 break; |
|
2859 case 'v': /* Double/even. */ |
|
2860 case 'V': /* Quad/multiple of 4. */ |
|
2861 fregx (X_RS1 (insn)); |
|
2862 break; |
|
2863 |
|
2864 case 'f': |
|
2865 freg (X_RS2 (insn)); |
|
2866 break; |
|
2867 case 'B': /* Double/even. */ |
|
2868 case 'R': /* Quad/multiple of 4. */ |
|
2869 fregx (X_RS2 (insn)); |
|
2870 break; |
|
2871 |
|
2872 case 'g': |
|
2873 freg (X_RD (insn)); |
|
2874 break; |
|
2875 case 'H': /* Double/even. */ |
|
2876 case 'J': /* Quad/multiple of 4. */ |
|
2877 fregx (X_RD (insn)); |
|
2878 break; |
|
2879 #undef freg |
|
2880 #undef fregx |
|
2881 |
|
2882 #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n)) |
|
2883 case 'b': |
|
2884 creg (X_RS1 (insn)); |
|
2885 break; |
|
2886 |
|
2887 case 'c': |
|
2888 creg (X_RS2 (insn)); |
|
2889 break; |
|
2890 |
|
2891 case 'D': |
|
2892 creg (X_RD (insn)); |
|
2893 break; |
|
2894 #undef creg |
|
2895 |
|
2896 case 'h': |
|
2897 (*info->fprintf_func) (stream, "%%hi(%#x)", |
|
2898 ((unsigned) 0xFFFFFFFF |
|
2899 & ((int) X_IMM22 (insn) << 10))); |
|
2900 break; |
|
2901 |
|
2902 case 'i': /* 13 bit immediate. */ |
|
2903 case 'I': /* 11 bit immediate. */ |
|
2904 case 'j': /* 10 bit immediate. */ |
|
2905 { |
|
2906 int imm; |
|
2907 |
|
2908 if (*s == 'i') |
|
2909 imm = X_SIMM (insn, 13); |
|
2910 else if (*s == 'I') |
|
2911 imm = X_SIMM (insn, 11); |
|
2912 else |
|
2913 imm = X_SIMM (insn, 10); |
|
2914 |
|
2915 /* Check to see whether we have a 1+i, and take |
|
2916 note of that fact. |
|
2917 |
|
2918 Note: because of the way we sort the table, |
|
2919 we will be matching 1+i rather than i+1, |
|
2920 so it is OK to assume that i is after +, |
|
2921 not before it. */ |
|
2922 if (found_plus) |
|
2923 imm_added_to_rs1 = 1; |
|
2924 |
|
2925 if (imm <= 9) |
|
2926 (*info->fprintf_func) (stream, "%d", imm); |
|
2927 else |
|
2928 (*info->fprintf_func) (stream, "%#x", imm); |
|
2929 } |
|
2930 break; |
|
2931 |
|
2932 case 'X': /* 5 bit unsigned immediate. */ |
|
2933 case 'Y': /* 6 bit unsigned immediate. */ |
|
2934 { |
|
2935 int imm = X_IMM (insn, *s == 'X' ? 5 : 6); |
|
2936 |
|
2937 if (imm <= 9) |
|
2938 (info->fprintf_func) (stream, "%d", imm); |
|
2939 else |
|
2940 (info->fprintf_func) (stream, "%#x", (unsigned) imm); |
|
2941 } |
|
2942 break; |
|
2943 |
|
2944 case '3': |
|
2945 (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3)); |
|
2946 break; |
|
2947 |
|
2948 case 'K': |
|
2949 { |
|
2950 int mask = X_MEMBAR (insn); |
|
2951 int bit = 0x40, printed_one = 0; |
|
2952 const char *name; |
|
2953 |
|
2954 if (mask == 0) |
|
2955 (info->fprintf_func) (stream, "0"); |
|
2956 else |
|
2957 while (bit) |
|
2958 { |
|
2959 if (mask & bit) |
|
2960 { |
|
2961 if (printed_one) |
|
2962 (info->fprintf_func) (stream, "|"); |
|
2963 name = sparc_decode_membar (bit); |
|
2964 (info->fprintf_func) (stream, "%s", name); |
|
2965 printed_one = 1; |
|
2966 } |
|
2967 bit >>= 1; |
|
2968 } |
|
2969 break; |
|
2970 } |
|
2971 |
|
2972 case 'k': |
|
2973 info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4; |
|
2974 (*info->print_address_func) (info->target, info); |
|
2975 break; |
|
2976 |
|
2977 case 'G': |
|
2978 info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4; |
|
2979 (*info->print_address_func) (info->target, info); |
|
2980 break; |
|
2981 |
|
2982 case '6': |
|
2983 case '7': |
|
2984 case '8': |
|
2985 case '9': |
|
2986 (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0'); |
|
2987 break; |
|
2988 |
|
2989 case 'z': |
|
2990 (*info->fprintf_func) (stream, "%%icc"); |
|
2991 break; |
|
2992 |
|
2993 case 'Z': |
|
2994 (*info->fprintf_func) (stream, "%%xcc"); |
|
2995 break; |
|
2996 |
|
2997 case 'E': |
|
2998 (*info->fprintf_func) (stream, "%%ccr"); |
|
2999 break; |
|
3000 |
|
3001 case 's': |
|
3002 (*info->fprintf_func) (stream, "%%fprs"); |
|
3003 break; |
|
3004 |
|
3005 case 'o': |
|
3006 (*info->fprintf_func) (stream, "%%asi"); |
|
3007 break; |
|
3008 |
|
3009 case 'W': |
|
3010 (*info->fprintf_func) (stream, "%%tick"); |
|
3011 break; |
|
3012 |
|
3013 case 'P': |
|
3014 (*info->fprintf_func) (stream, "%%pc"); |
|
3015 break; |
|
3016 |
|
3017 case '?': |
|
3018 if (X_RS1 (insn) == 31) |
|
3019 (*info->fprintf_func) (stream, "%%ver"); |
|
3020 else if ((unsigned) X_RS1 (insn) < 17) |
|
3021 (*info->fprintf_func) (stream, "%%%s", |
|
3022 v9_priv_reg_names[X_RS1 (insn)]); |
|
3023 else |
|
3024 (*info->fprintf_func) (stream, "%%reserved"); |
|
3025 break; |
|
3026 |
|
3027 case '!': |
|
3028 if ((unsigned) X_RD (insn) < 17) |
|
3029 (*info->fprintf_func) (stream, "%%%s", |
|
3030 v9_priv_reg_names[X_RD (insn)]); |
|
3031 else |
|
3032 (*info->fprintf_func) (stream, "%%reserved"); |
|
3033 break; |
|
3034 |
|
3035 case '$': |
|
3036 if ((unsigned) X_RS1 (insn) < 32) |
|
3037 (*info->fprintf_func) (stream, "%%%s", |
|
3038 v9_hpriv_reg_names[X_RS1 (insn)]); |
|
3039 else |
|
3040 (*info->fprintf_func) (stream, "%%reserved"); |
|
3041 break; |
|
3042 |
|
3043 case '%': |
|
3044 if ((unsigned) X_RD (insn) < 32) |
|
3045 (*info->fprintf_func) (stream, "%%%s", |
|
3046 v9_hpriv_reg_names[X_RD (insn)]); |
|
3047 else |
|
3048 (*info->fprintf_func) (stream, "%%reserved"); |
|
3049 break; |
|
3050 |
|
3051 case '/': |
|
3052 if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25) |
|
3053 (*info->fprintf_func) (stream, "%%reserved"); |
|
3054 else |
|
3055 (*info->fprintf_func) (stream, "%%%s", |
|
3056 v9a_asr_reg_names[X_RS1 (insn)-16]); |
|
3057 break; |
|
3058 |
|
3059 case '_': |
|
3060 if (X_RD (insn) < 16 || X_RD (insn) > 25) |
|
3061 (*info->fprintf_func) (stream, "%%reserved"); |
|
3062 else |
|
3063 (*info->fprintf_func) (stream, "%%%s", |
|
3064 v9a_asr_reg_names[X_RD (insn)-16]); |
|
3065 break; |
|
3066 |
|
3067 case '*': |
|
3068 { |
|
3069 const char *name = sparc_decode_prefetch (X_RD (insn)); |
|
3070 |
|
3071 if (name) |
|
3072 (*info->fprintf_func) (stream, "%s", name); |
|
3073 else |
|
3074 (*info->fprintf_func) (stream, "%ld", X_RD (insn)); |
|
3075 break; |
|
3076 } |
|
3077 |
|
3078 case 'M': |
|
3079 (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn)); |
|
3080 break; |
|
3081 |
|
3082 case 'm': |
|
3083 (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn)); |
|
3084 break; |
|
3085 |
|
3086 case 'L': |
|
3087 info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4; |
|
3088 (*info->print_address_func) (info->target, info); |
|
3089 break; |
|
3090 |
|
3091 case 'n': |
|
3092 (*info->fprintf_func) |
|
3093 (stream, "%#x", SEX (X_DISP22 (insn), 22)); |
|
3094 break; |
|
3095 |
|
3096 case 'l': |
|
3097 info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4; |
|
3098 (*info->print_address_func) (info->target, info); |
|
3099 break; |
|
3100 |
|
3101 case 'A': |
|
3102 { |
|
3103 const char *name; |
|
3104 |
|
3105 if ((info->mach == bfd_mach_sparc_v8plusa) || |
|
3106 ((info->mach >= bfd_mach_sparc_v9) && |
|
3107 (info->mach <= bfd_mach_sparc_v9b))) |
|
3108 name = sparc_decode_asi_v9 (X_ASI (insn)); |
|
3109 else |
|
3110 name = sparc_decode_asi_v8 (X_ASI (insn)); |
|
3111 |
|
3112 if (name) |
|
3113 (*info->fprintf_func) (stream, "%s", name); |
|
3114 else |
|
3115 (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn)); |
|
3116 break; |
|
3117 } |
|
3118 |
|
3119 case 'C': |
|
3120 (*info->fprintf_func) (stream, "%%csr"); |
|
3121 break; |
|
3122 |
|
3123 case 'F': |
|
3124 (*info->fprintf_func) (stream, "%%fsr"); |
|
3125 break; |
|
3126 |
|
3127 case 'p': |
|
3128 (*info->fprintf_func) (stream, "%%psr"); |
|
3129 break; |
|
3130 |
|
3131 case 'q': |
|
3132 (*info->fprintf_func) (stream, "%%fq"); |
|
3133 break; |
|
3134 |
|
3135 case 'Q': |
|
3136 (*info->fprintf_func) (stream, "%%cq"); |
|
3137 break; |
|
3138 |
|
3139 case 't': |
|
3140 (*info->fprintf_func) (stream, "%%tbr"); |
|
3141 break; |
|
3142 |
|
3143 case 'w': |
|
3144 (*info->fprintf_func) (stream, "%%wim"); |
|
3145 break; |
|
3146 |
|
3147 case 'x': |
|
3148 (*info->fprintf_func) (stream, "%ld", |
|
3149 ((X_LDST_I (insn) << 8) |
|
3150 + X_ASI (insn))); |
|
3151 break; |
|
3152 |
|
3153 case 'y': |
|
3154 (*info->fprintf_func) (stream, "%%y"); |
|
3155 break; |
|
3156 |
|
3157 case 'u': |
|
3158 case 'U': |
|
3159 { |
|
3160 int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn); |
|
3161 const char *name = sparc_decode_sparclet_cpreg (val); |
|
3162 |
|
3163 if (name) |
|
3164 (*info->fprintf_func) (stream, "%s", name); |
|
3165 else |
|
3166 (*info->fprintf_func) (stream, "%%cpreg(%d)", val); |
|
3167 break; |
|
3168 } |
|
3169 } |
|
3170 } |
|
3171 } |
|
3172 |
|
3173 /* If we are adding or or'ing something to rs1, then |
|
3174 check to see whether the previous instruction was |
|
3175 a sethi to the same register as in the sethi. |
|
3176 If so, attempt to print the result of the add or |
|
3177 or (in this context add and or do the same thing) |
|
3178 and its symbolic value. */ |
|
3179 if (imm_ored_to_rs1 || imm_added_to_rs1) |
|
3180 { |
|
3181 unsigned long prev_insn; |
|
3182 int errcode; |
|
3183 |
|
3184 if (memaddr >= 4) |
|
3185 errcode = |
|
3186 (*info->read_memory_func) |
|
3187 (memaddr - 4, buffer, sizeof (buffer), info); |
|
3188 else |
|
3189 errcode = 1; |
|
3190 |
|
3191 prev_insn = getword (buffer); |
|
3192 |
|
3193 if (errcode == 0) |
|
3194 { |
|
3195 /* If it is a delayed branch, we need to look at the |
|
3196 instruction before the delayed branch. This handles |
|
3197 sequences such as: |
|
3198 |
|
3199 sethi %o1, %hi(_foo), %o1 |
|
3200 call _printf |
|
3201 or %o1, %lo(_foo), %o1 */ |
|
3202 |
|
3203 if (is_delayed_branch (prev_insn)) |
|
3204 { |
|
3205 if (memaddr >= 8) |
|
3206 errcode = (*info->read_memory_func) |
|
3207 (memaddr - 8, buffer, sizeof (buffer), info); |
|
3208 else |
|
3209 errcode = 1; |
|
3210 |
|
3211 prev_insn = getword (buffer); |
|
3212 } |
|
3213 } |
|
3214 |
|
3215 /* If there was a problem reading memory, then assume |
|
3216 the previous instruction was not sethi. */ |
|
3217 if (errcode == 0) |
|
3218 { |
|
3219 /* Is it sethi to the same register? */ |
|
3220 if ((prev_insn & 0xc1c00000) == 0x01000000 |
|
3221 && X_RD (prev_insn) == X_RS1 (insn)) |
|
3222 { |
|
3223 (*info->fprintf_func) (stream, "\t! "); |
|
3224 info->target = |
|
3225 ((unsigned) 0xFFFFFFFF |
|
3226 & ((int) X_IMM22 (prev_insn) << 10)); |
|
3227 if (imm_added_to_rs1) |
|
3228 info->target += X_SIMM (insn, 13); |
|
3229 else |
|
3230 info->target |= X_SIMM (insn, 13); |
|
3231 (*info->print_address_func) (info->target, info); |
|
3232 info->insn_type = dis_dref; |
|
3233 info->data_size = 4; /* FIXME!!! */ |
|
3234 } |
|
3235 } |
|
3236 } |
|
3237 |
|
3238 if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR)) |
|
3239 { |
|
3240 /* FIXME -- check is_annulled flag. */ |
|
3241 if (opcode->flags & F_UNBR) |
|
3242 info->insn_type = dis_branch; |
|
3243 if (opcode->flags & F_CONDBR) |
|
3244 info->insn_type = dis_condbranch; |
|
3245 if (opcode->flags & F_JSR) |
|
3246 info->insn_type = dis_jsr; |
|
3247 if (opcode->flags & F_DELAYED) |
|
3248 info->branch_delay_insns = 1; |
|
3249 } |
|
3250 |
|
3251 return sizeof (buffer); |
|
3252 } |
|
3253 } |
|
3254 |
|
3255 info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */ |
|
3256 (*info->fprintf_func) (stream, _("unknown")); |
|
3257 return sizeof (buffer); |
|
3258 } |