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1 /* |
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2 * Alpha emulation cpu definitions for qemu. |
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3 * |
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4 * Copyright (c) 2007 Jocelyn Mayer |
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5 * |
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6 * This library is free software; you can redistribute it and/or |
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7 * modify it under the terms of the GNU Lesser General Public |
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8 * License as published by the Free Software Foundation; either |
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9 * version 2 of the License, or (at your option) any later version. |
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10 * |
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11 * This library is distributed in the hope that it will be useful, |
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 * Lesser General Public License for more details. |
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15 * |
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16 * You should have received a copy of the GNU Lesser General Public |
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17 * License along with this library; if not, write to the Free Software |
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18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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19 */ |
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20 |
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21 #if !defined (__CPU_ALPHA_H__) |
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22 #define __CPU_ALPHA_H__ |
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23 |
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24 #include "config.h" |
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25 |
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26 #define TARGET_LONG_BITS 64 |
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27 |
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28 #include "cpu-defs.h" |
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29 |
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30 #include <setjmp.h> |
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31 |
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32 #include "softfloat.h" |
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33 |
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34 #define TARGET_HAS_ICE 1 |
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35 |
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36 #define ELF_MACHINE EM_ALPHA |
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37 |
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38 #define ICACHE_LINE_SIZE 32 |
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39 #define DCACHE_LINE_SIZE 32 |
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40 |
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41 #define TARGET_PAGE_BITS 12 |
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42 |
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43 #define VA_BITS 43 |
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44 |
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45 /* Alpha major type */ |
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46 enum { |
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47 ALPHA_EV3 = 1, |
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48 ALPHA_EV4 = 2, |
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49 ALPHA_SIM = 3, |
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50 ALPHA_LCA = 4, |
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51 ALPHA_EV5 = 5, /* 21164 */ |
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52 ALPHA_EV45 = 6, /* 21064A */ |
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53 ALPHA_EV56 = 7, /* 21164A */ |
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54 }; |
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55 |
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56 /* EV4 minor type */ |
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57 enum { |
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58 ALPHA_EV4_2 = 0, |
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59 ALPHA_EV4_3 = 1, |
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60 }; |
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61 |
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62 /* LCA minor type */ |
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63 enum { |
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64 ALPHA_LCA_1 = 1, /* 21066 */ |
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65 ALPHA_LCA_2 = 2, /* 20166 */ |
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66 ALPHA_LCA_3 = 3, /* 21068 */ |
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67 ALPHA_LCA_4 = 4, /* 21068 */ |
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68 ALPHA_LCA_5 = 5, /* 21066A */ |
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69 ALPHA_LCA_6 = 6, /* 21068A */ |
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70 }; |
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71 |
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72 /* EV5 minor type */ |
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73 enum { |
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74 ALPHA_EV5_1 = 1, /* Rev BA, CA */ |
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75 ALPHA_EV5_2 = 2, /* Rev DA, EA */ |
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76 ALPHA_EV5_3 = 3, /* Pass 3 */ |
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77 ALPHA_EV5_4 = 4, /* Pass 3.2 */ |
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78 ALPHA_EV5_5 = 5, /* Pass 4 */ |
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79 }; |
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80 |
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81 /* EV45 minor type */ |
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82 enum { |
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83 ALPHA_EV45_1 = 1, /* Pass 1 */ |
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84 ALPHA_EV45_2 = 2, /* Pass 1.1 */ |
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85 ALPHA_EV45_3 = 3, /* Pass 2 */ |
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86 }; |
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87 |
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88 /* EV56 minor type */ |
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89 enum { |
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90 ALPHA_EV56_1 = 1, /* Pass 1 */ |
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91 ALPHA_EV56_2 = 2, /* Pass 2 */ |
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92 }; |
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93 |
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94 enum { |
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95 IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */ |
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96 IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */ |
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97 IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */ |
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98 IMPLVER_21364 = 3, /* EV7 & EV79 */ |
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99 }; |
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100 |
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101 enum { |
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102 AMASK_BWX = 0x00000001, |
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103 AMASK_FIX = 0x00000002, |
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104 AMASK_CIX = 0x00000004, |
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105 AMASK_MVI = 0x00000100, |
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106 AMASK_TRAP = 0x00000200, |
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107 AMASK_PREFETCH = 0x00001000, |
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108 }; |
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109 |
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110 enum { |
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111 VAX_ROUND_NORMAL = 0, |
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112 VAX_ROUND_CHOPPED, |
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113 }; |
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114 |
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115 enum { |
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116 IEEE_ROUND_NORMAL = 0, |
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117 IEEE_ROUND_DYNAMIC, |
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118 IEEE_ROUND_PLUS, |
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119 IEEE_ROUND_MINUS, |
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120 IEEE_ROUND_CHOPPED, |
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121 }; |
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122 |
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123 /* IEEE floating-point operations encoding */ |
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124 /* Trap mode */ |
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125 enum { |
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126 FP_TRAP_I = 0x0, |
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127 FP_TRAP_U = 0x1, |
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128 FP_TRAP_S = 0x4, |
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129 FP_TRAP_SU = 0x5, |
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130 FP_TRAP_SUI = 0x7, |
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131 }; |
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132 |
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133 /* Rounding mode */ |
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134 enum { |
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135 FP_ROUND_CHOPPED = 0x0, |
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136 FP_ROUND_MINUS = 0x1, |
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137 FP_ROUND_NORMAL = 0x2, |
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138 FP_ROUND_DYNAMIC = 0x3, |
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139 }; |
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140 |
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141 /* Internal processor registers */ |
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142 /* XXX: TOFIX: most of those registers are implementation dependant */ |
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143 enum { |
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144 /* Ebox IPRs */ |
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145 IPR_CC = 0xC0, |
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146 IPR_CC_CTL = 0xC1, |
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147 IPR_VA = 0xC2, |
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148 IPR_VA_CTL = 0xC4, |
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149 IPR_VA_FORM = 0xC3, |
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150 /* Ibox IPRs */ |
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151 IPR_ITB_TAG = 0x00, |
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152 IPR_ITB_PTE = 0x01, |
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153 IPT_ITB_IAP = 0x02, |
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154 IPT_ITB_IA = 0x03, |
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155 IPT_ITB_IS = 0x04, |
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156 IPR_PMPC = 0x05, |
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157 IPR_EXC_ADDR = 0x06, |
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158 IPR_IVA_FORM = 0x07, |
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159 IPR_CM = 0x09, |
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160 IPR_IER = 0x0A, |
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161 IPR_SIRR = 0x0C, |
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162 IPR_ISUM = 0x0D, |
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163 IPR_HW_INT_CLR = 0x0E, |
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164 IPR_EXC_SUM = 0x0F, |
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165 IPR_PAL_BASE = 0x10, |
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166 IPR_I_CTL = 0x11, |
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167 IPR_I_STAT = 0x16, |
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168 IPR_IC_FLUSH = 0x13, |
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169 IPR_IC_FLUSH_ASM = 0x12, |
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170 IPR_CLR_MAP = 0x15, |
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171 IPR_SLEEP = 0x17, |
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172 IPR_PCTX = 0x40, |
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173 IPR_PCTR_CTL = 0x14, |
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174 /* Mbox IPRs */ |
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175 IPR_DTB_TAG0 = 0x20, |
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176 IPR_DTB_TAG1 = 0xA0, |
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177 IPR_DTB_PTE0 = 0x21, |
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178 IPR_DTB_PTE1 = 0xA1, |
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179 IPR_DTB_ALTMODE = 0xA6, |
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180 IPR_DTB_IAP = 0xA2, |
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181 IPR_DTB_IA = 0xA3, |
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182 IPR_DTB_IS0 = 0x24, |
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183 IPR_DTB_IS1 = 0xA4, |
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184 IPR_DTB_ASN0 = 0x25, |
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185 IPR_DTB_ASN1 = 0xA5, |
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186 IPR_MM_STAT = 0x27, |
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187 IPR_M_CTL = 0x28, |
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188 IPR_DC_CTL = 0x29, |
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189 IPR_DC_STAT = 0x2A, |
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190 /* Cbox IPRs */ |
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191 IPR_C_DATA = 0x2B, |
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192 IPR_C_SHIFT = 0x2C, |
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193 |
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194 IPR_ASN, |
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195 IPR_ASTEN, |
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196 IPR_ASTSR, |
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197 IPR_DATFX, |
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198 IPR_ESP, |
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199 IPR_FEN, |
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200 IPR_IPIR, |
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201 IPR_IPL, |
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202 IPR_KSP, |
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203 IPR_MCES, |
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204 IPR_PERFMON, |
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205 IPR_PCBB, |
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206 IPR_PRBR, |
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207 IPR_PTBR, |
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208 IPR_SCBB, |
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209 IPR_SISR, |
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210 IPR_SSP, |
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211 IPR_SYSPTBR, |
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212 IPR_TBCHK, |
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213 IPR_TBIA, |
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214 IPR_TBIAP, |
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215 IPR_TBIS, |
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216 IPR_TBISD, |
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217 IPR_TBISI, |
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218 IPR_USP, |
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219 IPR_VIRBND, |
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220 IPR_VPTB, |
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221 IPR_WHAMI, |
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222 IPR_ALT_MODE, |
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223 IPR_LAST, |
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224 }; |
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225 |
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226 typedef struct CPUAlphaState CPUAlphaState; |
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227 |
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228 typedef struct pal_handler_t pal_handler_t; |
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229 struct pal_handler_t { |
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230 /* Reset */ |
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231 void (*reset)(CPUAlphaState *env); |
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232 /* Uncorrectable hardware error */ |
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233 void (*machine_check)(CPUAlphaState *env); |
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234 /* Arithmetic exception */ |
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235 void (*arithmetic)(CPUAlphaState *env); |
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236 /* Interrupt / correctable hardware error */ |
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237 void (*interrupt)(CPUAlphaState *env); |
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238 /* Data fault */ |
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239 void (*dfault)(CPUAlphaState *env); |
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240 /* DTB miss pal */ |
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241 void (*dtb_miss_pal)(CPUAlphaState *env); |
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242 /* DTB miss native */ |
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243 void (*dtb_miss_native)(CPUAlphaState *env); |
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244 /* Unaligned access */ |
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245 void (*unalign)(CPUAlphaState *env); |
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246 /* ITB miss */ |
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247 void (*itb_miss)(CPUAlphaState *env); |
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248 /* Instruction stream access violation */ |
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249 void (*itb_acv)(CPUAlphaState *env); |
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250 /* Reserved or privileged opcode */ |
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251 void (*opcdec)(CPUAlphaState *env); |
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252 /* Floating point exception */ |
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253 void (*fen)(CPUAlphaState *env); |
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254 /* Call pal instruction */ |
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255 void (*call_pal)(CPUAlphaState *env, uint32_t palcode); |
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256 }; |
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257 |
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258 #define NB_MMU_MODES 4 |
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259 |
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260 struct CPUAlphaState { |
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261 uint64_t ir[31]; |
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262 float64 fir[31]; |
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263 float_status fp_status; |
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264 uint64_t fpcr; |
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265 uint64_t pc; |
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266 uint64_t lock; |
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267 uint32_t pcc[2]; |
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268 uint64_t ipr[IPR_LAST]; |
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269 uint64_t ps; |
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270 uint64_t unique; |
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271 int saved_mode; /* Used for HW_LD / HW_ST */ |
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272 int intr_flag; /* For RC and RS */ |
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273 |
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274 #if TARGET_LONG_BITS > HOST_LONG_BITS |
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275 /* temporary fixed-point registers |
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276 * used to emulate 64 bits target on 32 bits hosts |
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277 */ |
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278 target_ulong t0, t1; |
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279 #endif |
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280 |
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281 /* Those resources are used only in Qemu core */ |
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282 CPU_COMMON |
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283 |
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284 uint32_t hflags; |
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285 |
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286 int error_code; |
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287 |
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288 uint32_t features; |
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289 uint32_t amask; |
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290 int implver; |
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291 pal_handler_t *pal_handler; |
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292 }; |
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293 |
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294 #define CPUState CPUAlphaState |
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295 #define cpu_init cpu_alpha_init |
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296 #define cpu_exec cpu_alpha_exec |
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297 #define cpu_gen_code cpu_alpha_gen_code |
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298 #define cpu_signal_handler cpu_alpha_signal_handler |
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299 |
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300 /* MMU modes definitions */ |
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301 #define MMU_MODE0_SUFFIX _kernel |
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302 #define MMU_MODE1_SUFFIX _executive |
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303 #define MMU_MODE2_SUFFIX _supervisor |
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304 #define MMU_MODE3_SUFFIX _user |
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305 #define MMU_USER_IDX 3 |
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306 static inline int cpu_mmu_index (CPUState *env) |
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307 { |
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308 return (env->ps >> 3) & 3; |
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309 } |
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310 |
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311 #if defined(CONFIG_USER_ONLY) |
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312 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
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313 { |
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314 if (newsp) |
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315 env->ir[30] = newsp; |
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316 /* FIXME: Zero syscall return value. */ |
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317 } |
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318 #endif |
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319 |
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320 #include "cpu-all.h" |
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321 #include "exec-all.h" |
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322 |
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323 enum { |
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324 FEATURE_ASN = 0x00000001, |
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325 FEATURE_SPS = 0x00000002, |
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326 FEATURE_VIRBND = 0x00000004, |
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327 FEATURE_TBCHK = 0x00000008, |
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328 }; |
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329 |
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330 enum { |
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331 EXCP_RESET = 0x0000, |
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332 EXCP_MCHK = 0x0020, |
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333 EXCP_ARITH = 0x0060, |
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334 EXCP_HW_INTERRUPT = 0x00E0, |
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335 EXCP_DFAULT = 0x01E0, |
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336 EXCP_DTB_MISS_PAL = 0x09E0, |
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337 EXCP_ITB_MISS = 0x03E0, |
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338 EXCP_ITB_ACV = 0x07E0, |
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339 EXCP_DTB_MISS_NATIVE = 0x08E0, |
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340 EXCP_UNALIGN = 0x11E0, |
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341 EXCP_OPCDEC = 0x13E0, |
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342 EXCP_FEN = 0x17E0, |
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343 EXCP_CALL_PAL = 0x2000, |
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344 EXCP_CALL_PALP = 0x3000, |
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345 EXCP_CALL_PALE = 0x4000, |
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346 /* Pseudo exception for console */ |
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347 EXCP_CONSOLE_DISPATCH = 0x4001, |
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348 EXCP_CONSOLE_FIXUP = 0x4002, |
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349 }; |
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350 |
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351 /* Arithmetic exception */ |
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352 enum { |
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353 EXCP_ARITH_OVERFLOW, |
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354 }; |
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355 |
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356 enum { |
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357 PALCODE_CALL = 0x00000000, |
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358 PALCODE_LD = 0x01000000, |
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359 PALCODE_ST = 0x02000000, |
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360 PALCODE_MFPR = 0x03000000, |
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361 PALCODE_MTPR = 0x04000000, |
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362 PALCODE_REI = 0x05000000, |
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363 PALCODE_INIT = 0xF0000000, |
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364 }; |
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365 |
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366 enum { |
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367 IR_V0 = 0, |
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368 IR_T0 = 1, |
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369 IR_T1 = 2, |
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370 IR_T2 = 3, |
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371 IR_T3 = 4, |
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372 IR_T4 = 5, |
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373 IR_T5 = 6, |
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374 IR_T6 = 7, |
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375 IR_T7 = 8, |
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376 IR_S0 = 9, |
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377 IR_S1 = 10, |
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378 IR_S2 = 11, |
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379 IR_S3 = 12, |
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380 IR_S4 = 13, |
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381 IR_S5 = 14, |
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382 IR_S6 = 15, |
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383 #define IR_FP IR_S6 |
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384 IR_A0 = 16, |
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385 IR_A1 = 17, |
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386 IR_A2 = 18, |
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387 IR_A3 = 19, |
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388 IR_A4 = 20, |
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389 IR_A5 = 21, |
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390 IR_T8 = 22, |
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391 IR_T9 = 23, |
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392 IR_T10 = 24, |
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393 IR_T11 = 25, |
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394 IR_RA = 26, |
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395 IR_T12 = 27, |
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396 #define IR_PV IR_T12 |
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397 IR_AT = 28, |
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398 IR_GP = 29, |
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399 IR_SP = 30, |
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400 IR_ZERO = 31, |
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401 }; |
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402 |
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403 CPUAlphaState * cpu_alpha_init (const char *cpu_model); |
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404 int cpu_alpha_exec(CPUAlphaState *s); |
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405 /* you can call this signal handler from your SIGBUS and SIGSEGV |
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406 signal handlers to inform the virtual CPU of exceptions. non zero |
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407 is returned if the signal was handled by the virtual CPU. */ |
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408 int cpu_alpha_signal_handler(int host_signum, void *pinfo, |
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409 void *puc); |
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410 int cpu_alpha_handle_mmu_fault (CPUState *env, uint64_t address, int rw, |
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411 int mmu_idx, int is_softmmu); |
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412 void do_interrupt (CPUState *env); |
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413 |
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414 int cpu_alpha_mfpr (CPUState *env, int iprn, uint64_t *valp); |
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415 int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp); |
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416 void pal_init (CPUState *env); |
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417 #if !defined (CONFIG_USER_ONLY) |
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418 void call_pal (CPUState *env); |
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419 #else |
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420 void call_pal (CPUState *env, int palcode); |
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421 #endif |
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422 |
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423 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
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424 { |
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425 env->pc = tb->pc; |
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426 } |
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427 |
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428 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
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429 target_ulong *cs_base, int *flags) |
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430 { |
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431 *pc = env->pc; |
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432 *cs_base = 0; |
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433 *flags = env->ps; |
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434 } |
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435 |
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436 #endif /* !defined (__CPU_ALPHA_H__) */ |