1 #include <stdio.h>

     2 #include <stdlib.h>

     3 #include <string.h>

     4 

     5 #include "cpu.h"

     6 #include "exec-all.h"

     7 #include "gdbstub.h"

     8 #include "helpers.h"

     9 #include "qemu-common.h"

    10 

    11 static uint32_t cortexa8_cp15_c0_c1[8] =

    12 { 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };

    13 

    14 static uint32_t cortexa8_cp15_c0_c2[8] =

    15 { 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };

    16 

    17 static uint32_t mpcore_cp15_c0_c1[8] =

    18 { 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };

    19 

    20 static uint32_t mpcore_cp15_c0_c2[8] =

    21 { 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };

    22 

    23 static uint32_t arm1136_cp15_c0_c1[8] =

    24 { 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };

    25 

    26 static uint32_t arm1136_cp15_c0_c2[8] =

    27 { 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };

    28 

    29 static uint32_t cpu_arm_find_by_name(const char *name);

    30 

    31 static inline void set_feature(CPUARMState *env, int feature)

    32 {

    33     env->features |= 1u << feature;

    34 }

    35 

    36 static void cpu_reset_model_id(CPUARMState *env, uint32_t id)

    37 {

    38     env->cp15.c0_cpuid = id;

    39     switch (id) {

    40     case ARM_CPUID_ARM926:

    41         set_feature(env, ARM_FEATURE_VFP);

    42         env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;

    43         env->cp15.c0_cachetype = 0x1dd20d2;

    44         env->cp15.c1_sys = 0x00090078;

    45         break;

    46     case ARM_CPUID_ARM946:

    47         set_feature(env, ARM_FEATURE_MPU);

    48         env->cp15.c0_cachetype = 0x0f004006;

    49         env->cp15.c1_sys = 0x00000078;

    50         break;

    51     case ARM_CPUID_ARM1026:

    52         set_feature(env, ARM_FEATURE_VFP);

    53         set_feature(env, ARM_FEATURE_AUXCR);

    54         env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;

    55         env->cp15.c0_cachetype = 0x1dd20d2;

    56         env->cp15.c1_sys = 0x00090078;

    57         break;

    58     case ARM_CPUID_ARM1136_R2:

    59     case ARM_CPUID_ARM1136:

    60         set_feature(env, ARM_FEATURE_V6);

    61         set_feature(env, ARM_FEATURE_VFP);

    62         set_feature(env, ARM_FEATURE_AUXCR);

    63         env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;

    64         env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;

    65         env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;

    66         memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));

    67         memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));

    68         env->cp15.c0_cachetype = 0x1dd20d2;

    69         break;

    70     case ARM_CPUID_ARM11MPCORE:

    71         set_feature(env, ARM_FEATURE_V6);

    72         set_feature(env, ARM_FEATURE_V6K);

    73         set_feature(env, ARM_FEATURE_VFP);

    74         set_feature(env, ARM_FEATURE_AUXCR);

    75         env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;

    76         env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;

    77         env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;

    78         memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));

    79         memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));

    80         env->cp15.c0_cachetype = 0x1dd20d2;

    81         break;

    82     case ARM_CPUID_CORTEXA8:

    83         set_feature(env, ARM_FEATURE_V6);

    84         set_feature(env, ARM_FEATURE_V6K);

    85         set_feature(env, ARM_FEATURE_V7);

    86         set_feature(env, ARM_FEATURE_AUXCR);

    87         set_feature(env, ARM_FEATURE_THUMB2);

    88         set_feature(env, ARM_FEATURE_VFP);

    89         set_feature(env, ARM_FEATURE_VFP3);

    90         set_feature(env, ARM_FEATURE_NEON);

    91         set_feature(env, ARM_FEATURE_THUMB2EE);

    92         env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;

    93         env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;

    94         env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;

    95         memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));

    96         memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));

    97         env->cp15.c0_cachetype = 0x82048004;

    98         env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;

    99         env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */

   100         env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */

   101         env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */

   102         break;

   103     case ARM_CPUID_CORTEXM3:

   104         set_feature(env, ARM_FEATURE_V6);

   105         set_feature(env, ARM_FEATURE_THUMB2);

   106         set_feature(env, ARM_FEATURE_V7);

   107         set_feature(env, ARM_FEATURE_M);

   108         set_feature(env, ARM_FEATURE_DIV);

   109         break;

   110     case ARM_CPUID_ANY: /* For userspace emulation.  */

   111         set_feature(env, ARM_FEATURE_V6);

   112         set_feature(env, ARM_FEATURE_V6K);

   113         set_feature(env, ARM_FEATURE_V7);

   114         set_feature(env, ARM_FEATURE_THUMB2);

   115         set_feature(env, ARM_FEATURE_VFP);

   116         set_feature(env, ARM_FEATURE_VFP3);

   117         set_feature(env, ARM_FEATURE_NEON);

   118         set_feature(env, ARM_FEATURE_THUMB2EE);

   119         set_feature(env, ARM_FEATURE_DIV);

   120         set_feature(env, ARM_FEATURE_FP16);

   121         set_feature(env, ARM_FEATURE_THUMB2EE);

   122         break;

   123     case ARM_CPUID_TI915T:

   124     case ARM_CPUID_TI925T:

   125         set_feature(env, ARM_FEATURE_OMAPCP);

   126         env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring.  */

   127         env->cp15.c0_cachetype = 0x5109149;

   128         env->cp15.c1_sys = 0x00000070;

   129         env->cp15.c15_i_max = 0x000;

   130         env->cp15.c15_i_min = 0xff0;

   131         break;

   132     case ARM_CPUID_PXA250:

   133     case ARM_CPUID_PXA255:

   134     case ARM_CPUID_PXA260:

   135     case ARM_CPUID_PXA261:

   136     case ARM_CPUID_PXA262:

   137         set_feature(env, ARM_FEATURE_XSCALE);

   138         /* JTAG_ID is ((id << 28) | 0x09265013) */

   139         env->cp15.c0_cachetype = 0xd172172;

   140         env->cp15.c1_sys = 0x00000078;

   141         break;

   142     case ARM_CPUID_PXA270_A0:

   143     case ARM_CPUID_PXA270_A1:

   144     case ARM_CPUID_PXA270_B0:

   145     case ARM_CPUID_PXA270_B1:

   146     case ARM_CPUID_PXA270_C0:

   147     case ARM_CPUID_PXA270_C5:

   148         set_feature(env, ARM_FEATURE_XSCALE);

   149         /* JTAG_ID is ((id << 28) | 0x09265013) */

   150         set_feature(env, ARM_FEATURE_IWMMXT);

   151         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';

   152         env->cp15.c0_cachetype = 0xd172172;

   153         env->cp15.c1_sys = 0x00000078;

   154         break;

   155     default:

   156         cpu_abort(env, "Bad CPU ID: %x\n", id);

   157         break;

   158     }

   159 }

   160 

   161 void cpu_reset(CPUARMState *env)

   162 {

   163     uint32_t id;

   164     id = env->cp15.c0_cpuid;

   165     memset(env, 0, offsetof(CPUARMState, breakpoints));

   166     if (id)

   167         cpu_reset_model_id(env, id);

   168 #if defined (CONFIG_USER_ONLY)

   169     env->uncached_cpsr = ARM_CPU_MODE_USR;

   170     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;

   171 #else

   172     /* SVC mode with interrupts disabled.  */

   173     env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;

   174     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is

   175        clear at reset.  */

   176     if (IS_M(env))

   177         env->uncached_cpsr &= ~CPSR_I;

   178     env->vfp.xregs[ARM_VFP_FPEXC] = 0;

   179     env->cp15.c2_base_mask = 0xffffc000u;

   180 #endif

   181     env->regs[15] = 0;

   182     tlb_flush(env, 1);

   183     arm_cpu_reset_dev(env);

   184 }

   185 

   186 static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)

   187 {

   188     int nregs;

   189 

   190     /* VFP data registers are always little-endian.  */

   191     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;

   192     if (reg < nregs) {

   193         stfq_le_p(buf, env->vfp.regs[reg]);

   194         return 8;

   195     }

   196     if (arm_feature(env, ARM_FEATURE_NEON)) {

   197         /* Aliases for Q regs.  */

   198         nregs += 16;

   199         if (reg < nregs) {

   200             stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);

   201             stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);

   202             return 16;

   203         }

   204     }

   205     switch (reg - nregs) {

   206     case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;

   207     case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;

   208     case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;

   209     }

   210     return 0;

   211 }

   212 

   213 static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg)

   214 {

   215     int nregs;

   216 

   217     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;

   218     if (reg < nregs) {

   219         env->vfp.regs[reg] = ldfq_le_p(buf);

   220         return 8;

   221     }

   222     if (arm_feature(env, ARM_FEATURE_NEON)) {

   223         nregs += 16;

   224         if (reg < nregs) {

   225             env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);

   226             env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);

   227             return 16;

   228         }

   229     }

   230     switch (reg - nregs) {

   231     case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;

   232     case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;

   233     case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf); return 4;

   234     }

   235     return 0;

   236 }

   237 

   238 CPUARMState *cpu_arm_init(const char *cpu_model, void *dev)

   239 {

   240     CPUARMState *env;

   241     uint32_t id;

   242     static int inited = 0;

   243 

   244     id = cpu_arm_find_by_name(cpu_model);

   245     if (id == 0)

   246         return NULL;

   247     env = qemu_mallocz(sizeof(CPUARMState));

   248     if (!env)

   249         return NULL;

   250     cpu_exec_init(env);

   251     if (!inited) {

   252         inited = 1;

   253         arm_translate_init();

   254     }

   255 

   256     env->cpu_model_str = cpu_model;

   257     env->cp15.c0_cpuid = id;

   258     env->qdev = dev;

   259     cpu_reset(env);

   260     if (arm_feature(env, ARM_FEATURE_NEON)) {

   261         gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,

   262                                  51, "arm-neon.xml", 0);

   263     } else if (arm_feature(env, ARM_FEATURE_VFP3)) {

   264         gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,

   265                                  35, "arm-vfp3.xml", 0);

   266     } else if (arm_feature(env, ARM_FEATURE_VFP)) {

   267         gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,

   268                                  19, "arm-vfp.xml", 0);

   269     }

   270     return env;

   271 }

   272 

   273 struct arm_cpu_t {

   274     uint32_t id;

   275     const char *name;

   276 };

   277 

   278 static const struct arm_cpu_t arm_cpu_names[] = {

   279     { ARM_CPUID_ARM926, "arm926"},

   280     { ARM_CPUID_ARM946, "arm946"},

   281     { ARM_CPUID_ARM1026, "arm1026"},

   282     { ARM_CPUID_ARM1136, "arm1136"},

   283     { ARM_CPUID_ARM1136_R2, "arm1136-r2"},

   284     { ARM_CPUID_ARM11MPCORE, "arm11mpcore"},

   285     { ARM_CPUID_CORTEXM3, "cortex-m3"},

   286     { ARM_CPUID_CORTEXA8, "cortex-a8"},

   287     { ARM_CPUID_TI925T, "ti925t" },

   288     { ARM_CPUID_PXA250, "pxa250" },

   289     { ARM_CPUID_PXA255, "pxa255" },

   290     { ARM_CPUID_PXA260, "pxa260" },

   291     { ARM_CPUID_PXA261, "pxa261" },

   292     { ARM_CPUID_PXA262, "pxa262" },

   293     { ARM_CPUID_PXA270, "pxa270" },

   294     { ARM_CPUID_PXA270_A0, "pxa270-a0" },

   295     { ARM_CPUID_PXA270_A1, "pxa270-a1" },

   296     { ARM_CPUID_PXA270_B0, "pxa270-b0" },

   297     { ARM_CPUID_PXA270_B1, "pxa270-b1" },

   298     { ARM_CPUID_PXA270_C0, "pxa270-c0" },

   299     { ARM_CPUID_PXA270_C5, "pxa270-c5" },

   300     { ARM_CPUID_ANY, "any"},

   301     { 0, NULL}

   302 };

   303 

   304 void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))

   305 {

   306     int i;

   307 

   308     (*cpu_fprintf)(f, "Available CPUs:\n");

   309     for (i = 0; arm_cpu_names[i].name; i++) {

   310         (*cpu_fprintf)(f, "  %s\n", arm_cpu_names[i].name);

   311     }

   312 }

   313 

   314 /* return 0 if not found */

   315 static uint32_t cpu_arm_find_by_name(const char *name)

   316 {

   317     int i;

   318     uint32_t id;

   319 

   320     id = 0;

   321     for (i = 0; arm_cpu_names[i].name; i++) {

   322         if (strcmp(name, arm_cpu_names[i].name) == 0) {

   323             id = arm_cpu_names[i].id;

   324             break;

   325         }

   326     }

   327     return id;

   328 }

   329 

   330 void cpu_arm_close(CPUARMState *env)

   331 {

   332     free(env);

   333 }

   334 

   335 uint32_t cpsr_read(CPUARMState *env)

   336 {

   337     int ZF;

   338     ZF = (env->ZF == 0);

   339     return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |

   340         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)

   341         | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)

   342         | ((env->condexec_bits & 0xfc) << 8)

   343         | (env->GE << 16);

   344 }

   345 

   346 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)

   347 {

   348     if (mask & CPSR_NZCV) {

   349         env->ZF = (~val) & CPSR_Z;

   350         env->NF = val;

   351         env->CF = (val >> 29) & 1;

   352         env->VF = (val << 3) & 0x80000000;

   353     }

   354     if (mask & CPSR_Q)

   355         env->QF = ((val & CPSR_Q) != 0);

   356     if (mask & CPSR_T)

   357         env->thumb = ((val & CPSR_T) != 0);

   358     if (mask & CPSR_IT_0_1) {

   359         env->condexec_bits &= ~3;

   360         env->condexec_bits |= (val >> 25) & 3;

   361     }

   362     if (mask & CPSR_IT_2_7) {

   363         env->condexec_bits &= 3;

   364         env->condexec_bits |= (val >> 8) & 0xfc;

   365     }

   366     if (mask & CPSR_GE) {

   367         env->GE = (val >> 16) & 0xf;

   368     }

   369 

   370     if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {

   371         switch_mode(env, val & CPSR_M);

   372     }

   373     mask &= ~CACHED_CPSR_BITS;

   374     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);

   375 }

   376 

   377 /* Sign/zero extend */

   378 uint32_t HELPER(sxtb16)(uint32_t x)

   379 {

   380     uint32_t res;

   381     res = (uint16_t)(int8_t)x;

   382     res |= (uint32_t)(int8_t)(x >> 16) << 16;

   383     return res;

   384 }

   385 

   386 uint32_t HELPER(uxtb16)(uint32_t x)

   387 {

   388     uint32_t res;

   389     res = (uint16_t)(uint8_t)x;

   390     res |= (uint32_t)(uint8_t)(x >> 16) << 16;

   391     return res;

   392 }

   393 

   394 uint32_t HELPER(clz)(uint32_t x)

   395 {

   396     int count;

   397     for (count = 32; x; count--)

   398         x >>= 1;

   399     return count;

   400 }

   401 

   402 int32_t HELPER(sdiv)(int32_t num, int32_t den)

   403 {

   404     if (den == 0)

   405       return 0;

   406     return num / den;

   407 }

   408 

   409 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)

   410 {

   411     if (den == 0)

   412       return 0;

   413     return num / den;

   414 }

   415 

   416 uint32_t HELPER(rbit)(uint32_t x)

   417 {

   418     x =  ((x & 0xff000000) >> 24)

   419        | ((x & 0x00ff0000) >> 8)

   420        | ((x & 0x0000ff00) << 8)

   421        | ((x & 0x000000ff) << 24);

   422     x =  ((x & 0xf0f0f0f0) >> 4)

   423        | ((x & 0x0f0f0f0f) << 4);

   424     x =  ((x & 0x88888888) >> 3)

   425        | ((x & 0x44444444) >> 1)

   426        | ((x & 0x22222222) << 1)

   427        | ((x & 0x11111111) << 3);

   428     return x;

   429 }

   430 

   431 uint32_t HELPER(abs)(uint32_t x)

   432 {

   433     return ((int32_t)x < 0) ? -x : x;

   434 }

   435 

   436 #if defined(CONFIG_USER_ONLY)

   437 

   438 void do_interrupt (CPUState *env)

   439 {

   440     env->exception_index = -1;

   441 }

   442 

   443 /* Structure used to record exclusive memory locations.  */

   444 typedef struct mmon_state {

   445     struct mmon_state *next;

   446     CPUARMState *cpu_env;

   447     uint32_t addr;

   448 } mmon_state;

   449 

   450 /* Chain of current locks.  */

   451 static mmon_state* mmon_head = NULL;

   452 

   453 int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,

   454                               int mmu_idx, int is_softmmu)

   455 {

   456     if (rw == 2) {

   457         env->exception_index = EXCP_PREFETCH_ABORT;

   458         env->cp15.c6_insn = address;

   459     } else {

   460         env->exception_index = EXCP_DATA_ABORT;

   461         env->cp15.c6_data = address;

   462     }

   463     return 1;

   464 }

   465 

   466 static void allocate_mmon_state(CPUState *env)

   467 {

   468     env->mmon_entry = malloc(sizeof (mmon_state));

   469     if (!env->mmon_entry)

   470         abort();

   471     memset (env->mmon_entry, 0, sizeof (mmon_state));

   472     env->mmon_entry->cpu_env = env;

   473     mmon_head = env->mmon_entry;

   474 }

   475 

   476 /* Flush any monitor locks for the specified address.  */

   477 static void flush_mmon(uint32_t addr)

   478 {

   479     mmon_state *mon;

   480 

   481     for (mon = mmon_head; mon; mon = mon->next)

   482       {

   483         if (mon->addr != addr)

   484           continue;

   485 

   486         mon->addr = 0;

   487         break;

   488       }

   489 }

   490 

   491 /* Mark an address for exclusive access.  */

   492 void HELPER(mark_exclusive)(CPUState *env, uint32_t addr)

   493 {

   494     if (!env->mmon_entry)

   495         allocate_mmon_state(env);

   496     /* Clear any previous locks.  */

   497     flush_mmon(addr);

   498     env->mmon_entry->addr = addr;

   499 }

   500 

   501 /* Test if an exclusive address is still exclusive.  Returns zero

   502    if the address is still exclusive.   */

   503 uint32_t HELPER(test_exclusive)(CPUState *env, uint32_t addr)

   504 {

   505     int res;

   506 

   507     if (!env->mmon_entry)

   508         return 1;

   509     if (env->mmon_entry->addr == addr)

   510         res = 0;

   511     else

   512         res = 1;

   513     flush_mmon(addr);

   514     return res;

   515 }

   516 

   517 void HELPER(clrex)(CPUState *env)

   518 {

   519     if (!(env->mmon_entry && env->mmon_entry->addr))

   520         return;

   521     flush_mmon(env->mmon_entry->addr);

   522 }

   523 

   524 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)

   525 {

   526     return addr;

   527 }

   528 

   529 /* These should probably raise undefined insn exceptions.  */

   530 void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)

   531 {

   532     int op1 = (insn >> 8) & 0xf;

   533     cpu_abort(env, "cp%i insn %08x\n", op1, insn);

   534     return;

   535 }

   536 

   537 uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)

   538 {

   539     int op1 = (insn >> 8) & 0xf;

   540     cpu_abort(env, "cp%i insn %08x\n", op1, insn);

   541     return 0;

   542 }

   543 

   544 void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)

   545 {

   546     cpu_abort(env, "cp15 insn %08x\n", insn);

   547 }

   548 

   549 uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)

   550 {

   551     cpu_abort(env, "cp15 insn %08x\n", insn);

   552     return 0;

   553 }

   554 

   555 /* These should probably raise undefined insn exceptions.  */

   556 void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)

   557 {

   558     cpu_abort(env, "v7m_mrs %d\n", reg);

   559 }

   560 

   561 uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)

   562 {

   563     cpu_abort(env, "v7m_mrs %d\n", reg);

   564     return 0;

   565 }

   566 

   567 void switch_mode(CPUState *env, int mode)

   568 {

   569     if (mode != ARM_CPU_MODE_USR)

   570         cpu_abort(env, "Tried to switch out of user mode\n");

   571 }

   572 

   573 void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)

   574 {

   575     cpu_abort(env, "banked r13 write\n");

   576 }

   577 

   578 uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)

   579 {

   580     cpu_abort(env, "banked r13 read\n");

   581     return 0;

   582 }

   583 

   584 #else

   585 

   586 extern int semihosting_enabled;

   587 

   588 /* Map CPU modes onto saved register banks.  */

   589 static inline int bank_number (int mode)

   590 {

   591     switch (mode) {

   592     case ARM_CPU_MODE_USR:

   593     case ARM_CPU_MODE_SYS:

   594         return 0;

   595     case ARM_CPU_MODE_SVC:

   596         return 1;

   597     case ARM_CPU_MODE_ABT:

   598         return 2;

   599     case ARM_CPU_MODE_UND:

   600         return 3;

   601     case ARM_CPU_MODE_IRQ:

   602         return 4;

   603     case ARM_CPU_MODE_FIQ:

   604         return 5;

   605     }

   606     cpu_abort(cpu_single_env, "Bad mode %x\n", mode);

   607     return -1;

   608 }

   609 

   610 void switch_mode(CPUState *env, int mode)

   611 {

   612     int old_mode;

   613     int i;

   614 

   615     old_mode = env->uncached_cpsr & CPSR_M;

   616     if (mode == old_mode)

   617         return;

   618 

   619     if (old_mode == ARM_CPU_MODE_FIQ) {

   620         memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));

   621         memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));

   622     } else if (mode == ARM_CPU_MODE_FIQ) {

   623         memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));

   624         memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));

   625     }

   626 

   627     i = bank_number(old_mode);

   628     env->banked_r13[i] = env->regs[13];

   629     env->banked_r14[i] = env->regs[14];

   630     env->banked_spsr[i] = env->spsr;

   631 

   632     i = bank_number(mode);

   633     env->regs[13] = env->banked_r13[i];

   634     env->regs[14] = env->banked_r14[i];

   635     env->spsr = env->banked_spsr[i];

   636 }

   637 

   638 static void v7m_push(CPUARMState *env, uint32_t val)

   639 {

   640     env->regs[13] -= 4;

   641     stl_phys(env->regs[13], val);

   642 }

   643 

   644 static uint32_t v7m_pop(CPUARMState *env)

   645 {

   646     uint32_t val;

   647     val = ldl_phys(env->regs[13]);

   648     env->regs[13] += 4;

   649     return val;

   650 }

   651 

   652 /* Switch to V7M main or process stack pointer.  */

   653 static void switch_v7m_sp(CPUARMState *env, int process)

   654 {

   655     uint32_t tmp;

   656     if (env->v7m.current_sp != process) {

   657         tmp = env->v7m.other_sp;

   658         env->v7m.other_sp = env->regs[13];

   659         env->regs[13] = tmp;

   660         env->v7m.current_sp = process;

   661     }

   662 }

   663 

   664 static void do_v7m_exception_exit(CPUARMState *env)

   665 {

   666     uint32_t type;

   667     uint32_t xpsr;

   668 

   669     type = env->regs[15];

   670     if (env->v7m.exception != 0)

   671         armv7m_nvic_complete_irq(env->v7m.nvic, env->v7m.exception);

   672 

   673     /* Switch to the target stack.  */

   674     switch_v7m_sp(env, (type & 4) != 0);

   675     /* Pop registers.  */

   676     env->regs[0] = v7m_pop(env);

   677     env->regs[1] = v7m_pop(env);

   678     env->regs[2] = v7m_pop(env);

   679     env->regs[3] = v7m_pop(env);

   680     env->regs[12] = v7m_pop(env);

   681     env->regs[14] = v7m_pop(env);

   682     env->regs[15] = v7m_pop(env);

   683     xpsr = v7m_pop(env);

   684     xpsr_write(env, xpsr, 0xfffffdff);

   685     /* Undo stack alignment.  */

   686     if (xpsr & 0x200)

   687         env->regs[13] |= 4;

   688     /* ??? The exception return type specifies Thread/Handler mode.  However

   689        this is also implied by the xPSR value. Not sure what to do

   690        if there is a mismatch.  */

   691     /* ??? Likewise for mismatches between the CONTROL register and the stack

   692        pointer.  */

   693 }

   694 

   695 void do_interrupt_v7m(CPUARMState *env)

   696 {

   697     uint32_t xpsr = xpsr_read(env);

   698     uint32_t lr;

   699     uint32_t addr;

   700 

   701     lr = 0xfffffff1;

   702     if (env->v7m.current_sp)

   703         lr |= 4;

   704     if (env->v7m.exception == 0)

   705         lr |= 8;

   706 

   707     /* For exceptions we just mark as pending on the NVIC, and let that

   708        handle it.  */

   709     /* TODO: Need to escalate if the current priority is higher than the

   710        one we're raising.  */

   711     switch (env->exception_index) {

   712     case EXCP_UDEF:

   713         armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_USAGE);

   714         return;

   715     case EXCP_SWI:

   716         env->regs[15] += 2;

   717         armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_SVC);

   718         return;

   719     case EXCP_PREFETCH_ABORT:

   720     case EXCP_DATA_ABORT:

   721         armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_MEM);

   722         return;

   723     case EXCP_BKPT:

   724         if (semihosting_enabled) {

   725             int nr;

   726             nr = lduw_code(env->regs[15]) & 0xff;

   727             if (nr == 0xab) {

   728                 env->regs[15] += 2;

   729                 env->regs[0] = do_arm_semihosting(env);

   730                 return;

   731             }

   732         }

   733         armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_DEBUG);

   734         return;

   735     case EXCP_IRQ:

   736         env->v7m.exception = armv7m_nvic_acknowledge_irq(env->v7m.nvic);

   737         break;

   738     case EXCP_EXCEPTION_EXIT:

   739         do_v7m_exception_exit(env);

   740         return;

   741     default:

   742         cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);

   743         return; /* Never happens.  Keep compiler happy.  */

   744     }

   745 

   746     /* Align stack pointer.  */

   747     /* ??? Should only do this if Configuration Control Register

   748        STACKALIGN bit is set.  */

   749     if (env->regs[13] & 4) {

   750         env->regs[13] -= 4;

   751         xpsr |= 0x200;

   752     }

   753     /* Switch to the handler mode.  */

   754     v7m_push(env, xpsr);

   755     v7m_push(env, env->regs[15]);

   756     v7m_push(env, env->regs[14]);

   757     v7m_push(env, env->regs[12]);

   758     v7m_push(env, env->regs[3]);

   759     v7m_push(env, env->regs[2]);

   760     v7m_push(env, env->regs[1]);

   761     v7m_push(env, env->regs[0]);

   762     switch_v7m_sp(env, 0);

   763     env->uncached_cpsr &= ~CPSR_IT;

   764     env->regs[14] = lr;

   765     addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);

   766     env->regs[15] = addr & 0xfffffffe;

   767     env->thumb = addr & 1;

   768 }

   769 

   770 /* Handle a CPU exception.  */

   771 void do_interrupt(CPUARMState *env)

   772 {

   773     uint32_t addr;

   774     uint32_t mask;

   775     int new_mode;

   776     uint32_t offset;

   777 

   778     if (IS_M(env)) {

   779         do_interrupt_v7m(env);

   780         return;

   781     }

   782     /* TODO: Vectored interrupt controller.  */

   783     switch (env->exception_index) {

   784     case EXCP_UDEF:

   785         new_mode = ARM_CPU_MODE_UND;

   786         addr = 0x04;

   787         mask = CPSR_I;

   788         if (env->thumb)

   789             offset = 2;

   790         else

   791             offset = 4;

   792         break;

   793     case EXCP_SWI:

   794         if (semihosting_enabled) {

   795             /* Check for semihosting interrupt.  */

   796             if (env->thumb) {

   797                 mask = lduw_code(env->regs[15] - 2) & 0xff;

   798             } else {

   799                 mask = ldl_code(env->regs[15] - 4) & 0xffffff;

   800             }

   801             /* Only intercept calls from privileged modes, to provide some

   802                semblance of security.  */

   803             if (((mask == 0x123456 && !env->thumb)

   804                     || (mask == 0xab && env->thumb))

   805                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {

   806                 env->regs[0] = do_arm_semihosting(env);

   807                 return;

   808             }

   809         }

   810         new_mode = ARM_CPU_MODE_SVC;

   811         addr = 0x08;

   812         mask = CPSR_I;

   813         /* The PC already points to the next instruction.  */

   814         offset = 0;

   815         break;

   816     case EXCP_BKPT:

   817         /* See if this is a semihosting syscall.  */

   818         if (env->thumb && semihosting_enabled) {

   819             mask = lduw_code(env->regs[15]) & 0xff;

   820             if (mask == 0xab

   821                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {

   822                 env->regs[15] += 2;

   823                 env->regs[0] = do_arm_semihosting(env);

   824                 return;

   825             }

   826         }

   827         /* Fall through to prefetch abort.  */

   828     case EXCP_PREFETCH_ABORT:

   829         new_mode = ARM_CPU_MODE_ABT;

   830         addr = 0x0c;

   831         mask = CPSR_A | CPSR_I;

   832         offset = 4;

   833         break;

   834     case EXCP_DATA_ABORT:

   835         new_mode = ARM_CPU_MODE_ABT;

   836         addr = 0x10;

   837         mask = CPSR_A | CPSR_I;

   838         offset = 8;

   839         break;

   840     case EXCP_IRQ:

   841         new_mode = ARM_CPU_MODE_IRQ;

   842         addr = 0x18;

   843         /* Disable IRQ and imprecise data aborts.  */

   844         mask = CPSR_A | CPSR_I;

   845         offset = 4;

   846         break;

   847     case EXCP_FIQ:

   848         new_mode = ARM_CPU_MODE_FIQ;

   849         addr = 0x1c;

   850         /* Disable FIQ, IRQ and imprecise data aborts.  */

   851         mask = CPSR_A | CPSR_I | CPSR_F;

   852         offset = 4;

   853         break;

   854     default:

   855         cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);

   856         return; /* Never happens.  Keep compiler happy.  */

   857     }

   858     /* High vectors.  */

   859     if (env->cp15.c1_sys & (1 << 13)) {

   860         addr += 0xffff0000;

   861     } else {

   862         addr += env->cp15.c12_vbar;

   863     }

   864     switch_mode (env, new_mode);

   865     env->spsr = cpsr_read(env);

   866     /* Clear IT bits.  */

   867     env->condexec_bits = 0;

   868     /* Switch to the new mode, and switch to Arm mode.  */

   869     /* ??? Thumb interrupt handlers not implemented.  */

   870     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;

   871     env->uncached_cpsr |= mask;

   872     env->thumb = 0;

   873     env->regs[14] = env->regs[15] + offset;

   874     env->regs[15] = addr;

   875     env->interrupt_request |= CPU_INTERRUPT_EXITTB;

   876 }

   877 

   878 /* Check section/page access permissions.

   879    Returns the page protection flags, or zero if the access is not

   880    permitted.  */

   881 static inline int check_ap(CPUState *env, int ap, int domain, int access_type,

   882                            int is_user)

   883 {

   884   int prot_ro;

   885 

   886   if (domain == 3)

   887     return PAGE_READ | PAGE_WRITE;

   888 

   889   if (access_type == 1)

   890       prot_ro = 0;

   891   else

   892       prot_ro = PAGE_READ;

   893 

   894   switch (ap) {

   895   case 0:

   896       if (access_type == 1)

   897           return 0;

   898       switch ((env->cp15.c1_sys >> 8) & 3) {

   899       case 1:

   900           return is_user ? 0 : PAGE_READ;

   901       case 2:

   902           return PAGE_READ;

   903       default:

   904           return 0;

   905       }

   906   case 1:

   907       return is_user ? 0 : PAGE_READ | PAGE_WRITE;

   908   case 2:

   909       if (is_user)

   910           return prot_ro;

   911       else

   912           return PAGE_READ | PAGE_WRITE;

   913   case 3:

   914       return PAGE_READ | PAGE_WRITE;

   915   case 4: /* Reserved.  */

   916       return 0;

   917   case 5:

   918       return is_user ? 0 : prot_ro;

   919   case 6:

   920       return prot_ro;

   921   case 7:

   922       if (!arm_feature (env, ARM_FEATURE_V7))

   923           return 0;

   924       return prot_ro;

   925   default:

   926       abort();

   927   }

   928 }

   929 

   930 static uint32_t get_level1_table_address(CPUState *env, uint32_t address)

   931 {

   932     uint32_t table;

   933 

   934     if (address & env->cp15.c2_mask)

   935         table = env->cp15.c2_base1 & 0xffffc000;

   936     else

   937         table = env->cp15.c2_base0 & env->cp15.c2_base_mask;

   938 

   939     table |= (address >> 18) & 0x3ffc;

   940     return table;

   941 }

   942 

   943 static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,

   944 			    int is_user, uint32_t *phys_ptr, int *prot)

   945 {

   946     int code;

   947     uint32_t table;

   948     uint32_t desc;

   949     int type;

   950     int ap;

   951     int domain;

   952     uint32_t phys_addr;

   953 

   954     /* Pagetable walk.  */

   955     /* Lookup l1 descriptor.  */

   956     table = get_level1_table_address(env, address);

   957     desc = ldl_phys(table);

   958     type = (desc & 3);

   959     domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;

   960     if (type == 0) {

   961         /* Section translation fault.  */

   962         code = 5;

   963         goto do_fault;

   964     }

   965     if (domain == 0 || domain == 2) {

   966         if (type == 2)

   967             code = 9; /* Section domain fault.  */

   968         else

   969             code = 11; /* Page domain fault.  */

   970         goto do_fault;

   971     }

   972     if (type == 2) {

   973         /* 1Mb section.  */

   974         phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);

   975         ap = (desc >> 10) & 3;

   976         code = 13;

   977     } else {

   978         /* Lookup l2 entry.  */

   979 	if (type == 1) {

   980 	    /* Coarse pagetable.  */

   981 	    table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);

   982 	} else {

   983 	    /* Fine pagetable.  */

   984 	    table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);

   985 	}

   986         desc = ldl_phys(table);

   987         switch (desc & 3) {

   988         case 0: /* Page translation fault.  */

   989             code = 7;

   990             goto do_fault;

   991         case 1: /* 64k page.  */

   992             phys_addr = (desc & 0xffff0000) | (address & 0xffff);

   993             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;

   994             break;

   995         case 2: /* 4k page.  */

   996             phys_addr = (desc & 0xfffff000) | (address & 0xfff);

   997             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;

   998             break;

   999         case 3: /* 1k page.  */

  1000 	    if (type == 1) {

  1001 		if (arm_feature(env, ARM_FEATURE_XSCALE)) {

  1002 		    phys_addr = (desc & 0xfffff000) | (address & 0xfff);

  1003 		} else {

  1004 		    /* Page translation fault.  */

  1005 		    code = 7;

  1006 		    goto do_fault;

  1007 		}

  1008 	    } else {

  1009 		phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);

  1010 	    }

  1011             ap = (desc >> 4) & 3;

  1012             break;

  1013         default:

  1014             /* Never happens, but compiler isn't smart enough to tell.  */

  1015             abort();

  1016         }

  1017         code = 15;

  1018     }

  1019     *prot = check_ap(env, ap, domain, access_type, is_user);

  1020     if (!*prot) {

  1021         /* Access permission fault.  */

  1022         goto do_fault;

  1023     }

  1024     *phys_ptr = phys_addr;

  1025     return 0;

  1026 do_fault:

  1027     return code | (domain << 4);

  1028 }

  1029 

  1030 static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,

  1031 			    int is_user, uint32_t *phys_ptr, int *prot)

  1032 {

  1033     int code;

  1034     uint32_t table;

  1035     uint32_t desc;

  1036     uint32_t xn;

  1037     int type;

  1038     int ap;

  1039     int domain;

  1040     uint32_t phys_addr;

  1041 

  1042     /* Pagetable walk.  */

  1043     /* Lookup l1 descriptor.  */

  1044     table = get_level1_table_address(env, address);

  1045     desc = ldl_phys(table);

  1046     type = (desc & 3);

  1047     if (type == 0) {

  1048         /* Section translation fault.  */

  1049         code = 5;

  1050         domain = 0;

  1051         goto do_fault;

  1052     } else if (type == 2 && (desc & (1 << 18))) {

  1053         /* Supersection.  */

  1054         domain = 0;

  1055     } else {

  1056         /* Section or page.  */

  1057         domain = (desc >> 4) & 0x1e;

  1058     }

  1059     domain = (env->cp15.c3 >> domain) & 3;

  1060     if (domain == 0 || domain == 2) {

  1061         if (type == 2)

  1062             code = 9; /* Section domain fault.  */

  1063         else

  1064             code = 11; /* Page domain fault.  */

  1065         goto do_fault;

  1066     }

  1067     if (type == 2) {

  1068         if (desc & (1 << 18)) {

  1069             /* Supersection.  */

  1070             phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);

  1071         } else {

  1072             /* Section.  */

  1073             phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);

  1074         }

  1075         ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);

  1076         xn = desc & (1 << 4);

  1077         code = 13;

  1078     } else {

  1079         /* Lookup l2 entry.  */

  1080         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);

  1081         desc = ldl_phys(table);

  1082         ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);

  1083         switch (desc & 3) {

  1084         case 0: /* Page translation fault.  */

  1085             code = 7;

  1086             goto do_fault;

  1087         case 1: /* 64k page.  */

  1088             phys_addr = (desc & 0xffff0000) | (address & 0xffff);

  1089             xn = desc & (1 << 15);

  1090             break;

  1091         case 2: case 3: /* 4k page.  */

  1092             phys_addr = (desc & 0xfffff000) | (address & 0xfff);

  1093             xn = desc & 1;

  1094             break;

  1095         default:

  1096             /* Never happens, but compiler isn't smart enough to tell.  */

  1097             abort();

  1098         }

  1099         code = 15;

  1100     }

  1101     if (xn && access_type == 2)

  1102         goto do_fault;

  1103 

  1104     /* The simplified model uses AP[0] as an access control bit.  */

  1105     if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {

  1106         /* Access flag fault.  */

  1107         code = (code == 15) ? 6 : 3;

  1108         goto do_fault;

  1109     }

  1110     *prot = check_ap(env, ap, domain, access_type, is_user);

  1111     if (!*prot) {

  1112         /* Access permission fault.  */

  1113         goto do_fault;

  1114     }

  1115     *phys_ptr = phys_addr;

  1116     return 0;

  1117 do_fault:

  1118     return code | (domain << 4);

  1119 }

  1120 

  1121 static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type,

  1122 			     int is_user, uint32_t *phys_ptr, int *prot)

  1123 {

  1124     int n;

  1125     uint32_t mask;

  1126     uint32_t base;

  1127 

  1128     *phys_ptr = address;

  1129     for (n = 7; n >= 0; n--) {

  1130 	base = env->cp15.c6_region[n];

  1131 	if ((base & 1) == 0)

  1132 	    continue;

  1133 	mask = 1 << ((base >> 1) & 0x1f);

  1134 	/* Keep this shift separate from the above to avoid an

  1135 	   (undefined) << 32.  */