1 /*

     2  *  i386 translation

     3  *

     4  *  Copyright (c) 2003 Fabrice Bellard

     5  *

     6  * This library is free software; you can redistribute it and/or

     7  * modify it under the terms of the GNU Lesser General Public

     8  * License as published by the Free Software Foundation; either

     9  * version 2 of the License, or (at your option) any later version.

    10  *

    11  * This library is distributed in the hope that it will be useful,

    12  * but WITHOUT ANY WARRANTY; without even the implied warranty of

    13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

    14  * Lesser General Public License for more details.

    15  *

    16  * You should have received a copy of the GNU Lesser General Public

    17  * License along with this library; if not, write to the Free Software

    18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

    19  */

    20 #include <stdarg.h>

    21 #include <stdlib.h>

    22 #include <stdio.h>

    23 #include <string.h>

    24 #include <inttypes.h>

    25 #include <signal.h>

    26 #include <assert.h>

    27 

    28 #include "cpu.h"

    29 #include "exec-all.h"

    30 #include "disas.h"

    31 #include "tcg-op.h"

    32 

    33 #include "helper.h"

    34 #define GEN_HELPER 1

    35 #include "helper.h"

    36 

    37 #define PREFIX_REPZ   0x01

    38 #define PREFIX_REPNZ  0x02

    39 #define PREFIX_LOCK   0x04

    40 #define PREFIX_DATA   0x08

    41 #define PREFIX_ADR    0x10

    42 

    43 #ifdef TARGET_X86_64

    44 #define X86_64_ONLY(x) x

    45 #define X86_64_DEF(x...) x

    46 #define CODE64(s) ((s)->code64)

    47 #define REX_X(s) ((s)->rex_x)

    48 #define REX_B(s) ((s)->rex_b)

    49 /* XXX: gcc generates push/pop in some opcodes, so we cannot use them */

    50 #if 1

    51 #define BUGGY_64(x) NULL

    52 #endif

    53 #else

    54 #define X86_64_ONLY(x) NULL

    55 #define X86_64_DEF(x...)

    56 #define CODE64(s) 0

    57 #define REX_X(s) 0

    58 #define REX_B(s) 0

    59 #endif

    60 

    61 //#define MACRO_TEST   1

    62 

    63 /* global register indexes */

    64 static TCGv_ptr cpu_env;

    65 static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst, cpu_cc_tmp;

    66 static TCGv_i32 cpu_cc_op;

    67 /* local temps */

    68 static TCGv cpu_T[2], cpu_T3;

    69 /* local register indexes (only used inside old micro ops) */

    70 static TCGv cpu_tmp0, cpu_tmp4;

    71 static TCGv_ptr cpu_ptr0, cpu_ptr1;

    72 static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32;

    73 static TCGv_i64 cpu_tmp1_i64;

    74 static TCGv cpu_tmp5, cpu_tmp6;

    75 

    76 #include "gen-icount.h"

    77 

    78 #ifdef TARGET_X86_64

    79 static int x86_64_hregs;

    80 #endif

    81 

    82 typedef struct DisasContext {

    83     /* current insn context */

    84     int override; /* -1 if no override */

    85     int prefix;

    86     int aflag, dflag;

    87     target_ulong pc; /* pc = eip + cs_base */

    88     int is_jmp; /* 1 = means jump (stop translation), 2 means CPU

    89                    static state change (stop translation) */

    90     /* current block context */

    91     target_ulong cs_base; /* base of CS segment */

    92     int pe;     /* protected mode */

    93     int code32; /* 32 bit code segment */

    94 #ifdef TARGET_X86_64

    95     int lma;    /* long mode active */

    96     int code64; /* 64 bit code segment */

    97     int rex_x, rex_b;

    98 #endif

    99     int ss32;   /* 32 bit stack segment */

   100     int cc_op;  /* current CC operation */

   101     int addseg; /* non zero if either DS/ES/SS have a non zero base */

   102     int f_st;   /* currently unused */

   103     int vm86;   /* vm86 mode */

   104     int cpl;

   105     int iopl;

   106     int tf;     /* TF cpu flag */

   107     int singlestep_enabled; /* "hardware" single step enabled */

   108     int jmp_opt; /* use direct block chaining for direct jumps */

   109     int mem_index; /* select memory access functions */

   110     uint64_t flags; /* all execution flags */

   111     struct TranslationBlock *tb;

   112     int popl_esp_hack; /* for correct popl with esp base handling */

   113     int rip_offset; /* only used in x86_64, but left for simplicity */

   114     int cpuid_features;

   115     int cpuid_ext_features;

   116     int cpuid_ext2_features;

   117     int cpuid_ext3_features;

   118 } DisasContext;

   119 

   120 static void gen_eob(DisasContext *s);

   121 static void gen_jmp(DisasContext *s, target_ulong eip);

   122 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);

   123 

   124 /* i386 arith/logic operations */

   125 enum {

   126     OP_ADDL,

   127     OP_ORL,

   128     OP_ADCL,

   129     OP_SBBL,

   130     OP_ANDL,

   131     OP_SUBL,

   132     OP_XORL,

   133     OP_CMPL,

   134 };

   135 

   136 /* i386 shift ops */

   137 enum {

   138     OP_ROL,

   139     OP_ROR,

   140     OP_RCL,

   141     OP_RCR,

   142     OP_SHL,

   143     OP_SHR,

   144     OP_SHL1, /* undocumented */

   145     OP_SAR = 7,

   146 };

   147 

   148 enum {

   149     JCC_O,

   150     JCC_B,

   151     JCC_Z,

   152     JCC_BE,

   153     JCC_S,

   154     JCC_P,

   155     JCC_L,

   156     JCC_LE,

   157 };

   158 

   159 /* operand size */

   160 enum {

   161     OT_BYTE = 0,

   162     OT_WORD,

   163     OT_LONG,

   164     OT_QUAD,

   165 };

   166 

   167 enum {

   168     /* I386 int registers */

   169     OR_EAX,   /* MUST be even numbered */

   170     OR_ECX,

   171     OR_EDX,

   172     OR_EBX,

   173     OR_ESP,

   174     OR_EBP,

   175     OR_ESI,

   176     OR_EDI,

   177 

   178     OR_TMP0 = 16,    /* temporary operand register */

   179     OR_TMP1,

   180     OR_A0, /* temporary register used when doing address evaluation */

   181 };

   182 

   183 static inline void gen_op_movl_T0_0(void)

   184 {

   185     tcg_gen_movi_tl(cpu_T[0], 0);

   186 }

   187 

   188 static inline void gen_op_movl_T0_im(int32_t val)

   189 {

   190     tcg_gen_movi_tl(cpu_T[0], val);

   191 }

   192 

   193 static inline void gen_op_movl_T0_imu(uint32_t val)

   194 {

   195     tcg_gen_movi_tl(cpu_T[0], val);

   196 }

   197 

   198 static inline void gen_op_movl_T1_im(int32_t val)

   199 {

   200     tcg_gen_movi_tl(cpu_T[1], val);

   201 }

   202 

   203 static inline void gen_op_movl_T1_imu(uint32_t val)

   204 {

   205     tcg_gen_movi_tl(cpu_T[1], val);

   206 }

   207 

   208 static inline void gen_op_movl_A0_im(uint32_t val)

   209 {

   210     tcg_gen_movi_tl(cpu_A0, val);

   211 }

   212 

   213 #ifdef TARGET_X86_64

   214 static inline void gen_op_movq_A0_im(int64_t val)

   215 {

   216     tcg_gen_movi_tl(cpu_A0, val);

   217 }

   218 #endif

   219 

   220 static inline void gen_movtl_T0_im(target_ulong val)

   221 {

   222     tcg_gen_movi_tl(cpu_T[0], val);

   223 }

   224 

   225 static inline void gen_movtl_T1_im(target_ulong val)

   226 {

   227     tcg_gen_movi_tl(cpu_T[1], val);

   228 }

   229 

   230 static inline void gen_op_andl_T0_ffff(void)

   231 {

   232     tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);

   233 }

   234 

   235 static inline void gen_op_andl_T0_im(uint32_t val)

   236 {

   237     tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);

   238 }

   239 

   240 static inline void gen_op_movl_T0_T1(void)

   241 {

   242     tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);

   243 }

   244 

   245 static inline void gen_op_andl_A0_ffff(void)

   246 {

   247     tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);

   248 }

   249 

   250 #ifdef TARGET_X86_64

   251 

   252 #define NB_OP_SIZES 4

   253 

   254 #else /* !TARGET_X86_64 */

   255 

   256 #define NB_OP_SIZES 3

   257 

   258 #endif /* !TARGET_X86_64 */

   259 

   260 #if defined(WORDS_BIGENDIAN)

   261 #define REG_B_OFFSET (sizeof(target_ulong) - 1)

   262 #define REG_H_OFFSET (sizeof(target_ulong) - 2)

   263 #define REG_W_OFFSET (sizeof(target_ulong) - 2)

   264 #define REG_L_OFFSET (sizeof(target_ulong) - 4)

   265 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)

   266 #else

   267 #define REG_B_OFFSET 0

   268 #define REG_H_OFFSET 1

   269 #define REG_W_OFFSET 0

   270 #define REG_L_OFFSET 0

   271 #define REG_LH_OFFSET 4

   272 #endif

   273 

   274 static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)

   275 {

   276     switch(ot) {

   277     case OT_BYTE:

   278         if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {

   279             tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_B_OFFSET);

   280         } else {

   281             tcg_gen_st8_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);

   282         }

   283         break;

   284     case OT_WORD:

   285         tcg_gen_st16_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);

   286         break;

   287 #ifdef TARGET_X86_64

   288     case OT_LONG:

   289         tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);

   290         /* high part of register set to zero */

   291         tcg_gen_movi_tl(cpu_tmp0, 0);

   292         tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);

   293         break;

   294     default:

   295     case OT_QUAD:

   296         tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, regs[reg]));

   297         break;

   298 #else

   299     default:

   300     case OT_LONG:

   301         tcg_gen_st32_tl(t0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);

   302         break;

   303 #endif

   304     }

   305 }

   306 

   307 static inline void gen_op_mov_reg_T0(int ot, int reg)

   308 {

   309     gen_op_mov_reg_v(ot, reg, cpu_T[0]);

   310 }

   311 

   312 static inline void gen_op_mov_reg_T1(int ot, int reg)

   313 {

   314     gen_op_mov_reg_v(ot, reg, cpu_T[1]);

   315 }

   316 

   317 static inline void gen_op_mov_reg_A0(int size, int reg)

   318 {

   319     switch(size) {

   320     case 0:

   321         tcg_gen_st16_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);

   322         break;

   323 #ifdef TARGET_X86_64

   324     case 1:

   325         tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);

   326         /* high part of register set to zero */

   327         tcg_gen_movi_tl(cpu_tmp0, 0);

   328         tcg_gen_st32_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_LH_OFFSET);

   329         break;

   330     default:

   331     case 2:

   332         tcg_gen_st_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]));

   333         break;

   334 #else

   335     default:

   336     case 1:

   337         tcg_gen_st32_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);

   338         break;

   339 #endif

   340     }

   341 }

   342 

   343 static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)

   344 {

   345     switch(ot) {

   346     case OT_BYTE:

   347         if (reg < 4 X86_64_DEF( || reg >= 8 || x86_64_hregs)) {

   348             goto std_case;

   349         } else {

   350             tcg_gen_ld8u_tl(t0, cpu_env, offsetof(CPUState, regs[reg - 4]) + REG_H_OFFSET);

   351         }

   352         break;

   353     default:

   354     std_case:

   355         tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, regs[reg]));

   356         break;

   357     }

   358 }

   359 

   360 static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)

   361 {

   362     gen_op_mov_v_reg(ot, cpu_T[t_index], reg);

   363 }

   364 

   365 static inline void gen_op_movl_A0_reg(int reg)

   366 {

   367     tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]) + REG_L_OFFSET);

   368 }

   369 

   370 static inline void gen_op_addl_A0_im(int32_t val)

   371 {

   372     tcg_gen_addi_tl(cpu_A0, cpu_A0, val);

   373 #ifdef TARGET_X86_64

   374     tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);

   375 #endif

   376 }

   377 

   378 #ifdef TARGET_X86_64

   379 static inline void gen_op_addq_A0_im(int64_t val)

   380 {

   381     tcg_gen_addi_tl(cpu_A0, cpu_A0, val);

   382 }

   383 #endif

   384     

   385 static void gen_add_A0_im(DisasContext *s, int val)

   386 {

   387 #ifdef TARGET_X86_64

   388     if (CODE64(s))

   389         gen_op_addq_A0_im(val);

   390     else

   391 #endif

   392         gen_op_addl_A0_im(val);

   393 }

   394 

   395 static inline void gen_op_addl_T0_T1(void)

   396 {

   397     tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);

   398 }

   399 

   400 static inline void gen_op_jmp_T0(void)

   401 {

   402     tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, eip));

   403 }

   404 

   405 static inline void gen_op_add_reg_im(int size, int reg, int32_t val)

   406 {

   407     switch(size) {

   408     case 0:

   409         tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));

   410         tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);

   411         tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);

   412         break;

   413     case 1:

   414         tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));

   415         tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);

   416 #ifdef TARGET_X86_64

   417         tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff);

   418 #endif

   419         tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));

   420         break;

   421 #ifdef TARGET_X86_64

   422     case 2:

   423         tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));

   424         tcg_gen_addi_tl(cpu_tmp0, cpu_tmp0, val);

   425         tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));

   426         break;

   427 #endif

   428     }

   429 }

   430 

   431 static inline void gen_op_add_reg_T0(int size, int reg)

   432 {

   433     switch(size) {

   434     case 0:

   435         tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));

   436         tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);

   437         tcg_gen_st16_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]) + REG_W_OFFSET);

   438         break;

   439     case 1:

   440         tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));

   441         tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);

   442 #ifdef TARGET_X86_64

   443         tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffff);

   444 #endif

   445         tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));

   446         break;

   447 #ifdef TARGET_X86_64

   448     case 2:

   449         tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));

   450         tcg_gen_add_tl(cpu_tmp0, cpu_tmp0, cpu_T[0]);

   451         tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));

   452         break;

   453 #endif

   454     }

   455 }

   456 

   457 static inline void gen_op_set_cc_op(int32_t val)

   458 {

   459     tcg_gen_movi_i32(cpu_cc_op, val);

   460 }

   461 

   462 static inline void gen_op_addl_A0_reg_sN(int shift, int reg)

   463 {

   464     tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));

   465     if (shift != 0) 

   466         tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);

   467     tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);

   468 #ifdef TARGET_X86_64

   469     tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);

   470 #endif

   471 }

   472 

   473 static inline void gen_op_movl_A0_seg(int reg)

   474 {

   475     tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base) + REG_L_OFFSET);

   476 }

   477 

   478 static inline void gen_op_addl_A0_seg(int reg)

   479 {

   480     tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));

   481     tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);

   482 #ifdef TARGET_X86_64

   483     tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);

   484 #endif

   485 }

   486 

   487 #ifdef TARGET_X86_64

   488 static inline void gen_op_movq_A0_seg(int reg)

   489 {

   490     tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, segs[reg].base));

   491 }

   492 

   493 static inline void gen_op_addq_A0_seg(int reg)

   494 {

   495     tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, segs[reg].base));

   496     tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);

   497 }

   498 

   499 static inline void gen_op_movq_A0_reg(int reg)

   500 {

   501     tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUState, regs[reg]));

   502 }

   503 

   504 static inline void gen_op_addq_A0_reg_sN(int shift, int reg)

   505 {

   506     tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg]));

   507     if (shift != 0) 

   508         tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);

   509     tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);

   510 }

   511 #endif

   512 

   513 static inline void gen_op_lds_T0_A0(int idx)

   514 {

   515     int mem_index = (idx >> 2) - 1;

   516     switch(idx & 3) {

   517     case 0:

   518         tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);

   519         break;

   520     case 1:

   521         tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);

   522         break;

   523     default:

   524     case 2:

   525         tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);

   526         break;

   527     }

   528 }

   529 

   530 static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0)

   531 {

   532     int mem_index = (idx >> 2) - 1;

   533     switch(idx & 3) {

   534     case 0:

   535         tcg_gen_qemu_ld8u(t0, a0, mem_index);

   536         break;

   537     case 1:

   538         tcg_gen_qemu_ld16u(t0, a0, mem_index);

   539         break;

   540     case 2:

   541         tcg_gen_qemu_ld32u(t0, a0, mem_index);

   542         break;

   543     default:

   544     case 3:

   545         /* Should never happen on 32-bit targets.  */

   546 #ifdef TARGET_X86_64

   547         tcg_gen_qemu_ld64(t0, a0, mem_index);

   548 #endif

   549         break;

   550     }

   551 }

   552 

   553 /* XXX: always use ldu or lds */

   554 static inline void gen_op_ld_T0_A0(int idx)

   555 {

   556     gen_op_ld_v(idx, cpu_T[0], cpu_A0);

   557 }

   558 

   559 static inline void gen_op_ldu_T0_A0(int idx)

   560 {

   561     gen_op_ld_v(idx, cpu_T[0], cpu_A0);

   562 }

   563 

   564 static inline void gen_op_ld_T1_A0(int idx)

   565 {

   566     gen_op_ld_v(idx, cpu_T[1], cpu_A0);

   567 }

   568 

   569 static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0)

   570 {

   571     int mem_index = (idx >> 2) - 1;

   572     switch(idx & 3) {

   573     case 0:

   574         tcg_gen_qemu_st8(t0, a0, mem_index);

   575         break;

   576     case 1:

   577         tcg_gen_qemu_st16(t0, a0, mem_index);

   578         break;

   579     case 2:

   580         tcg_gen_qemu_st32(t0, a0, mem_index);

   581         break;

   582     default:

   583     case 3:

   584         /* Should never happen on 32-bit targets.  */

   585 #ifdef TARGET_X86_64

   586         tcg_gen_qemu_st64(t0, a0, mem_index);

   587 #endif

   588         break;

   589     }

   590 }

   591 

   592 static inline void gen_op_st_T0_A0(int idx)

   593 {

   594     gen_op_st_v(idx, cpu_T[0], cpu_A0);

   595 }

   596 

   597 static inline void gen_op_st_T1_A0(int idx)

   598 {

   599     gen_op_st_v(idx, cpu_T[1], cpu_A0);

   600 }

   601 

   602 static inline void gen_jmp_im(target_ulong pc)

   603 {

   604     tcg_gen_movi_tl(cpu_tmp0, pc);

   605     tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUState, eip));

   606 }

   607 

   608 static inline void gen_string_movl_A0_ESI(DisasContext *s)

   609 {

   610     int override;

   611 

   612     override = s->override;

   613 #ifdef TARGET_X86_64

   614     if (s->aflag == 2) {

   615         if (override >= 0) {

   616             gen_op_movq_A0_seg(override);

   617             gen_op_addq_A0_reg_sN(0, R_ESI);

   618         } else {

   619             gen_op_movq_A0_reg(R_ESI);

   620         }

   621     } else

   622 #endif

   623     if (s->aflag) {

   624         /* 32 bit address */

   625         if (s->addseg && override < 0)

   626             override = R_DS;

   627         if (override >= 0) {

   628             gen_op_movl_A0_seg(override);

   629             gen_op_addl_A0_reg_sN(0, R_ESI);

   630         } else {

   631             gen_op_movl_A0_reg(R_ESI);

   632         }

   633     } else {

   634         /* 16 address, always override */

   635         if (override < 0)

   636             override = R_DS;

   637         gen_op_movl_A0_reg(R_ESI);

   638         gen_op_andl_A0_ffff();

   639         gen_op_addl_A0_seg(override);

   640     }

   641 }

   642 

   643 static inline void gen_string_movl_A0_EDI(DisasContext *s)

   644 {

   645 #ifdef TARGET_X86_64

   646     if (s->aflag == 2) {

   647         gen_op_movq_A0_reg(R_EDI);

   648     } else

   649 #endif

   650     if (s->aflag) {

   651         if (s->addseg) {

   652             gen_op_movl_A0_seg(R_ES);

   653             gen_op_addl_A0_reg_sN(0, R_EDI);

   654         } else {

   655             gen_op_movl_A0_reg(R_EDI);

   656         }

   657     } else {

   658         gen_op_movl_A0_reg(R_EDI);

   659         gen_op_andl_A0_ffff();

   660         gen_op_addl_A0_seg(R_ES);

   661     }

   662 }

   663 

   664 static inline void gen_op_movl_T0_Dshift(int ot) 

   665 {

   666     tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUState, df));

   667     tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);

   668 };

   669 

   670 static void gen_extu(int ot, TCGv reg)

   671 {

   672     switch(ot) {

   673     case OT_BYTE:

   674         tcg_gen_ext8u_tl(reg, reg);

   675         break;

   676     case OT_WORD:

   677         tcg_gen_ext16u_tl(reg, reg);

   678         break;

   679     case OT_LONG:

   680         tcg_gen_ext32u_tl(reg, reg);

   681         break;

   682     default:

   683         break;

   684     }

   685 }

   686 

   687 static void gen_exts(int ot, TCGv reg)

   688 {

   689     switch(ot) {

   690     case OT_BYTE:

   691         tcg_gen_ext8s_tl(reg, reg);

   692         break;

   693     case OT_WORD:

   694         tcg_gen_ext16s_tl(reg, reg);

   695         break;

   696     case OT_LONG:

   697         tcg_gen_ext32s_tl(reg, reg);

   698         break;

   699     default:

   700         break;

   701     }

   702 }

   703 

   704 static inline void gen_op_jnz_ecx(int size, int label1)

   705 {

   706     tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX]));

   707     gen_extu(size + 1, cpu_tmp0);

   708     tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1);

   709 }

   710 

   711 static inline void gen_op_jz_ecx(int size, int label1)

   712 {

   713     tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[R_ECX]));

   714     gen_extu(size + 1, cpu_tmp0);

   715     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);

   716 }

   717 

   718 static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)

   719 {

   720     switch (ot) {

   721     case 0: gen_helper_inb(v, n); break;

   722     case 1: gen_helper_inw(v, n); break;

   723     case 2: gen_helper_inl(v, n); break;

   724     }

   725 

   726 }

   727 

   728 static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n)

   729 {

   730     switch (ot) {

   731     case 0: gen_helper_outb(v, n); break;

   732     case 1: gen_helper_outw(v, n); break;

   733     case 2: gen_helper_outl(v, n); break;

   734     }

   735 

   736 }

   737 

   738 static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,

   739                          uint32_t svm_flags)

   740 {

   741     int state_saved;

   742     target_ulong next_eip;

   743 

   744     state_saved = 0;

   745     if (s->pe && (s->cpl > s->iopl || s->vm86)) {

   746         if (s->cc_op != CC_OP_DYNAMIC)

   747             gen_op_set_cc_op(s->cc_op);

   748         gen_jmp_im(cur_eip);

   749         state_saved = 1;

   750         tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);

   751         switch (ot) {

   752         case 0: gen_helper_check_iob(cpu_tmp2_i32); break;

   753         case 1: gen_helper_check_iow(cpu_tmp2_i32); break;

   754         case 2: gen_helper_check_iol(cpu_tmp2_i32); break;

   755         }

   756     }

   757     if(s->flags & HF_SVMI_MASK) {

   758         if (!state_saved) {

   759             if (s->cc_op != CC_OP_DYNAMIC)

   760                 gen_op_set_cc_op(s->cc_op);

   761             gen_jmp_im(cur_eip);

   762             state_saved = 1;

   763         }

   764         svm_flags |= (1 << (4 + ot));

   765         next_eip = s->pc - s->cs_base;

   766         tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);

   767         gen_helper_svm_check_io(cpu_tmp2_i32, tcg_const_i32(svm_flags),

   768                                 tcg_const_i32(next_eip - cur_eip));

   769     }

   770 }

   771 

   772 static inline void gen_movs(DisasContext *s, int ot)

   773 {

   774     gen_string_movl_A0_ESI(s);

   775     gen_op_ld_T0_A0(ot + s->mem_index);

   776     gen_string_movl_A0_EDI(s);

   777     gen_op_st_T0_A0(ot + s->mem_index);

   778     gen_op_movl_T0_Dshift(ot);

   779     gen_op_add_reg_T0(s->aflag, R_ESI);

   780     gen_op_add_reg_T0(s->aflag, R_EDI);

   781 }

   782 

   783 static inline void gen_update_cc_op(DisasContext *s)

   784 {

   785     if (s->cc_op != CC_OP_DYNAMIC) {

   786         gen_op_set_cc_op(s->cc_op);

   787         s->cc_op = CC_OP_DYNAMIC;

   788     }

   789 }

   790 

   791 static void gen_op_update1_cc(void)

   792 {

   793     tcg_gen_discard_tl(cpu_cc_src);

   794     tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);

   795 }

   796 

   797 static void gen_op_update2_cc(void)

   798 {

   799     tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);

   800     tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);

   801 }

   802 

   803 static inline void gen_op_cmpl_T0_T1_cc(void)

   804 {

   805     tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);

   806     tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);

   807 }

   808 

   809 static inline void gen_op_testl_T0_T1_cc(void)

   810 {

   811     tcg_gen_discard_tl(cpu_cc_src);

   812     tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);

   813 }

   814 

   815 static void gen_op_update_neg_cc(void)

   816 {

   817     tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);

   818     tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);

   819 }

   820 

   821 /* compute eflags.C to reg */

   822 static void gen_compute_eflags_c(TCGv reg)

   823 {

   824     gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_cc_op);

   825     tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);

   826 }

   827 

   828 /* compute all eflags to cc_src */

   829 static void gen_compute_eflags(TCGv reg)

   830 {

   831     gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_cc_op);

   832     tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);

   833 }

   834 

   835 static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op)

   836 {

   837     if (s->cc_op != CC_OP_DYNAMIC)

   838         gen_op_set_cc_op(s->cc_op);

   839     switch(jcc_op) {

   840     case JCC_O:

   841         gen_compute_eflags(cpu_T[0]);

   842         tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11);

   843         tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);

   844         break;

   845     case JCC_B:

   846         gen_compute_eflags_c(cpu_T[0]);

   847         break;

   848     case JCC_Z:

   849         gen_compute_eflags(cpu_T[0]);

   850         tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6);

   851         tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);

   852         break;

   853     case JCC_BE:

   854         gen_compute_eflags(cpu_tmp0);

   855         tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6);

   856         tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);

   857         tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);

   858         break;

   859     case JCC_S:

   860         gen_compute_eflags(cpu_T[0]);

   861         tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7);

   862         tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);

   863         break;

   864     case JCC_P:

   865         gen_compute_eflags(cpu_T[0]);

   866         tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2);

   867         tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);

   868         break;

   869     case JCC_L:

   870         gen_compute_eflags(cpu_tmp0);

   871         tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */

   872         tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */

   873         tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);

   874         tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);

   875         break;

   876     default:

   877     case JCC_LE:

   878         gen_compute_eflags(cpu_tmp0);

   879         tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */

   880         tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */

   881         tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */

   882         tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4);

   883         tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);

   884         tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);

   885         break;

   886     }

   887 }

   888 

   889 /* return true if setcc_slow is not needed (WARNING: must be kept in

   890    sync with gen_jcc1) */

   891 static int is_fast_jcc_case(DisasContext *s, int b)

   892 {

   893     int jcc_op;

   894     jcc_op = (b >> 1) & 7;

   895     switch(s->cc_op) {

   896         /* we optimize the cmp/jcc case */

   897     case CC_OP_SUBB:

   898     case CC_OP_SUBW:

   899     case CC_OP_SUBL:

   900     case CC_OP_SUBQ:

   901         if (jcc_op == JCC_O || jcc_op == JCC_P)

   902             goto slow_jcc;

   903         break;

   904 

   905         /* some jumps are easy to compute */

   906     case CC_OP_ADDB:

   907     case CC_OP_ADDW:

   908     case CC_OP_ADDL:

   909     case CC_OP_ADDQ:

   910 

   911     case CC_OP_LOGICB:

   912     case CC_OP_LOGICW:

   913     case CC_OP_LOGICL:

   914     case CC_OP_LOGICQ:

   915 

   916     case CC_OP_INCB:

   917     case CC_OP_INCW:

   918     case CC_OP_INCL:

   919     case CC_OP_INCQ:

   920 

   921     case CC_OP_DECB:

   922     case CC_OP_DECW:

   923     case CC_OP_DECL:

   924     case CC_OP_DECQ:

   925 

   926     case CC_OP_SHLB:

   927     case CC_OP_SHLW:

   928     case CC_OP_SHLL:

   929     case CC_OP_SHLQ:

   930         if (jcc_op != JCC_Z && jcc_op != JCC_S)

   931             goto slow_jcc;

   932         break;

   933     default:

   934     slow_jcc:

   935         return 0;

   936     }

   937     return 1;

   938 }

   939 

   940 /* generate a conditional jump to label 'l1' according to jump opcode

   941    value 'b'. In the fast case, T0 is guaranted not to be used. */

   942 static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1)

   943 {

   944     int inv, jcc_op, size, cond;

   945     TCGv t0;

   946 

   947     inv = b & 1;

   948     jcc_op = (b >> 1) & 7;

   949 

   950     switch(cc_op) {

   951         /* we optimize the cmp/jcc case */

   952     case CC_OP_SUBB:

   953     case CC_OP_SUBW:

   954     case CC_OP_SUBL:

   955     case CC_OP_SUBQ:

   956         

   957         size = cc_op - CC_OP_SUBB;

   958         switch(jcc_op) {

   959         case JCC_Z:

   960         fast_jcc_z:

   961             switch(size) {

   962             case 0:

   963                 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff);

   964                 t0 = cpu_tmp0;

   965                 break;

   966             case 1:

   967                 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff);

   968                 t0 = cpu_tmp0;

   969                 break;

   970 #ifdef TARGET_X86_64

   971             case 2:

   972                 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff);

   973                 t0 = cpu_tmp0;

   974                 break;

   975 #endif

   976             default:

   977                 t0 = cpu_cc_dst;

   978                 break;

   979             }

   980             tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1);

   981             break;

   982         case JCC_S:

   983         fast_jcc_s:

   984             switch(size) {

   985             case 0:

   986                 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80);

   987                 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, 

   988                                    0, l1);

   989                 break;

   990             case 1:

   991                 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000);

   992                 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, 

   993                                    0, l1);

   994                 break;

   995 #ifdef TARGET_X86_64

   996             case 2:

   997                 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000);

   998                 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, 

   999                                    0, l1);

  1000                 break;

  1001 #endif

  1002             default:

  1003                 tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst, 

  1004                                    0, l1);

  1005                 break;

  1006             }

  1007             break;

  1008             

  1009         case JCC_B:

  1010             cond = inv ? TCG_COND_GEU : TCG_COND_LTU;

  1011             goto fast_jcc_b;

  1012         case JCC_BE:

  1013             cond = inv ? TCG_COND_GTU : TCG_COND_LEU;

  1014         fast_jcc_b:

  1015             tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);

  1016             switch(size) {

  1017             case 0:

  1018                 t0 = cpu_tmp0;

  1019                 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xff);

  1020                 tcg_gen_andi_tl(t0, cpu_cc_src, 0xff);

  1021                 break;

  1022             case 1:

  1023                 t0 = cpu_tmp0;

  1024                 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffff);

  1025                 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffff);

  1026                 break;

  1027 #ifdef TARGET_X86_64

  1028             case 2:

  1029                 t0 = cpu_tmp0;

  1030                 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffffffff);

  1031                 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffffffff);

  1032                 break;

  1033 #endif

  1034             default:

  1035                 t0 = cpu_cc_src;

  1036                 break;

  1037             }

  1038             tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);

  1039             break;

  1040             

  1041         case JCC_L:

  1042             cond = inv ? TCG_COND_GE : TCG_COND_LT;

  1043             goto fast_jcc_l;

  1044         case JCC_LE:

  1045             cond = inv ? TCG_COND_GT : TCG_COND_LE;

  1046         fast_jcc_l:

  1047             tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);

  1048             switch(size) {

  1049             case 0:

  1050                 t0 = cpu_tmp0;

  1051                 tcg_gen_ext8s_tl(cpu_tmp4, cpu_tmp4);

  1052                 tcg_gen_ext8s_tl(t0, cpu_cc_src);

  1053                 break;

  1054             case 1:

  1055                 t0 = cpu_tmp0;

  1056                 tcg_gen_ext16s_tl(cpu_tmp4, cpu_tmp4);

  1057                 tcg_gen_ext16s_tl(t0, cpu_cc_src);

  1058                 break;

  1059 #ifdef TARGET_X86_64

  1060             case 2:

  1061                 t0 = cpu_tmp0;

  1062                 tcg_gen_ext32s_tl(cpu_tmp4, cpu_tmp4);

  1063                 tcg_gen_ext32s_tl(t0, cpu_cc_src);

  1064                 break;

  1065 #endif

  1066             default:

  1067                 t0 = cpu_cc_src;

  1068                 break;

  1069             }

  1070             tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);

  1071             break;

  1072             

  1073         default:

  1074             goto slow_jcc;

  1075         }

  1076         break;

  1077         

  1078         /* some jumps are easy to compute */

  1079     case CC_OP_ADDB:

  1080     case CC_OP_ADDW:

  1081     case CC_OP_ADDL:

  1082     case CC_OP_ADDQ:

  1083         

  1084     case CC_OP_ADCB:

  1085     case CC_OP_ADCW:

  1086     case CC_OP_ADCL:

  1087     case CC_OP_ADCQ:

  1088         

  1089     case CC_OP_SBBB:

  1090     case CC_OP_SBBW:

  1091     case CC_OP_SBBL:

  1092     case CC_OP_SBBQ:

  1093         

  1094     case CC_OP_LOGICB:

  1095     case CC_OP_LOGICW:

  1096     case CC_OP_LOGICL:

  1097     case CC_OP_LOGICQ:

  1098         

  1099     case CC_OP_INCB:

  1100     case CC_OP_INCW:

  1101     case CC_OP_INCL:

  1102     case CC_OP_INCQ:

  1103         

  1104     case CC_OP_DECB:

  1105     case CC_OP_DECW:

  1106     case CC_OP_DECL:

  1107     case CC_OP_DECQ:

  1108         

  1109     case CC_OP_SHLB:

  1110     case CC_OP_SHLW:

  1111     case CC_OP_SHLL:

  1112     case CC_OP_SHLQ:

  1113         

  1114     case CC_OP_SARB:

  1115     case CC_OP_SARW:

  1116     case CC_OP_SARL:

  1117     case CC_OP_SARQ:

  1118         switch(jcc_op) {

  1119         case JCC_Z:

  1120             size = (cc_op - CC_OP_ADDB) & 3;

  1121             goto fast_jcc_z;

  1122         case JCC_S:

  1123             size = (cc_op - CC_OP_ADDB) & 3;

  1124             goto fast_jcc_s;

  1125         default:

  1126             goto slow_jcc;

  1127         }

  1128         break;

  1129     default:

  1130     slow_jcc:

  1131         gen_setcc_slow_T0(s, jcc_op);

  1132         tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, 

  1133                            cpu_T[0], 0, l1);

  1134         break;

  1135     }