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1 #if !defined (__QEMU_MIPS_DEFS_H__) |
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2 #define __QEMU_MIPS_DEFS_H__ |
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3 |
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4 /* If we want to use host float regs... */ |
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5 //#define USE_HOST_FLOAT_REGS |
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6 |
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7 /* Real pages are variable size... */ |
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8 #define TARGET_PAGE_BITS 12 |
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9 #define MIPS_TLB_MAX 128 |
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10 |
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11 #if defined(TARGET_MIPS64) |
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12 #define TARGET_LONG_BITS 64 |
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13 #else |
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14 #define TARGET_LONG_BITS 32 |
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15 #endif |
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16 |
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17 /* Even MIPS32 can have 36 bits physical address space. */ |
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18 #define TARGET_PHYS_ADDR_BITS 64 |
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19 |
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20 /* Masks used to mark instructions to indicate which ISA level they |
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21 were introduced in. */ |
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22 #define ISA_MIPS1 0x00000001 |
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23 #define ISA_MIPS2 0x00000002 |
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24 #define ISA_MIPS3 0x00000004 |
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25 #define ISA_MIPS4 0x00000008 |
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26 #define ISA_MIPS5 0x00000010 |
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27 #define ISA_MIPS32 0x00000020 |
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28 #define ISA_MIPS32R2 0x00000040 |
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29 #define ISA_MIPS64 0x00000080 |
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30 #define ISA_MIPS64R2 0x00000100 |
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31 |
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32 /* MIPS ASEs. */ |
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33 #define ASE_MIPS16 0x00001000 |
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34 #define ASE_MIPS3D 0x00002000 |
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35 #define ASE_MDMX 0x00004000 |
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36 #define ASE_DSP 0x00008000 |
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37 #define ASE_DSPR2 0x00010000 |
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38 #define ASE_MT 0x00020000 |
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39 #define ASE_SMARTMIPS 0x00040000 |
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40 |
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41 /* Chip specific instructions. */ |
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42 #define INSN_VR54XX 0x80000000 |
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43 |
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44 /* MIPS CPU defines. */ |
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45 #define CPU_MIPS1 (ISA_MIPS1) |
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46 #define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2) |
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47 #define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) |
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48 #define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) |
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49 #define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) |
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50 |
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51 #define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) |
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52 |
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53 /* MIPS Technologies "Release 1" */ |
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54 #define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) |
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55 #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) |
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56 |
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57 /* MIPS Technologies "Release 2" */ |
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58 #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) |
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59 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) |
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60 |
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61 /* Strictly follow the architecture standard: |
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62 - Disallow "special" instruction handling for PMON/SPIM. |
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63 Note that we still maintain Count/Compare to match the host clock. */ |
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64 //#define MIPS_STRICT_STANDARD 1 |
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65 |
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66 #endif /* !defined (__QEMU_MIPS_DEFS_H__) */ |