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1 /* |
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2 * SH4 emulation |
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3 * |
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4 * Copyright (c) 2005 Samuel Tardieu |
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5 * |
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6 * This library is free software; you can redistribute it and/or |
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7 * modify it under the terms of the GNU Lesser General Public |
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8 * License as published by the Free Software Foundation; either |
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9 * version 2 of the License, or (at your option) any later version. |
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10 * |
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11 * This library is distributed in the hope that it will be useful, |
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 * Lesser General Public License for more details. |
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15 * |
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16 * You should have received a copy of the GNU Lesser General Public |
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17 * License along with this library; if not, write to the Free Software |
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18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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19 */ |
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20 #ifndef _CPU_SH4_H |
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21 #define _CPU_SH4_H |
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22 |
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23 #include "config.h" |
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24 |
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25 #define TARGET_LONG_BITS 32 |
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26 #define TARGET_HAS_ICE 1 |
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27 |
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28 #define ELF_MACHINE EM_SH |
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29 |
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30 /* CPU Subtypes */ |
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31 #define SH_CPU_SH7750 (1 << 0) |
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32 #define SH_CPU_SH7750S (1 << 1) |
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33 #define SH_CPU_SH7750R (1 << 2) |
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34 #define SH_CPU_SH7751 (1 << 3) |
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35 #define SH_CPU_SH7751R (1 << 4) |
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36 #define SH_CPU_SH7785 (1 << 5) |
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37 #define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R) |
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38 #define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R) |
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39 |
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40 #include "cpu-defs.h" |
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41 |
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42 #include "softfloat.h" |
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43 |
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44 #define TARGET_PAGE_BITS 12 /* 4k XXXXX */ |
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45 |
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46 #define SR_MD (1 << 30) |
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47 #define SR_RB (1 << 29) |
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48 #define SR_BL (1 << 28) |
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49 #define SR_FD (1 << 15) |
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50 #define SR_M (1 << 9) |
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51 #define SR_Q (1 << 8) |
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52 #define SR_I3 (1 << 7) |
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53 #define SR_I2 (1 << 6) |
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54 #define SR_I1 (1 << 5) |
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55 #define SR_I0 (1 << 4) |
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56 #define SR_S (1 << 1) |
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57 #define SR_T (1 << 0) |
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58 |
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59 #define FPSCR_FR (1 << 21) |
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60 #define FPSCR_SZ (1 << 20) |
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61 #define FPSCR_PR (1 << 19) |
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62 #define FPSCR_DN (1 << 18) |
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63 #define DELAY_SLOT (1 << 0) |
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64 #define DELAY_SLOT_CONDITIONAL (1 << 1) |
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65 #define DELAY_SLOT_TRUE (1 << 2) |
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66 #define DELAY_SLOT_CLEARME (1 << 3) |
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67 /* The dynamic value of the DELAY_SLOT_TRUE flag determines whether the jump |
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68 * after the delay slot should be taken or not. It is calculated from SR_T. |
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69 * |
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70 * It is unclear if it is permitted to modify the SR_T flag in a delay slot. |
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71 * The use of DELAY_SLOT_TRUE flag makes us accept such SR_T modification. |
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72 */ |
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73 |
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74 /* XXXXX The structure could be made more compact */ |
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75 typedef struct tlb_t { |
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76 uint8_t asid; /* address space identifier */ |
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77 uint32_t vpn; /* virtual page number */ |
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78 uint8_t v; /* validity */ |
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79 uint32_t ppn; /* physical page number */ |
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80 uint8_t sz; /* page size */ |
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81 uint32_t size; /* cached page size in bytes */ |
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82 uint8_t sh; /* share status */ |
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83 uint8_t c; /* cacheability */ |
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84 uint8_t pr; /* protection key */ |
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85 uint8_t d; /* dirty */ |
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86 uint8_t wt; /* write through */ |
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87 uint8_t sa; /* space attribute (PCMCIA) */ |
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88 uint8_t tc; /* timing control */ |
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89 } tlb_t; |
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90 |
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91 #define UTLB_SIZE 64 |
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92 #define ITLB_SIZE 4 |
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93 |
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94 #define NB_MMU_MODES 2 |
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95 |
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96 enum sh_features { |
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97 SH_FEATURE_SH4A = 1, |
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98 }; |
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99 |
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100 typedef struct CPUSH4State { |
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101 int id; /* CPU model */ |
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102 |
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103 uint32_t flags; /* general execution flags */ |
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104 uint32_t gregs[24]; /* general registers */ |
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105 float32 fregs[32]; /* floating point registers */ |
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106 uint32_t sr; /* status register */ |
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107 uint32_t ssr; /* saved status register */ |
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108 uint32_t spc; /* saved program counter */ |
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109 uint32_t gbr; /* global base register */ |
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110 uint32_t vbr; /* vector base register */ |
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111 uint32_t sgr; /* saved global register 15 */ |
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112 uint32_t dbr; /* debug base register */ |
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113 uint32_t pc; /* program counter */ |
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114 uint32_t delayed_pc; /* target of delayed jump */ |
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115 uint32_t mach; /* multiply and accumulate high */ |
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116 uint32_t macl; /* multiply and accumulate low */ |
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117 uint32_t pr; /* procedure register */ |
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118 uint32_t fpscr; /* floating point status/control register */ |
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119 uint32_t fpul; /* floating point communication register */ |
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120 |
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121 /* float point status register */ |
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122 float_status fp_status; |
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123 |
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124 /* The features that we should emulate. See sh_features above. */ |
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125 uint32_t features; |
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126 |
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127 /* Those belong to the specific unit (SH7750) but are handled here */ |
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128 uint32_t mmucr; /* MMU control register */ |
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129 uint32_t pteh; /* page table entry high register */ |
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130 uint32_t ptel; /* page table entry low register */ |
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131 uint32_t ptea; /* page table entry assistance register */ |
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132 uint32_t ttb; /* tranlation table base register */ |
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133 uint32_t tea; /* TLB exception address register */ |
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134 uint32_t tra; /* TRAPA exception register */ |
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135 uint32_t expevt; /* exception event register */ |
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136 uint32_t intevt; /* interrupt event register */ |
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137 |
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138 uint32_t pvr; /* Processor Version Register */ |
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139 uint32_t prr; /* Processor Revision Register */ |
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140 uint32_t cvr; /* Cache Version Register */ |
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141 |
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142 CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */ |
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143 tlb_t itlb[ITLB_SIZE]; /* instruction translation table */ |
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144 void *intc_handle; |
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145 int intr_at_halt; /* SR_BL ignored during sleep */ |
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146 } CPUSH4State; |
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147 |
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148 CPUSH4State *cpu_sh4_init(const char *cpu_model); |
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149 int cpu_sh4_exec(CPUSH4State * s); |
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150 int cpu_sh4_signal_handler(int host_signum, void *pinfo, |
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151 void *puc); |
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152 int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw, |
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153 int mmu_idx, int is_softmmu); |
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154 void do_interrupt(CPUSH4State * env); |
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155 |
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156 void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
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157 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr, |
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158 uint32_t mem_value); |
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159 |
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160 static inline void cpu_set_tls(CPUSH4State *env, target_ulong newtls) |
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161 { |
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162 env->gbr = newtls; |
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163 } |
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164 |
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165 #include "softfloat.h" |
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166 |
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167 #define CPUState CPUSH4State |
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168 #define cpu_init cpu_sh4_init |
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169 #define cpu_exec cpu_sh4_exec |
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170 #define cpu_gen_code cpu_sh4_gen_code |
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171 #define cpu_signal_handler cpu_sh4_signal_handler |
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172 #define cpu_list sh4_cpu_list |
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173 |
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174 /* MMU modes definitions */ |
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175 #define MMU_MODE0_SUFFIX _kernel |
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176 #define MMU_MODE1_SUFFIX _user |
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177 #define MMU_USER_IDX 1 |
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178 static inline int cpu_mmu_index (CPUState *env) |
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179 { |
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180 return (env->sr & SR_MD) == 0 ? 1 : 0; |
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181 } |
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182 |
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183 #if defined(CONFIG_USER_ONLY) |
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184 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
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185 { |
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186 if (newsp) |
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187 env->gregs[15] = newsp; |
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188 env->gregs[0] = 0; |
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189 } |
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190 #endif |
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191 |
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192 #include "cpu-all.h" |
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193 #include "exec-all.h" |
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194 |
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195 /* Memory access type */ |
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196 enum { |
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197 /* Privilege */ |
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198 ACCESS_PRIV = 0x01, |
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199 /* Direction */ |
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200 ACCESS_WRITE = 0x02, |
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201 /* Type of instruction */ |
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202 ACCESS_CODE = 0x10, |
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203 ACCESS_INT = 0x20 |
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204 }; |
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205 |
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206 /* MMU control register */ |
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207 #define MMUCR 0x1F000010 |
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208 #define MMUCR_AT (1<<0) |
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209 #define MMUCR_SV (1<<8) |
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210 #define MMUCR_URC_BITS (6) |
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211 #define MMUCR_URC_OFFSET (10) |
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212 #define MMUCR_URC_SIZE (1 << MMUCR_URC_BITS) |
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213 #define MMUCR_URC_MASK (((MMUCR_URC_SIZE) - 1) << MMUCR_URC_OFFSET) |
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214 static inline int cpu_mmucr_urc (uint32_t mmucr) |
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215 { |
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216 return ((mmucr & MMUCR_URC_MASK) >> MMUCR_URC_OFFSET); |
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217 } |
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218 |
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219 /* PTEH : Page Translation Entry High register */ |
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220 #define PTEH_ASID_BITS (8) |
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221 #define PTEH_ASID_SIZE (1 << PTEH_ASID_BITS) |
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222 #define PTEH_ASID_MASK (PTEH_ASID_SIZE - 1) |
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223 #define cpu_pteh_asid(pteh) ((pteh) & PTEH_ASID_MASK) |
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224 #define PTEH_VPN_BITS (22) |
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225 #define PTEH_VPN_OFFSET (10) |
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226 #define PTEH_VPN_SIZE (1 << PTEH_VPN_BITS) |
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227 #define PTEH_VPN_MASK (((PTEH_VPN_SIZE) - 1) << PTEH_VPN_OFFSET) |
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228 static inline int cpu_pteh_vpn (uint32_t pteh) |
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229 { |
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230 return ((pteh & PTEH_VPN_MASK) >> PTEH_VPN_OFFSET); |
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231 } |
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232 |
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233 /* PTEL : Page Translation Entry Low register */ |
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234 #define PTEL_V (1 << 8) |
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235 #define cpu_ptel_v(ptel) (((ptel) & PTEL_V) >> 8) |
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236 #define PTEL_C (1 << 3) |
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237 #define cpu_ptel_c(ptel) (((ptel) & PTEL_C) >> 3) |
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238 #define PTEL_D (1 << 2) |
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239 #define cpu_ptel_d(ptel) (((ptel) & PTEL_D) >> 2) |
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240 #define PTEL_SH (1 << 1) |
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241 #define cpu_ptel_sh(ptel)(((ptel) & PTEL_SH) >> 1) |
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242 #define PTEL_WT (1 << 0) |
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243 #define cpu_ptel_wt(ptel) ((ptel) & PTEL_WT) |
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244 |
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245 #define PTEL_SZ_HIGH_OFFSET (7) |
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246 #define PTEL_SZ_HIGH (1 << PTEL_SZ_HIGH_OFFSET) |
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247 #define PTEL_SZ_LOW_OFFSET (4) |
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248 #define PTEL_SZ_LOW (1 << PTEL_SZ_LOW_OFFSET) |
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249 static inline int cpu_ptel_sz (uint32_t ptel) |
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250 { |
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251 int sz; |
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252 sz = (ptel & PTEL_SZ_HIGH) >> PTEL_SZ_HIGH_OFFSET; |
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253 sz <<= 1; |
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254 sz |= (ptel & PTEL_SZ_LOW) >> PTEL_SZ_LOW_OFFSET; |
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255 return sz; |
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256 } |
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257 |
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258 #define PTEL_PPN_BITS (19) |
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259 #define PTEL_PPN_OFFSET (10) |
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260 #define PTEL_PPN_SIZE (1 << PTEL_PPN_BITS) |
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261 #define PTEL_PPN_MASK (((PTEL_PPN_SIZE) - 1) << PTEL_PPN_OFFSET) |
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262 static inline int cpu_ptel_ppn (uint32_t ptel) |
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263 { |
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264 return ((ptel & PTEL_PPN_MASK) >> PTEL_PPN_OFFSET); |
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265 } |
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266 |
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267 #define PTEL_PR_BITS (2) |
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268 #define PTEL_PR_OFFSET (5) |
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269 #define PTEL_PR_SIZE (1 << PTEL_PR_BITS) |
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270 #define PTEL_PR_MASK (((PTEL_PR_SIZE) - 1) << PTEL_PR_OFFSET) |
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271 static inline int cpu_ptel_pr (uint32_t ptel) |
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272 { |
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273 return ((ptel & PTEL_PR_MASK) >> PTEL_PR_OFFSET); |
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274 } |
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275 |
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276 /* PTEA : Page Translation Entry Assistance register */ |
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277 #define PTEA_SA_BITS (3) |
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278 #define PTEA_SA_SIZE (1 << PTEA_SA_BITS) |
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279 #define PTEA_SA_MASK (PTEA_SA_SIZE - 1) |
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280 #define cpu_ptea_sa(ptea) ((ptea) & PTEA_SA_MASK) |
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281 #define PTEA_TC (1 << 3) |
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282 #define cpu_ptea_tc(ptea) (((ptea) & PTEA_TC) >> 3) |
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283 |
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284 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |
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285 { |
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286 env->pc = tb->pc; |
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287 env->flags = tb->flags; |
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288 } |
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289 |
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290 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
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291 target_ulong *cs_base, int *flags) |
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292 { |
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293 *pc = env->pc; |
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294 *cs_base = 0; |
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295 *flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL |
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296 | DELAY_SLOT_TRUE | DELAY_SLOT_CLEARME)) /* Bits 0- 3 */ |
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297 | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */ |
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298 | (env->sr & (SR_MD | SR_RB)) /* Bits 29-30 */ |
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299 | (env->sr & SR_FD); /* Bit 15 */ |
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300 } |
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301 |
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302 #endif /* _CPU_SH4_H */ |