1 /*

     2    SPARC translation

     3 

     4    Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>

     5    Copyright (C) 2003-2005 Fabrice Bellard

     6 

     7    This library is free software; you can redistribute it and/or

     8    modify it under the terms of the GNU Lesser General Public

     9    License as published by the Free Software Foundation; either

    10    version 2 of the License, or (at your option) any later version.

    11 

    12    This library is distributed in the hope that it will be useful,

    13    but WITHOUT ANY WARRANTY; without even the implied warranty of

    14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

    15    Lesser General Public License for more details.

    16 

    17    You should have received a copy of the GNU Lesser General Public

    18    License along with this library; if not, write to the Free Software

    19    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

    20  */

    21 

    22 #include <stdarg.h>

    23 #include <stdlib.h>

    24 #include <stdio.h>

    25 #include <string.h>

    26 #include <inttypes.h>

    27 

    28 #include "cpu.h"

    29 #include "exec-all.h"

    30 #include "disas.h"

    31 #include "helper.h"

    32 #include "tcg-op.h"

    33 

    34 #define GEN_HELPER 1

    35 #include "helper.h"

    36 

    37 #define DEBUG_DISAS

    38 

    39 #define DYNAMIC_PC  1 /* dynamic pc value */

    40 #define JUMP_PC     2 /* dynamic pc value which takes only two values

    41                          according to jump_pc[T2] */

    42 

    43 /* global register indexes */

    44 static TCGv_ptr cpu_env, cpu_regwptr;

    45 static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst;

    46 static TCGv_i32 cpu_psr;

    47 static TCGv cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];

    48 static TCGv cpu_y;

    49 #ifndef CONFIG_USER_ONLY

    50 static TCGv cpu_tbr;

    51 #endif

    52 static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;

    53 #ifdef TARGET_SPARC64

    54 static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;

    55 static TCGv cpu_gsr;

    56 static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;

    57 static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;

    58 static TCGv_i32 cpu_softint;

    59 #else

    60 static TCGv cpu_wim;

    61 #endif

    62 /* local register indexes (only used inside old micro ops) */

    63 static TCGv cpu_tmp0;

    64 static TCGv_i32 cpu_tmp32;

    65 static TCGv_i64 cpu_tmp64;

    66 /* Floating point registers */

    67 static TCGv_i32 cpu_fpr[TARGET_FPREGS];

    68 

    69 #include "gen-icount.h"

    70 

    71 typedef struct DisasContext {

    72     target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */

    73     target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */

    74     target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */

    75     int is_br;

    76     int mem_idx;

    77     int fpu_enabled;

    78     int address_mask_32bit;

    79     struct TranslationBlock *tb;

    80     sparc_def_t *def;

    81 } DisasContext;

    82 

    83 // This function uses non-native bit order

    84 #define GET_FIELD(X, FROM, TO) \

    85   ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))

    86 

    87 // This function uses the order in the manuals, i.e. bit 0 is 2^0

    88 #define GET_FIELD_SP(X, FROM, TO) \

    89     GET_FIELD(X, 31 - (TO), 31 - (FROM))

    90 

    91 #define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)

    92 #define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))

    93 

    94 #ifdef TARGET_SPARC64

    95 #define FFPREG(r) (r)

    96 #define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))

    97 #define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))

    98 #else

    99 #define FFPREG(r) (r)

   100 #define DFPREG(r) (r & 0x1e)

   101 #define QFPREG(r) (r & 0x1c)

   102 #endif

   103 

   104 #define UA2005_HTRAP_MASK 0xff

   105 #define V8_TRAP_MASK 0x7f

   106 

   107 static int sign_extend(int x, int len)

   108 {

   109     len = 32 - len;

   110     return (x << len) >> len;

   111 }

   112 

   113 #define IS_IMM (insn & (1<<13))

   114 

   115 /* floating point registers moves */

   116 static void gen_op_load_fpr_DT0(unsigned int src)

   117 {

   118     tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt0) +

   119                    offsetof(CPU_DoubleU, l.upper));

   120     tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt0) +

   121                    offsetof(CPU_DoubleU, l.lower));

   122 }

   123 

   124 static void gen_op_load_fpr_DT1(unsigned int src)

   125 {

   126     tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, dt1) +

   127                    offsetof(CPU_DoubleU, l.upper));

   128     tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, dt1) +

   129                    offsetof(CPU_DoubleU, l.lower));

   130 }

   131 

   132 static void gen_op_store_DT0_fpr(unsigned int dst)

   133 {

   134     tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, dt0) +

   135                    offsetof(CPU_DoubleU, l.upper));

   136     tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, dt0) +

   137                    offsetof(CPU_DoubleU, l.lower));

   138 }

   139 

   140 static void gen_op_load_fpr_QT0(unsigned int src)

   141 {

   142     tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt0) +

   143                    offsetof(CPU_QuadU, l.upmost));

   144     tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt0) +

   145                    offsetof(CPU_QuadU, l.upper));

   146     tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt0) +

   147                    offsetof(CPU_QuadU, l.lower));

   148     tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt0) +

   149                    offsetof(CPU_QuadU, l.lowest));

   150 }

   151 

   152 static void gen_op_load_fpr_QT1(unsigned int src)

   153 {

   154     tcg_gen_st_i32(cpu_fpr[src], cpu_env, offsetof(CPUSPARCState, qt1) +

   155                    offsetof(CPU_QuadU, l.upmost));

   156     tcg_gen_st_i32(cpu_fpr[src + 1], cpu_env, offsetof(CPUSPARCState, qt1) +

   157                    offsetof(CPU_QuadU, l.upper));

   158     tcg_gen_st_i32(cpu_fpr[src + 2], cpu_env, offsetof(CPUSPARCState, qt1) +

   159                    offsetof(CPU_QuadU, l.lower));

   160     tcg_gen_st_i32(cpu_fpr[src + 3], cpu_env, offsetof(CPUSPARCState, qt1) +

   161                    offsetof(CPU_QuadU, l.lowest));

   162 }

   163 

   164 static void gen_op_store_QT0_fpr(unsigned int dst)

   165 {

   166     tcg_gen_ld_i32(cpu_fpr[dst], cpu_env, offsetof(CPUSPARCState, qt0) +

   167                    offsetof(CPU_QuadU, l.upmost));

   168     tcg_gen_ld_i32(cpu_fpr[dst + 1], cpu_env, offsetof(CPUSPARCState, qt0) +

   169                    offsetof(CPU_QuadU, l.upper));

   170     tcg_gen_ld_i32(cpu_fpr[dst + 2], cpu_env, offsetof(CPUSPARCState, qt0) +

   171                    offsetof(CPU_QuadU, l.lower));

   172     tcg_gen_ld_i32(cpu_fpr[dst + 3], cpu_env, offsetof(CPUSPARCState, qt0) +

   173                    offsetof(CPU_QuadU, l.lowest));

   174 }

   175 

   176 /* moves */

   177 #ifdef CONFIG_USER_ONLY

   178 #define supervisor(dc) 0

   179 #ifdef TARGET_SPARC64

   180 #define hypervisor(dc) 0

   181 #endif

   182 #else

   183 #define supervisor(dc) (dc->mem_idx >= 1)

   184 #ifdef TARGET_SPARC64

   185 #define hypervisor(dc) (dc->mem_idx == 2)

   186 #else

   187 #endif

   188 #endif

   189 

   190 #ifdef TARGET_SPARC64

   191 #ifndef TARGET_ABI32

   192 #define AM_CHECK(dc) ((dc)->address_mask_32bit)

   193 #else

   194 #define AM_CHECK(dc) (1)

   195 #endif

   196 #endif

   197 

   198 static inline void gen_address_mask(DisasContext *dc, TCGv addr)

   199 {

   200 #ifdef TARGET_SPARC64

   201     if (AM_CHECK(dc))

   202         tcg_gen_andi_tl(addr, addr, 0xffffffffULL);

   203 #endif

   204 }

   205 

   206 static inline void gen_movl_reg_TN(int reg, TCGv tn)

   207 {

   208     if (reg == 0)

   209         tcg_gen_movi_tl(tn, 0);

   210     else if (reg < 8)

   211         tcg_gen_mov_tl(tn, cpu_gregs[reg]);

   212     else {

   213         tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));

   214     }

   215 }

   216 

   217 static inline void gen_movl_TN_reg(int reg, TCGv tn)

   218 {

   219     if (reg == 0)

   220         return;

   221     else if (reg < 8)

   222         tcg_gen_mov_tl(cpu_gregs[reg], tn);

   223     else {

   224         tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));

   225     }

   226 }

   227 

   228 static inline void gen_goto_tb(DisasContext *s, int tb_num,

   229                                target_ulong pc, target_ulong npc)

   230 {

   231     TranslationBlock *tb;

   232 

   233     tb = s->tb;

   234     if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&

   235         (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK))  {

   236         /* jump to same page: we can use a direct jump */

   237         tcg_gen_goto_tb(tb_num);

   238         tcg_gen_movi_tl(cpu_pc, pc);

   239         tcg_gen_movi_tl(cpu_npc, npc);

   240         tcg_gen_exit_tb((long)tb + tb_num);

   241     } else {

   242         /* jump to another page: currently not optimized */

   243         tcg_gen_movi_tl(cpu_pc, pc);

   244         tcg_gen_movi_tl(cpu_npc, npc);

   245         tcg_gen_exit_tb(0);

   246     }

   247 }

   248 

   249 // XXX suboptimal

   250 static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src)

   251 {

   252     tcg_gen_extu_i32_tl(reg, src);

   253     tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT);

   254     tcg_gen_andi_tl(reg, reg, 0x1);

   255 }

   256 

   257 static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src)

   258 {

   259     tcg_gen_extu_i32_tl(reg, src);

   260     tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT);

   261     tcg_gen_andi_tl(reg, reg, 0x1);

   262 }

   263 

   264 static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src)

   265 {

   266     tcg_gen_extu_i32_tl(reg, src);

   267     tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT);

   268     tcg_gen_andi_tl(reg, reg, 0x1);

   269 }

   270 

   271 static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)

   272 {

   273     tcg_gen_extu_i32_tl(reg, src);

   274     tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT);

   275     tcg_gen_andi_tl(reg, reg, 0x1);

   276 }

   277 

   278 static inline void gen_cc_clear_icc(void)

   279 {

   280     tcg_gen_movi_i32(cpu_psr, 0);

   281 }

   282 

   283 #ifdef TARGET_SPARC64

   284 static inline void gen_cc_clear_xcc(void)

   285 {

   286     tcg_gen_movi_i32(cpu_xcc, 0);

   287 }

   288 #endif

   289 

   290 /* old op:

   291     if (!T0)

   292         env->psr |= PSR_ZERO;

   293     if ((int32_t) T0 < 0)

   294         env->psr |= PSR_NEG;

   295 */

   296 static inline void gen_cc_NZ_icc(TCGv dst)

   297 {

   298     TCGv r_temp;

   299     int l1, l2;

   300 

   301     l1 = gen_new_label();

   302     l2 = gen_new_label();

   303     r_temp = tcg_temp_new();

   304     tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);

   305     tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);

   306     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);

   307     gen_set_label(l1);

   308     tcg_gen_ext32s_tl(r_temp, dst);

   309     tcg_gen_brcondi_tl(TCG_COND_GE, r_temp, 0, l2);

   310     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);

   311     gen_set_label(l2);

   312     tcg_temp_free(r_temp);

   313 }

   314 

   315 #ifdef TARGET_SPARC64

   316 static inline void gen_cc_NZ_xcc(TCGv dst)

   317 {

   318     int l1, l2;

   319 

   320     l1 = gen_new_label();

   321     l2 = gen_new_label();

   322     tcg_gen_brcondi_tl(TCG_COND_NE, dst, 0, l1);

   323     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);

   324     gen_set_label(l1);

   325     tcg_gen_brcondi_tl(TCG_COND_GE, dst, 0, l2);

   326     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);

   327     gen_set_label(l2);

   328 }

   329 #endif

   330 

   331 /* old op:

   332     if (T0 < src1)

   333         env->psr |= PSR_CARRY;

   334 */

   335 static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)

   336 {

   337     TCGv r_temp1, r_temp2;

   338     int l1;

   339 

   340     l1 = gen_new_label();

   341     r_temp1 = tcg_temp_new();

   342     r_temp2 = tcg_temp_new();

   343     tcg_gen_andi_tl(r_temp1, dst, 0xffffffffULL);

   344     tcg_gen_andi_tl(r_temp2, src1, 0xffffffffULL);

   345     tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);

   346     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);

   347     gen_set_label(l1);

   348     tcg_temp_free(r_temp1);

   349     tcg_temp_free(r_temp2);

   350 }

   351 

   352 #ifdef TARGET_SPARC64

   353 static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)

   354 {

   355     int l1;

   356 

   357     l1 = gen_new_label();

   358     tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);

   359     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);

   360     gen_set_label(l1);

   361 }

   362 #endif

   363 

   364 /* old op:

   365     if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))

   366         env->psr |= PSR_OVF;

   367 */

   368 static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)

   369 {

   370     TCGv r_temp;

   371 

   372     r_temp = tcg_temp_new();

   373     tcg_gen_xor_tl(r_temp, src1, src2);

   374     tcg_gen_not_tl(r_temp, r_temp);

   375     tcg_gen_xor_tl(cpu_tmp0, src1, dst);

   376     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);

   377     tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));

   378     tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);

   379     tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);

   380     tcg_temp_free(r_temp);

   381     tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);

   382 }

   383 

   384 #ifdef TARGET_SPARC64

   385 static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)

   386 {

   387     TCGv r_temp;

   388 

   389     r_temp = tcg_temp_new();

   390     tcg_gen_xor_tl(r_temp, src1, src2);

   391     tcg_gen_not_tl(r_temp, r_temp);

   392     tcg_gen_xor_tl(cpu_tmp0, src1, dst);

   393     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);

   394     tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));

   395     tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);

   396     tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);

   397     tcg_temp_free(r_temp);

   398     tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);

   399 }

   400 #endif

   401 

   402 static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)

   403 {

   404     TCGv r_temp;

   405     TCGv_i32 r_const;

   406     int l1;

   407 

   408     l1 = gen_new_label();

   409 

   410     r_temp = tcg_temp_new();

   411     tcg_gen_xor_tl(r_temp, src1, src2);

   412     tcg_gen_not_tl(r_temp, r_temp);

   413     tcg_gen_xor_tl(cpu_tmp0, src1, dst);

   414     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);

   415     tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));

   416     tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);

   417     r_const = tcg_const_i32(TT_TOVF);

   418     gen_helper_raise_exception(r_const);

   419     tcg_temp_free_i32(r_const);

   420     gen_set_label(l1);

   421     tcg_temp_free(r_temp);

   422 }

   423 

   424 static inline void gen_cc_V_tag(TCGv src1, TCGv src2)

   425 {

   426     int l1;

   427 

   428     l1 = gen_new_label();

   429     tcg_gen_or_tl(cpu_tmp0, src1, src2);

   430     tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);

   431     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);

   432     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);

   433     gen_set_label(l1);

   434 }

   435 

   436 static inline void gen_tag_tv(TCGv src1, TCGv src2)

   437 {

   438     int l1;

   439     TCGv_i32 r_const;

   440 

   441     l1 = gen_new_label();

   442     tcg_gen_or_tl(cpu_tmp0, src1, src2);

   443     tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);

   444     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);

   445     r_const = tcg_const_i32(TT_TOVF);

   446     gen_helper_raise_exception(r_const);

   447     tcg_temp_free_i32(r_const);

   448     gen_set_label(l1);

   449 }

   450 

   451 static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)

   452 {

   453     tcg_gen_mov_tl(cpu_cc_src, src1);

   454     tcg_gen_mov_tl(cpu_cc_src2, src2);

   455     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

   456     gen_cc_clear_icc();

   457     gen_cc_NZ_icc(cpu_cc_dst);

   458     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);

   459     gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

   460 #ifdef TARGET_SPARC64

   461     gen_cc_clear_xcc();

   462     gen_cc_NZ_xcc(cpu_cc_dst);

   463     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);

   464     gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

   465 #endif

   466     tcg_gen_mov_tl(dst, cpu_cc_dst);

   467 }

   468 

   469 static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)

   470 {

   471     tcg_gen_mov_tl(cpu_cc_src, src1);

   472     tcg_gen_mov_tl(cpu_cc_src2, src2);

   473     gen_mov_reg_C(cpu_tmp0, cpu_psr);

   474     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);

   475     gen_cc_clear_icc();

   476     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);

   477 #ifdef TARGET_SPARC64

   478     gen_cc_clear_xcc();

   479     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);

   480 #endif

   481     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);

   482     gen_cc_NZ_icc(cpu_cc_dst);

   483     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);

   484     gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

   485 #ifdef TARGET_SPARC64

   486     gen_cc_NZ_xcc(cpu_cc_dst);

   487     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);

   488     gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

   489 #endif

   490     tcg_gen_mov_tl(dst, cpu_cc_dst);

   491 }

   492 

   493 static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)

   494 {

   495     tcg_gen_mov_tl(cpu_cc_src, src1);

   496     tcg_gen_mov_tl(cpu_cc_src2, src2);

   497     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

   498     gen_cc_clear_icc();

   499     gen_cc_NZ_icc(cpu_cc_dst);

   500     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);

   501     gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

   502     gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);

   503 #ifdef TARGET_SPARC64

   504     gen_cc_clear_xcc();

   505     gen_cc_NZ_xcc(cpu_cc_dst);

   506     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);

   507     gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

   508 #endif

   509     tcg_gen_mov_tl(dst, cpu_cc_dst);

   510 }

   511 

   512 static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)

   513 {

   514     tcg_gen_mov_tl(cpu_cc_src, src1);

   515     tcg_gen_mov_tl(cpu_cc_src2, src2);

   516     gen_tag_tv(cpu_cc_src, cpu_cc_src2);

   517     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

   518     gen_add_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

   519     gen_cc_clear_icc();

   520     gen_cc_NZ_icc(cpu_cc_dst);

   521     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);

   522 #ifdef TARGET_SPARC64

   523     gen_cc_clear_xcc();

   524     gen_cc_NZ_xcc(cpu_cc_dst);

   525     gen_cc_C_add_xcc(cpu_cc_dst, cpu_cc_src);

   526     gen_cc_V_add_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

   527 #endif

   528     tcg_gen_mov_tl(dst, cpu_cc_dst);

   529 }

   530 

   531 /* old op:

   532     if (src1 < T1)

   533         env->psr |= PSR_CARRY;

   534 */

   535 static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)

   536 {

   537     TCGv r_temp1, r_temp2;

   538     int l1;

   539 

   540     l1 = gen_new_label();

   541     r_temp1 = tcg_temp_new();

   542     r_temp2 = tcg_temp_new();

   543     tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);

   544     tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);

   545     tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);

   546     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);

   547     gen_set_label(l1);

   548     tcg_temp_free(r_temp1);

   549     tcg_temp_free(r_temp2);

   550 }

   551 

   552 #ifdef TARGET_SPARC64

   553 static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)

   554 {

   555     int l1;

   556 

   557     l1 = gen_new_label();

   558     tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);

   559     tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);

   560     gen_set_label(l1);

   561 }

   562 #endif

   563 

   564 /* old op:

   565     if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))

   566         env->psr |= PSR_OVF;

   567 */

   568 static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)

   569 {

   570     TCGv r_temp;

   571 

   572     r_temp = tcg_temp_new();

   573     tcg_gen_xor_tl(r_temp, src1, src2);

   574     tcg_gen_xor_tl(cpu_tmp0, src1, dst);

   575     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);

   576     tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));

   577     tcg_gen_shri_tl(r_temp, r_temp, 31 - PSR_OVF_SHIFT);

   578     tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);

   579     tcg_gen_or_i32(cpu_psr, cpu_psr, cpu_tmp32);

   580     tcg_temp_free(r_temp);

   581 }

   582 

   583 #ifdef TARGET_SPARC64

   584 static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)

   585 {

   586     TCGv r_temp;

   587 

   588     r_temp = tcg_temp_new();

   589     tcg_gen_xor_tl(r_temp, src1, src2);

   590     tcg_gen_xor_tl(cpu_tmp0, src1, dst);

   591     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);

   592     tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));

   593     tcg_gen_shri_tl(r_temp, r_temp, 63 - PSR_OVF_SHIFT);

   594     tcg_gen_trunc_tl_i32(cpu_tmp32, r_temp);

   595     tcg_gen_or_i32(cpu_xcc, cpu_xcc, cpu_tmp32);

   596     tcg_temp_free(r_temp);

   597 }

   598 #endif

   599 

   600 static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)

   601 {

   602     TCGv r_temp;

   603     TCGv_i32 r_const;

   604     int l1;

   605 

   606     l1 = gen_new_label();

   607 

   608     r_temp = tcg_temp_new();

   609     tcg_gen_xor_tl(r_temp, src1, src2);

   610     tcg_gen_xor_tl(cpu_tmp0, src1, dst);

   611     tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);

   612     tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31));

   613     tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1);

   614     r_const = tcg_const_i32(TT_TOVF);

   615     gen_helper_raise_exception(r_const);

   616     tcg_temp_free_i32(r_const);

   617     gen_set_label(l1);

   618     tcg_temp_free(r_temp);

   619 }

   620 

   621 static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)

   622 {

   623     tcg_gen_mov_tl(cpu_cc_src, src1);

   624     tcg_gen_mov_tl(cpu_cc_src2, src2);

   625     tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

   626     gen_cc_clear_icc();

   627     gen_cc_NZ_icc(cpu_cc_dst);

   628     gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);

   629     gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

   630 #ifdef TARGET_SPARC64

   631     gen_cc_clear_xcc();

   632     gen_cc_NZ_xcc(cpu_cc_dst);

   633     gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);

   634     gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

   635 #endif

   636     tcg_gen_mov_tl(dst, cpu_cc_dst);

   637 }

   638 

   639 static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)

   640 {

   641     tcg_gen_mov_tl(cpu_cc_src, src1);

   642     tcg_gen_mov_tl(cpu_cc_src2, src2);

   643     gen_mov_reg_C(cpu_tmp0, cpu_psr);

   644     tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_tmp0);

   645     gen_cc_clear_icc();

   646     gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);

   647 #ifdef TARGET_SPARC64

   648     gen_cc_clear_xcc();

   649     gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);

   650 #endif

   651     tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_dst, cpu_cc_src2);

   652     gen_cc_NZ_icc(cpu_cc_dst);

   653     gen_cc_C_sub_icc(cpu_cc_dst, cpu_cc_src);

   654     gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

   655 #ifdef TARGET_SPARC64

   656     gen_cc_NZ_xcc(cpu_cc_dst);

   657     gen_cc_C_sub_xcc(cpu_cc_dst, cpu_cc_src);

   658     gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

   659 #endif

   660     tcg_gen_mov_tl(dst, cpu_cc_dst);

   661 }

   662 

   663 static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)

   664 {

   665     tcg_gen_mov_tl(cpu_cc_src, src1);

   666     tcg_gen_mov_tl(cpu_cc_src2, src2);

   667     tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

   668     gen_cc_clear_icc();

   669     gen_cc_NZ_icc(cpu_cc_dst);

   670     gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);

   671     gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

   672     gen_cc_V_tag(cpu_cc_src, cpu_cc_src2);

   673 #ifdef TARGET_SPARC64

   674     gen_cc_clear_xcc();

   675     gen_cc_NZ_xcc(cpu_cc_dst);

   676     gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);

   677     gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

   678 #endif

   679     tcg_gen_mov_tl(dst, cpu_cc_dst);

   680 }

   681 

   682 static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)

   683 {

   684     tcg_gen_mov_tl(cpu_cc_src, src1);

   685     tcg_gen_mov_tl(cpu_cc_src2, src2);

   686     gen_tag_tv(cpu_cc_src, cpu_cc_src2);

   687     tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

   688     gen_sub_tv(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

   689     gen_cc_clear_icc();

   690     gen_cc_NZ_icc(cpu_cc_dst);

   691     gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);

   692 #ifdef TARGET_SPARC64

   693     gen_cc_clear_xcc();

   694     gen_cc_NZ_xcc(cpu_cc_dst);

   695     gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);

   696     gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

   697 #endif

   698     tcg_gen_mov_tl(dst, cpu_cc_dst);

   699 }

   700 

   701 static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)

   702 {

   703     TCGv r_temp;

   704     int l1;

   705 

   706     l1 = gen_new_label();

   707     r_temp = tcg_temp_new();

   708 

   709     /* old op:

   710     if (!(env->y & 1))

   711         T1 = 0;

   712     */

   713     tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff);

   714     tcg_gen_andi_tl(r_temp, cpu_y, 0x1);

   715     tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff);

   716     tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1);

   717     tcg_gen_movi_tl(cpu_cc_src2, 0);

   718     gen_set_label(l1);

   719 

   720     // b2 = T0 & 1;

   721     // env->y = (b2 << 31) | (env->y >> 1);

   722     tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);

   723     tcg_gen_shli_tl(r_temp, r_temp, 31);

   724     tcg_gen_shri_tl(cpu_tmp0, cpu_y, 1);

   725     tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x7fffffff);

   726     tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp);

   727     tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);

   728 

   729     // b1 = N ^ V;

   730     gen_mov_reg_N(cpu_tmp0, cpu_psr);

   731     gen_mov_reg_V(r_temp, cpu_psr);

   732     tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);

   733     tcg_temp_free(r_temp);

   734 

   735     // T0 = (b1 << 31) | (T0 >> 1);

   736     // src1 = T0;

   737     tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);

   738     tcg_gen_shri_tl(cpu_cc_src, cpu_cc_src, 1);

   739     tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);

   740 

   741     /* do addition and update flags */

   742     tcg_gen_add_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

   743 

   744     gen_cc_clear_icc();

   745     gen_cc_NZ_icc(cpu_cc_dst);

   746     gen_cc_V_add_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);

   747     gen_cc_C_add_icc(cpu_cc_dst, cpu_cc_src);

   748     tcg_gen_mov_tl(dst, cpu_cc_dst);

   749 }

   750 

   751 static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)

   752 {

   753     TCGv_i64 r_temp, r_temp2;

   754 

   755     r_temp = tcg_temp_new_i64();

   756     r_temp2 = tcg_temp_new_i64();

   757 

   758     tcg_gen_extu_tl_i64(r_temp, src2);

   759     tcg_gen_extu_tl_i64(r_temp2, src1);

   760     tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);

   761 

   762     tcg_gen_shri_i64(r_temp, r_temp2, 32);

   763     tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp);

   764     tcg_temp_free_i64(r_temp);

   765     tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);

   766 #ifdef TARGET_SPARC64

   767     tcg_gen_mov_i64(dst, r_temp2);

   768 #else

   769     tcg_gen_trunc_i64_tl(dst, r_temp2);

   770 #endif

   771     tcg_temp_free_i64(r_temp2);

   772 }

   773 

   774 static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)

   775 {

   776     TCGv_i64 r_temp, r_temp2;

   777 

   778     r_temp = tcg_temp_new_i64();

   779     r_temp2 = tcg_temp_new_i64();

   780 

   781     tcg_gen_ext_tl_i64(r_temp, src2);

   782     tcg_gen_ext_tl_i64(r_temp2, src1);

   783     tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);

   784 

   785     tcg_gen_shri_i64(r_temp, r_temp2, 32);

   786     tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp);

   787     tcg_temp_free_i64(r_temp);

   788     tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);

   789 #ifdef TARGET_SPARC64

   790     tcg_gen_mov_i64(dst, r_temp2);

   791 #else

   792     tcg_gen_trunc_i64_tl(dst, r_temp2);

   793 #endif

   794     tcg_temp_free_i64(r_temp2);

   795 }

   796 

   797 #ifdef TARGET_SPARC64

   798 static inline void gen_trap_ifdivzero_tl(TCGv divisor)

   799 {

   800     TCGv_i32 r_const;

   801     int l1;

   802 

   803     l1 = gen_new_label();

   804     tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1);

   805     r_const = tcg_const_i32(TT_DIV_ZERO);

   806     gen_helper_raise_exception(r_const);

   807     tcg_temp_free_i32(r_const);

   808     gen_set_label(l1);

   809 }

   810 

   811 static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)

   812 {

   813     int l1, l2;

   814 

   815     l1 = gen_new_label();

   816     l2 = gen_new_label();

   817     tcg_gen_mov_tl(cpu_cc_src, src1);

   818     tcg_gen_mov_tl(cpu_cc_src2, src2);

   819     gen_trap_ifdivzero_tl(cpu_cc_src2);

   820     tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1);

   821     tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1);

   822     tcg_gen_movi_i64(dst, INT64_MIN);

   823     tcg_gen_br(l2);

   824     gen_set_label(l1);

   825     tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2);

   826     gen_set_label(l2);

   827 }

   828 #endif

   829 

   830 static inline void gen_op_div_cc(TCGv dst)

   831 {

   832     int l1;

   833 

   834     tcg_gen_mov_tl(cpu_cc_dst, dst);

   835     gen_cc_clear_icc();

   836     gen_cc_NZ_icc(cpu_cc_dst);

   837     l1 = gen_new_label();

   838     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_src2, 0, l1);

   839     tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);

   840     gen_set_label(l1);

   841 }

   842 

   843 static inline void gen_op_logic_cc(TCGv dst)

   844 {

   845     tcg_gen_mov_tl(cpu_cc_dst, dst);

   846 

   847     gen_cc_clear_icc();

   848     gen_cc_NZ_icc(cpu_cc_dst);

   849 #ifdef TARGET_SPARC64

   850     gen_cc_clear_xcc();

   851     gen_cc_NZ_xcc(cpu_cc_dst);

   852 #endif

   853 }

   854 

   855 // 1

   856 static inline void gen_op_eval_ba(TCGv dst)

   857 {

   858     tcg_gen_movi_tl(dst, 1);

   859 }

   860 

   861 // Z

   862 static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src)

   863 {

   864     gen_mov_reg_Z(dst, src);

   865 }

   866 

   867 // Z | (N ^ V)

   868 static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src)

   869 {

   870     gen_mov_reg_N(cpu_tmp0, src);

   871     gen_mov_reg_V(dst, src);

   872     tcg_gen_xor_tl(dst, dst, cpu_tmp0);

   873     gen_mov_reg_Z(cpu_tmp0, src);

   874     tcg_gen_or_tl(dst, dst, cpu_tmp0);

   875 }

   876 

   877 // N ^ V

   878 static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src)

   879 {

   880     gen_mov_reg_V(cpu_tmp0, src);

   881     gen_mov_reg_N(dst, src);

   882     tcg_gen_xor_tl(dst, dst, cpu_tmp0);

   883 }

   884 

   885 // C | Z

   886 static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src)

   887 {

   888     gen_mov_reg_Z(cpu_tmp0, src);

   889     gen_mov_reg_C(dst, src);

   890     tcg_gen_or_tl(dst, dst, cpu_tmp0);

   891 }

   892 

   893 // C

   894 static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src)

   895 {

   896     gen_mov_reg_C(dst, src);

   897 }

   898 

   899 // V

   900 static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src)

   901 {

   902     gen_mov_reg_V(dst, src);

   903 }

   904 

   905 // 0

   906 static inline void gen_op_eval_bn(TCGv dst)

   907 {

   908     tcg_gen_movi_tl(dst, 0);

   909 }

   910 

   911 // N

   912 static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src)

   913 {

   914     gen_mov_reg_N(dst, src);

   915 }

   916 

   917 // !Z

   918 static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src)

   919 {

   920     gen_mov_reg_Z(dst, src);

   921     tcg_gen_xori_tl(dst, dst, 0x1);

   922 }

   923 

   924 // !(Z | (N ^ V))

   925 static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src)

   926 {

   927     gen_mov_reg_N(cpu_tmp0, src);

   928     gen_mov_reg_V(dst, src);

   929     tcg_gen_xor_tl(dst, dst, cpu_tmp0);

   930     gen_mov_reg_Z(cpu_tmp0, src);

   931     tcg_gen_or_tl(dst, dst, cpu_tmp0);

   932     tcg_gen_xori_tl(dst, dst, 0x1);

   933 }

   934 

   935 // !(N ^ V)

   936 static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src)

   937 {

   938     gen_mov_reg_V(cpu_tmp0, src);

   939     gen_mov_reg_N(dst, src);

   940     tcg_gen_xor_tl(dst, dst, cpu_tmp0);

   941     tcg_gen_xori_tl(dst, dst, 0x1);

   942 }

   943 

   944 // !(C | Z)

   945 static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src)

   946 {

   947     gen_mov_reg_Z(cpu_tmp0, src);

   948     gen_mov_reg_C(dst, src);

   949     tcg_gen_or_tl(dst, dst, cpu_tmp0);

   950     tcg_gen_xori_tl(dst, dst, 0x1);

   951 }

   952 

   953 // !C

   954 static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src)

   955 {

   956     gen_mov_reg_C(dst, src);

   957     tcg_gen_xori_tl(dst, dst, 0x1);

   958 }

   959 

   960 // !N

   961 static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src)

   962 {

   963     gen_mov_reg_N(dst, src);

   964     tcg_gen_xori_tl(dst, dst, 0x1);

   965 }

   966 

   967 // !V

   968 static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src)

   969 {

   970     gen_mov_reg_V(dst, src);

   971     tcg_gen_xori_tl(dst, dst, 0x1);

   972 }

   973 

   974 /*

   975   FPSR bit field FCC1 | FCC0:

   976    0 =

   977    1 <

   978    2 >

   979    3 unordered

   980 */

   981 static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,

   982                                     unsigned int fcc_offset)

   983 {

   984     tcg_gen_shri_tl(reg, src, FSR_FCC0_SHIFT + fcc_offset);

   985     tcg_gen_andi_tl(reg, reg, 0x1);

   986 }

   987 

   988 static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,

   989                                     unsigned int fcc_offset)

   990 {

   991     tcg_gen_shri_tl(reg, src, FSR_FCC1_SHIFT + fcc_offset);

   992     tcg_gen_andi_tl(reg, reg, 0x1);

   993 }

   994 

   995 // !0: FCC0 | FCC1

   996 static inline void gen_op_eval_fbne(TCGv dst, TCGv src,

   997                                     unsigned int fcc_offset)

   998 {

   999     gen_mov_reg_FCC0(dst, src, fcc_offset);

  1000     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);

  1001     tcg_gen_or_tl(dst, dst, cpu_tmp0);

  1002 }

  1003 

  1004 // 1 or 2: FCC0 ^ FCC1

  1005 static inline void gen_op_eval_fblg(TCGv dst, TCGv src,

  1006                                     unsigned int fcc_offset)

  1007 {

  1008     gen_mov_reg_FCC0(dst, src, fcc_offset);

  1009     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);

  1010     tcg_gen_xor_tl(dst, dst, cpu_tmp0);

  1011 }

  1012 

  1013 // 1 or 3: FCC0

  1014 static inline void gen_op_eval_fbul(TCGv dst, TCGv src,

  1015                                     unsigned int fcc_offset)

  1016 {

  1017     gen_mov_reg_FCC0(dst, src, fcc_offset);

  1018 }

  1019 

  1020 // 1: FCC0 & !FCC1

  1021 static inline void gen_op_eval_fbl(TCGv dst, TCGv src,

  1022                                     unsigned int fcc_offset)

  1023 {

  1024     gen_mov_reg_FCC0(dst, src, fcc_offset);

  1025     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);

  1026     tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);

  1027     tcg_gen_and_tl(dst, dst, cpu_tmp0);

  1028 }

  1029 

  1030 // 2 or 3: FCC1

  1031 static inline void gen_op_eval_fbug(TCGv dst, TCGv src,

  1032                                     unsigned int fcc_offset)

  1033 {

  1034     gen_mov_reg_FCC1(dst, src, fcc_offset);

  1035 }

  1036 

  1037 // 2: !FCC0 & FCC1

  1038 static inline void gen_op_eval_fbg(TCGv dst, TCGv src,

  1039                                     unsigned int fcc_offset)

  1040 {

  1041     gen_mov_reg_FCC0(dst, src, fcc_offset);

  1042     tcg_gen_xori_tl(dst, dst, 0x1);

  1043     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);

  1044     tcg_gen_and_tl(dst, dst, cpu_tmp0);

  1045 }

  1046 

  1047 // 3: FCC0 & FCC1

  1048 static inline void gen_op_eval_fbu(TCGv dst, TCGv src,

  1049                                     unsigned int fcc_offset)

  1050 {

  1051     gen_mov_reg_FCC0(dst, src, fcc_offset);

  1052     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);

  1053     tcg_gen_and_tl(dst, dst, cpu_tmp0);

  1054 }

  1055 

  1056 // 0: !(FCC0 | FCC1)

  1057 static inline void gen_op_eval_fbe(TCGv dst, TCGv src,

  1058                                     unsigned int fcc_offset)

  1059 {

  1060     gen_mov_reg_FCC0(dst, src, fcc_offset);

  1061     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);

  1062     tcg_gen_or_tl(dst, dst, cpu_tmp0);

  1063     tcg_gen_xori_tl(dst, dst, 0x1);

  1064 }

  1065 

  1066 // 0 or 3: !(FCC0 ^ FCC1)

  1067 static inline void gen_op_eval_fbue(TCGv dst, TCGv src,

  1068                                     unsigned int fcc_offset)

  1069 {

  1070     gen_mov_reg_FCC0(dst, src, fcc_offset);

  1071     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);

  1072     tcg_gen_xor_tl(dst, dst, cpu_tmp0);

  1073     tcg_gen_xori_tl(dst, dst, 0x1);

  1074 }

  1075 

  1076 // 0 or 2: !FCC0

  1077 static inline void gen_op_eval_fbge(TCGv dst, TCGv src,

  1078                                     unsigned int fcc_offset)

  1079 {

  1080     gen_mov_reg_FCC0(dst, src, fcc_offset);

  1081     tcg_gen_xori_tl(dst, dst, 0x1);

  1082 }

  1083 

  1084 // !1: !(FCC0 & !FCC1)

  1085 static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,

  1086                                     unsigned int fcc_offset)

  1087 {

  1088     gen_mov_reg_FCC0(dst, src, fcc_offset);

  1089     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);

  1090     tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);

  1091     tcg_gen_and_tl(dst, dst, cpu_tmp0);

  1092     tcg_gen_xori_tl(dst, dst, 0x1);

  1093 }

  1094 

  1095 // 0 or 1: !FCC1

  1096 static inline void gen_op_eval_fble(TCGv dst, TCGv src,

  1097                                     unsigned int fcc_offset)

  1098 {

  1099     gen_mov_reg_FCC1(dst, src, fcc_offset);

  1100     tcg_gen_xori_tl(dst, dst, 0x1);

  1101 }

  1102 

  1103 // !2: !(!FCC0 & FCC1)

  1104 static inline void gen_op_eval_fbule(TCGv dst, TCGv src,

  1105                                     unsigned int fcc_offset)

  1106 {

  1107     gen_mov_reg_FCC0(dst, src, fcc_offset);

  1108     tcg_gen_xori_tl(dst, dst, 0x1);

  1109     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);

  1110     tcg_gen_and_tl(dst, dst, cpu_tmp0);

  1111     tcg_gen_xori_tl(dst, dst, 0x1);

  1112 }

  1113 

  1114 // !3: !(FCC0 & FCC1)

  1115 static inline void gen_op_eval_fbo(TCGv dst, TCGv src,

  1116                                     unsigned int fcc_offset)

  1117 {

  1118     gen_mov_reg_FCC0(dst, src, fcc_offset);

  1119     gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);

  1120     tcg_gen_and_tl(dst, dst, cpu_tmp0);

  1121     tcg_gen_xori_tl(dst, dst, 0x1);

  1122 }

  1123 

  1124 static inline void gen_branch2(DisasContext *dc, target_ulong pc1,

  1125                                target_ulong pc2, TCGv r_cond)

  1126 {

  1127     int l1;

  1128 

  1129     l1 = gen_new_label();

  1130 

  1131     tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1);

  1132 

  1133     gen_goto_tb(dc, 0, pc1, pc1 + 4);

  1134 

  1135     gen_set_label(l1);