SF Bug 1284 - QEMU has faulty instruction emulation for VMOV (between two ARM core registers and two single-precision registers)
- Add new instructions such as: andnot, ror, rol, setcond, clz, ctz,
popcnt.
- See if it is worth exporting mul2, mulu2, div2, divu2.
- Support of globals saved in fixed registers between TBs.
Ideas:
- Move the slow part of the qemu_ld/st ops after the end of the TB.
- Change exception syntax to get closer to QOP system (exception
parameters given with a specific instruction).
- Add float and vector support.